Control circuit, method and chip for an analog-to-digital converter

Abstract

The embodiment of the present application provides a kind of control circuit, method and chip of analog-digital converter, the circuit includes analog-digital converter, buffer, verification circuit and central processing unit, by analog-digital converter in channel conversion completion obtains first conversion result after generating conversion completion signal, verification circuit is based on conversion completion signal, whether the second conversion result currently stored in the register corresponding to channel has been read by central processing unit, if it has been read, write signal is generated, and first conversion result is written into register, if it has not been read, first conversion result and the channel number of the channel corresponding to first conversion result are stored to buffer, to avoid the situation that the second conversion result currently stored in the register is not read by central processing unit, in register, store first conversion result and cover the situation of unread second conversion result, the reliable storage of the conversion result data of analog-digital converter is realized.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a control circuit, method, and chip for an analog-to-digital converter. Background Technology

[0002] Analog-to-digital converters (ADCs) play a crucial role in modern electronic systems, their primary function being to convert analog signals into digital signals. ADCs typically have multiple conversion channels, enabling them to sample and convert multiple analog signals simultaneously or sequentially, thus meeting the multi-signal processing requirements of complex systems.

[0003] In common implementations, each ADC conversion channel is equipped with an independent register to store its own conversion result. While this design simplifies data management, it may expose some potential problems under high sampling rates or heavy system loads. Specifically, due to potential delays in the Central Processing Unit (CPU) while processing other tasks, it may be unable to read the current conversion result stored in the register in a timely manner. In this case, a new conversion result may be generated quickly and overwrite the current conversion result, leading to data loss or result corruption. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a control circuit, method and chip for an analog-to-digital converter that overcomes or at least partially solves the above problems.

[0005] To address the above problems, this invention discloses a control circuit for an analog-to-digital converter, the control circuit comprising: an analog-to-digital converter, a buffer, a verification circuit, and a central processing unit;

[0006] The analog-to-digital converter includes at least one channel and at least one register, with one channel corresponding to one register; the analog-to-digital converter is used to generate a conversion completion signal after the channel completes conversion and obtains a first conversion result, and to generate an interrupt signal when the first conversion result is stored in the buffer; the register is used to store the first conversion result of the corresponding channel based on a write signal;

[0007] The verification circuit is used to verify, based on the conversion completion signal, whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit; if the second conversion result has been read by the central processing unit, a write signal is generated; if the second conversion result has not been read by the central processing unit, the first conversion result is stored in the buffer.

[0008] The central processing unit is configured to read the first conversion result from the register when no interrupt signal is detected, and to read the first conversion result from the buffer when the interrupt signal is detected.

[0009] Optionally, the verification circuit is further configured to, if the second conversion result is not read by the central processing unit, store the channel number of the channel corresponding to the first conversion result in the buffer.

[0010] Optionally, the central processing unit is further configured to read the second conversion result from the register when the interrupt signal is detected.

[0011] Optionally, the verification circuit is used to obtain the read flag bit of the register from the register; and to determine whether the second conversion result has been read by the central processing unit based on the read flag bit.

[0012] Optionally, the verification circuit is configured to set the overflow flag of the register to invalid if the second conversion result has been read by the central processing unit, and to set the overflow flag of the register to valid if the second conversion result has not been read by the central processing unit.

[0013] Optionally, the verification circuit is used to control the write pointer of the register to remain unchanged if the second conversion result has been read by the central processing unit;

[0014] If the second conversion result is not read by the central processing unit, the write pointer of the cache is incremented by one, and the first conversion result is stored in the cache space corresponding to the write pointer.

[0015] Accordingly, embodiments of the present invention disclose a control method for an analog-to-digital converter, applied to the control circuit described above. The method includes:

[0016] The analog-to-digital converter generates a conversion completion signal after obtaining a first conversion result from the channel conversion, and generates an interrupt signal when the first conversion result is stored in the buffer; the register is used to store the first conversion result of the corresponding channel based on the write signal;

[0017] The verification circuit checks, based on the conversion completion signal, whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit (CPU). If the second conversion result has been read by the CPU, a write signal is generated. If the second conversion result has not been read by the CPU, the first conversion result is stored in the buffer.

[0018] When the central processing unit does not detect the interrupt signal, it reads the first conversion result from the register; when the interrupt signal is detected, it reads the first conversion result from the buffer.

[0019] Optionally, the method further includes:

[0020] If the second conversion result is not read by the central processing unit through the verification circuit, the channel number of the channel corresponding to the first conversion result is stored in the buffer.

[0021] Optionally, the method further includes:

[0022] When the interrupt signal is detected, the central processing unit reads the second conversion result from the register.

[0023] Optionally, the step of verifying, based on the conversion completion signal, whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit through the verification circuit includes:

[0024] The verification circuit obtains the read flag bit of the register from the register based on the conversion completion signal;

[0025] The read flag is used to determine whether the second conversion result has been read by the central processing unit.

[0026] Optionally, the method further includes:

[0027] If the second conversion result has been read by the central processing unit through the verification circuit, the overflow flag of the register is set to invalid.

[0028] If the second conversion result is not read by the central processing unit, the overflow flag of the register is set to valid.

[0029] Optionally, the method further includes:

[0030] If the second conversion result has been read by the central processing unit through the verification circuit, the write pointer of the cache is kept unchanged.

[0031] The step of storing the first conversion result in the cache if the second conversion result is not read by the central processing unit includes:

[0032] If the second conversion result is not read by the central processing unit, the write pointer of the cache is incremented by one, and the first conversion result is stored in the cache space corresponding to the write pointer.

[0033] Accordingly, an embodiment of the present invention discloses a chip, which includes the control circuit of the analog-to-digital converter described above.

[0034] The embodiments of the present invention have the following advantages:

[0035] An analog-to-digital converter (ADC) control circuit according to an embodiment of the present invention includes: an ADC, a buffer, a verification circuit, and a central processing unit (CPU). The ADC includes at least one channel and at least one register, with one channel corresponding to one register. The ADC generates a conversion completion signal after obtaining a first conversion result upon completion of channel conversion, and generates an interrupt signal when the first conversion result is stored in the buffer. The register stores the first conversion result of the corresponding channel based on a write signal. The verification circuit verifies whether the second conversion result currently stored in the register corresponding to the channel has been read by the CPU based on the conversion completion signal. If the second conversion result has been read by the CPU, a write signal is generated; if the second conversion result has not been read by the CPU, the first conversion result is stored in the buffer. This avoids the situation where storing the first conversion result in the register and overwriting the unread second conversion result when the second conversion result currently stored in the register has not been read by the CPU, thus achieving reliable storage of the ADC conversion result data. The central processing unit is used to read the first conversion result from the register when no interrupt signal is detected, and to read the first conversion result from the buffer when an interrupt signal is detected, as well as to read the second conversion result from the register. This avoids the problem of data loss or corruption caused by the inability to read the current conversion result stored in the register in time. Attached Figure Description

[0036] Figure 1 This is a structural diagram of a control circuit for an analog-to-digital converter according to an embodiment of the present invention;

[0037] Figure 2 This is a flowchart illustrating the steps of a control method for an analog-to-digital converter according to an embodiment of the present invention.

[0038] Figure reference numerals: Analog-to-digital converter 10, Channel 11, Register 12, Buffer 20, Verification circuit 30, Central processing unit 40. Detailed Implementation

[0039] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0040] Analog-to-digital converters (ADCs) play a crucial role in modern electronic systems, their primary function being to convert analog signals into digital signals. ADCs typically have multiple conversion channels, enabling them to sample and convert multiple analog signals simultaneously or sequentially, thus meeting the multi-signal processing requirements of complex systems.

[0041] In common implementations, each ADC conversion channel is equipped with an independent register to store its own conversion result. While this design simplifies data management, it may expose some potential problems under high sampling rates or heavy system loads. Specifically, due to potential delays in the central processing unit (CPU) while processing other tasks, it may be unable to read the current conversion result stored in the register in a timely manner. In this case, a new conversion result may be quickly generated and overwrite the current one, leading to data loss or result corruption.

[0042] One of the core concepts of this invention is that after the analog-to-digital converter (ADC) obtains the first conversion result after channel conversion, it generates a conversion completion signal. Based on the conversion completion signal, the verification circuit checks whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit (CPU). If it has been read, a write signal is generated to write the first conversion result into the register. If it has not been read, the first conversion result is stored in the buffer. This avoids the situation where the first conversion result is stored in the register and overwrites the unread second conversion result when the second conversion result currently stored in the register has not been read by the CPU, thus achieving reliable storage of the conversion result data of the ADC.

[0043] Reference Figure 1 The diagram shows a structural diagram of a control circuit for an analog-to-digital converter according to an embodiment of the present invention, which may specifically include the following structure:

[0044] Analog-to-digital converter 10, buffer 20, verification circuit 30 and central processing unit 40.

[0045] An analog-to-digital converter (ADC) is used to convert analog signals (such as voltage or current) into digital signals. The working principle of an ADC includes: sampling, where the ADC first samples the input analog signal, that is, measures the value of the analog signal at a specific point in time; quantization, where the sampled analog signal value is quantized into discrete digital values, converting the continuous analog signal into a finite number of discrete levels; and encoding, where the quantized digital values ​​are encoded into binary form to form a digital signal.

[0046] The analog-to-digital converter 10 includes at least one channel 11 and at least one register 12, with one channel 11 corresponding to one register 12.

[0047] The number of channels in an analog-to-digital converter (ADC) refers to the number of analog input signals it can process simultaneously. A multi-channel ADC can process multiple input signals simultaneously and convert them into digital signals, typically using a multiplexer to select different input channels. A single-channel ADC can only process one input signal. Internally, an ADC contains various types of registers for storing and processing data. These include: a sample-and-hold register (SUP) to store the voltage value of the input signal at the sampling moment, enabling accurate quantization by the ADC, including a sampling switch, hold capacitor, and buffer amplifier; a quantization register to store the quantized digital value, converting the continuous analog signal into discrete digital values, including a comparator array and encoding logic; an encoding register to encode the quantized digital value into binary form, forming a digital signal, including logic gates and shift registers; a control register to store and process control signals, controlling the ADC's conversion process, including a state machine and control logic; a status register to store the ADC's operating status information, such as conversion completion and overflow flags, including status bits and flag bits; and a configuration register to store the ADC's configuration parameters, such as resolution, sampling rate, and input range, including configuration bits and parameter storage units.

[0048] The analog-to-digital converter 10 is used to generate a conversion completion signal after the first conversion result is obtained after the conversion is completed in the channel 11, and to generate an interrupt signal when the first conversion result is stored in the buffer 20. The conversion completion signal (End of Conversion Signal, or EOC signal) is used to indicate the end of the ADC conversion process.

[0049] The register 12 is used to store the first conversion result of the corresponding channel 11 based on the write signal.

[0050] Register 12 can be a result register, used to store the converted result, ensuring that the converted data can be read and processed by external systems. The result register transmits the stored data to external systems (such as microcontrollers or processors) through interface circuits (such as parallel or serial interfaces). Before the data is read, the result register maintains the stability of the converted result to prevent data loss or corruption. The result register consists of: a data storage unit for storing the converted digital data. The number of bits in the data storage unit is usually consistent with the resolution of the analog-to-digital converter, such as 8-bit, 12-bit, or 16-bit; read control logic for controlling the data read operation. The read control logic typically includes a read enable signal and address decoding logic; and an interface circuit for communicating with external systems and transmitting the stored data. The interface circuit can be a parallel interface, serial interface, or other types of interface.

[0051] Register 12 has a depth of 1. A register with a depth of 1 is used to temporarily store a single data item. During data transfer, the register can be used to buffer data and ensure data integrity during transmission. When an external system writes data to the register, the register stores that data item. If the register already contains data, the new data will overwrite the old data. When an external system reads data from the register, the register will output the stored data item.

[0052] The verification circuit 30 is used to verify, based on the conversion completion signal, whether the second conversion result currently stored in the register 12 corresponding to the channel 11 has been read by the central processing unit 40; if the second conversion result has been read by the central processing unit 40, a write signal is generated; if the second conversion result has not been read by the central processing unit 40, the first conversion result is stored in the buffer 20.

[0053] After the analog-to-digital converter 10 completes the conversion in channel 11 and obtains the first conversion result, it generates a conversion completion signal. This means that there is a new first conversion result that needs to be stored. The verification circuit 30 needs to check whether the second conversion result currently stored in the register 12 corresponding to channel 11 has been read by the central processing unit 40. If the second conversion result has been read by the central processing unit 40, that is, the second conversion result currently stored in register 12 can be overwritten, a write signal is generated. After receiving the write signal, register 12 stores the first conversion result in register 12 according to the write signal. The first conversion result overwrites the second conversion result, that is, the second conversion result is updated to the first conversion result.

[0054] If the second conversion result is not read by the central processing unit 40, then the first conversion result cannot be stored in register 12. If the first conversion result is stored in register 12, it will overwrite the first conversion result that has not been read by the central processing unit 40, resulting in data corruption. Therefore, the first conversion result is moved to the buffer 20, while the second conversion result is still stored in register 12.

[0055] Buffer 20 can be a FIFO (First In, First Out) memory. A FIFO memory is a first-in, first-out queue structure, meaning that the data that enters first will also be retrieved first. FIFOs are widely used in digital signal processing, communication systems, embedded systems, and other fields, especially in situations where temporary data storage is required for sequential processing later. FIFO memory is used for temporary data storage, ensuring data integrity during transmission. It stores and retrieves data in a first-in, first-out order, ensuring that the processing order matches the input order. It can also be used for flow control, balancing the rate of data production and consumption. A FIFO memory includes: storage cells, which store data items. The number of storage cells determines the depth of the FIFO (i.e., the number of data items that can be stored); a write pointer, which indicates the next location to write data. The write pointer increments after each data write; and a read pointer, which indicates the next location to read data. After each data read, the read pointer increments. Status signals: FIFOs typically provide status signals, such as Full, Empty, and Half Full, to indicate the FIFO's storage status. Control logic: The control logic manages the FIFO's read and write operations, ensuring correct data storage and retrieval. The working principle of a FIFO is as follows: Data writing: When an external system writes data to the FIFO, the data is stored in the memory cell pointed to by the write pointer, and the write pointer increments. Data reading: When an external system reads data from the FIFO, the data is read from the memory cell pointed to by the read pointer, and the read pointer increments. Status detection: External systems can determine the FIFO's storage status by detecting its status signals (such as Full, Empty), avoiding overflow or data loss.

[0056] The central processing unit 40 is configured to read the first conversion result from the register 12 when no interrupt signal is detected, and to read the first conversion result from the buffer 20 when the interrupt signal is detected.

[0057] The analog-to-digital converter 10 generates an interrupt signal when the first conversion result is stored in the buffer 20. When no interrupt signal is detected, that is, when the first conversion result is stored in the register 12, the first conversion result is read from the register 12. When an interrupt signal is detected, that is, when the first conversion result is stored in the buffer 20, the first conversion result is read from the buffer 20.

[0058] When a conversion completion signal is detected, and the second conversion result currently stored in register 12 corresponding to the channel has not been read by the central processing unit 40, the first conversion result is stored in buffer 20. This avoids the problem of the second conversion result currently stored in register 12 being overwritten when it has not been read by the central processing unit 40. Furthermore, storing the first conversion result in buffer 20 only when it has not been read also avoids caching duplicate results, reduces the time required for the software program to filter data, makes the system run faster, and can also reduce the depth of the FIFO, reduce the area of ​​the overall circuit, and save costs.

[0059] An analog-to-digital converter (ADC) control circuit according to an embodiment of the present invention includes: an ADC, a buffer, a verification circuit, and a central processing unit (CPU). The ADC includes at least one channel and at least one register, with one channel corresponding to one register. The ADC generates a conversion completion signal after obtaining a first conversion result upon completion of channel conversion, and generates an interrupt signal when the first conversion result is stored in the buffer. The register stores the first conversion result of the corresponding channel based on a write signal. The verification circuit verifies whether the second conversion result currently stored in the register corresponding to the channel has been read by the CPU based on the conversion completion signal. If the second conversion result has been read by the CPU, a write signal is generated; if the second conversion result has not been read by the CPU, the first conversion result is stored in the buffer. This avoids the situation where storing the first conversion result in the register and overwriting the unread second conversion result when the second conversion result currently stored in the register has not been read by the CPU, thus achieving reliable storage of the ADC conversion result data. The central processing unit is used to read the first conversion result from the register when no interrupt signal is detected, and to read the first conversion result from the buffer when an interrupt signal is detected, as well as to read the second conversion result from the register. This avoids the problem of data loss or corruption caused by the inability to read the current conversion result stored in the register in time.

[0060] In this embodiment of the invention, the verification circuit 30 is further configured to store the channel number of the channel corresponding to the first conversion result in the buffer 20 if the second conversion result is not read by the central processing unit 40.

[0061] When the verification circuit 30 detects that the second conversion result has not been read by the central processing unit 40, it not only stores the first conversion result in the buffer 20, but also sends the channel number of the channel corresponding to the first conversion result to the buffer 20. In this way, when the central processing unit 40 reads data from the buffer 20, it can know the first conversion result and the channel number of the channel corresponding to the first conversion result. Since one register 12 corresponds to one channel, when the central processing unit 40 reads the conversion result from the register 12, it also knows the channel corresponding to the conversion result.

[0062] In this embodiment of the invention, the central processing unit 40 is further configured to read the second conversion result from the register when the interrupt signal is detected.

[0063] When the central processing unit 40 detects the interrupt signal, it needs to read the first conversion result from the buffer 20 and also needs to speed up the reading of the second conversion result from the register 12.

[0064] To accelerate data reading by the CPU 40, the following measures can be taken: Set overflow interrupts as high-priority interrupts to ensure the processor can respond to overflow events promptly; allow interrupt nesting, meaning that during interrupt handling, higher-priority interrupt requests can interrupt the current interrupt handler to ensure high-priority events are processed in a timely manner; when an overflow is detected, the system can prefetch data from the buffer or memory into the cache (such as L1 or L2 cache) to reduce data read latency; utilize the processor's pipelined operations to prepare data read instructions in advance, reducing data read waiting time; in multi-core processor systems, multiple cores can be used to process data read tasks in parallel to improve data read speed; distribute data read tasks to multiple cores or threads to accelerate data reading using parallel processing capabilities.

[0065] In this embodiment of the invention, the verification circuit 30 is used to obtain the read flag bit of the register 12 from the register 12; and to determine whether the second conversion result has been read by the central processing unit based on the read flag bit.

[0066] The read flag bit of register 12 indicates whether the second conversion result currently stored in register 12 has been read by the central processing unit 40. The read flag bit is a single bit used to indicate whether the data in the result register has been read or processed. A read flag bit of 1 indicates that the data has not been read (valid), and a read flag bit of 0 indicates that the data has been read (invalid). Before writing new data to the result register, the system will check whether the read flag bit in the current result register is valid (i.e., the read flag bit is 1). If the read flag bit is valid, it means that the data in the current result register has not been read. Writing new data at this time will cause the data to be overwritten, thus causing an overflow.

[0067] In this embodiment of the invention, the verification circuit 30 is used to set the overflow flag of the register 12 to invalid if the second conversion result has been read by the central processing unit 40; and to set the overflow flag of the register 12 to valid if the second conversion result has not been read by the central processing unit 40.

[0068] The verification circuit 30 is used to set the overflow flag of register 12 to invalid if the second conversion result has been read by the central processing unit 40, indicating that the data has not overflowed; and to set the overflow flag of register 12 to valid if the second conversion result has not been read by the central processing unit 40, indicating that writing new data at this time will cause data overwriting and thus overflow will occur.

[0069] In this embodiment of the invention, the verification circuit 30 is used to control the write pointer of the cache 20 to remain unchanged if the second conversion result has been read by the central processing unit 40.

[0070] The verification circuit 30 is used to store the first conversion result in the register 12 if the second conversion result has been read by the central processing unit 40, and to keep the write pointer of the buffer 20 unchanged and not store data in the buffer 20.

[0071] If the second conversion result is not read by the central processing unit 40, the write pointer of the cache 20 is incremented by one, and the first conversion result is stored in the cache space corresponding to the write pointer.

[0072] The verification circuit 30 is used to check if the second conversion result is not read by the central processing unit 40. If so, it indicates that the first conversion result needs to be stored in the cache 20. The write pointer of the control cache 20 is incremented by one to point to the next available storage location, and the first conversion result is stored in the cache space corresponding to the write pointer.

[0073] The verification circuit 30 is responsible for detecting whether register 12 of the current channel has overflowed. Before writing new data to register 12, the verification circuit 30 checks whether the read flag bit in register 12 is valid (i.e., the read flag bit is 1). If the read flag bit is valid, it means that the data in the current result register has not been read. Writing new data at this time will cause the data to be overwritten, thus causing an overflow. When an overflow is detected, the verification circuit 30 controls the write pointer of the buffer 20 to increment by 1, pointing to the next available storage location. After the write pointer is updated, the verification circuit 30 controls the buffer 20 to store the conversion result in the new address space. At this time, register 12 of the channel does not buffer the new result, but retains the previous conversion result. When an overflow is detected, an interrupt signal is generated to notify the processor that there is an urgent event that needs to be handled. The interrupt signal is transmitted to the processor through the interrupt controller. After detecting an interrupt request signal, the CPU 40 pauses the current execution flow and saves the current execution state (such as the program counter and register states). According to the type of interrupt request signal, the CPU 40 jumps to the corresponding interrupt handler to handle the overflow event. In the interrupt handler, the processor speeds up the reading of the conversion results in the buffer 20 to ensure that the data is not lost. After the interrupt handler finishes execution, the CPU 40 clears the overflow flag, indicating that the overflow event has been handled.

[0074] The verification circuit 30 is responsible for detecting whether register 12 of the current channel has overflowed. If an overflow occurs, the write pointer of buffer 20 is incremented by 1, the storage space of buffer 20 saves the conversion result, and at this time, register 12 of the channel does not buffer the new result, but retains the previous conversion result and generates an overflow interrupt, which is transmitted to the processor through the interrupt controller. In the interrupt handler, the central processing unit 40 accelerates the reading of the conversion result in buffer 20 and clears the overflow flag to ensure correct data processing and normal system operation.

[0075] By adding a buffer 20 to store the conversion results and channel sequence numbers of each channel 11 of the analog-to-digital converter 10, and a circuit to check whether the data in the register 12 overflows, the write address of the buffer 20 is incremented only when an overflow occurs, thus avoiding cached duplicate results, reducing the time required for the software program to filter data, making the system run faster, and also reducing the depth of the buffer 20, reducing the overall circuit area, and saving costs.

[0076] Reference Figure 2 The diagram illustrates a flowchart of a control method for an analog-to-digital converter according to an embodiment of the present invention, which may specifically include the following steps:

[0077] Step 101: After the analog-to-digital converter obtains the first conversion result after the channel conversion is completed, a conversion completion signal is generated, and an interrupt signal is generated when the first conversion result is stored in the buffer; the register is used to store the first conversion result of the corresponding channel based on the write signal.

[0078] Step 102: The verification circuit checks whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit based on the conversion completion signal; if the second conversion result has been read by the central processing unit, a write signal is generated; if the second conversion result has not been read by the central processing unit, the first conversion result is stored in the buffer.

[0079] Step 103: When the central processing unit does not detect the interrupt signal, it reads the first conversion result from the register; when the interrupt signal is detected, it reads the first conversion result from the buffer.

[0080] An analog-to-digital converter (ADC) control circuit according to an embodiment of the present invention includes: an ADC, a buffer, a verification circuit, and a central processing unit (CPU). The ADC includes at least one channel and at least one register, with one channel corresponding to one register. The ADC generates a conversion completion signal after obtaining a first conversion result upon completion of channel conversion, and generates an interrupt signal when the first conversion result is stored in the buffer. The register stores the first conversion result of the corresponding channel based on a write signal. The verification circuit verifies whether the second conversion result currently stored in the register corresponding to the channel has been read by the CPU based on the conversion completion signal. If the second conversion result has been read by the CPU, a write signal is generated; if the second conversion result has not been read by the CPU, the first conversion result is stored in the buffer. This avoids the situation where storing the first conversion result in the register and overwriting the unread second conversion result when the second conversion result currently stored in the register has not been read by the CPU, thus achieving reliable storage of the ADC conversion result data. The central processing unit is used to read the first conversion result from the register when no interrupt signal is detected, and to read the first conversion result from the buffer when an interrupt signal is detected, as well as to read the second conversion result from the register. This avoids the problem of data loss or corruption caused by the inability to read the current conversion result stored in the register in time.

[0081] In this embodiment of the invention, the method further includes:

[0082] If the second conversion result is not read by the central processing unit through the verification circuit, the channel number of the channel corresponding to the first conversion result is stored in the buffer.

[0083] In this embodiment of the invention, the method further includes:

[0084] When the interrupt signal is detected, the central processing unit reads the second conversion result from the register.

[0085] In this embodiment of the invention, step 102, which involves the verification circuit verifying whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit based on the conversion completion signal, may specifically include the following sub-steps:

[0086] Sub-step S21: Based on the conversion completion signal, the verification circuit obtains the read flag bit of the register from the register;

[0087] Sub-step S22: Determine whether the second conversion result has been read by the central processing unit based on the read flag bit.

[0088] In this embodiment of the invention, the method further includes:

[0089] If the second conversion result has been read by the central processing unit through the verification circuit, the overflow flag of the register is set to invalid.

[0090] If the second conversion result is not read by the central processing unit, the overflow flag of the register is set to valid.

[0091] In this embodiment of the invention, the method further includes:

[0092] If the second conversion result has been read by the central processing unit through the verification circuit, the write pointer of the cache is kept unchanged.

[0093] The step of storing the first conversion result in the cache if the second conversion result is not read by the central processing unit includes:

[0094] If the second conversion result is not read by the central processing unit, the write pointer of the cache is incremented by one, and the first conversion result is stored in the cache space corresponding to the write pointer.

[0095] An embodiment of the present invention provides a control circuit for an analog-to-digital converter (ADC). The ADC includes at least one channel and at least one register, with one channel corresponding to one register. The ADC generates a conversion completion signal after obtaining a first conversion result upon completion of channel conversion, and generates an interrupt signal when the first conversion result is stored in a buffer. The register stores the first conversion result of the corresponding channel based on a write signal. A verification circuit checks whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit (CPU) based on the conversion completion signal. If the second conversion result has been read by the CPU, a write signal is generated; if the second conversion result has not been read by the CPU, the first conversion result is stored in the buffer. The CPU reads the first conversion result from the register when no interrupt signal is detected, reads the first conversion result from the buffer when an interrupt signal is detected, and reads the second conversion result from the register. After the analog-to-digital converter (ADC) completes the first conversion and obtains the first conversion result, it generates a conversion completion signal. Based on the conversion completion signal, the verification circuit checks whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit (CPU). If it has been read, a write signal is generated to write the first conversion result into the register. If it has not been read, the first conversion result is stored in the buffer. This avoids the situation where the first conversion result is stored in the register and overwrites the unread second conversion result if the second conversion result currently stored in the register has not been read by the CPU, thus achieving reliable storage of the conversion result data of the ADC.

[0096] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0097] This invention also discloses a chip, which includes the control circuit of the analog-to-digital converter as described above.

[0098] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0099] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0100] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0101] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0102] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0103] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0104] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0105] The control circuit, method, and chip of an analog-to-digital converter provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A control circuit for an analog-to-digital converter, characterized by The control circuit comprises an analog-to-digital converter, a buffer, a checking circuit and a central processing unit. The analog-to-digital converter comprises at least one channel and at least one register, one channel corresponding to one register; the analog-to-digital converter is configured to generate a conversion completion signal after the conversion of the channel is completed to obtain a first conversion result, and generate an interrupt signal when the first conversion result is stored in the buffer; the register is configured to store the first conversion result of the corresponding channel based on a write signal; The checking circuit is configured to check whether a second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit based on the conversion completion signal; if the second conversion result has been read by the central processing unit, a write signal is generated; if the second conversion result has not been read by the central processing unit, the first conversion result is stored in the buffer; The central processing unit is configured to read the first conversion result from the register when the interrupt signal is not detected, and read the first conversion result from the buffer when the interrupt signal is detected.

2. The control circuit of claim 1, wherein, The checking circuit is further configured to store a channel number of the channel corresponding to the first conversion result in the buffer if the second conversion result has not been read by the central processing unit.

3. The control circuit of claim 1, wherein, The central processing unit is further configured to read the second conversion result from the register when the interrupt signal is detected.

4. The control circuit of claim 1, wherein, The checking circuit is configured to obtain a read flag bit of the register from the register, and determine whether the second conversion result has been read by the central processing unit according to the read flag bit.

5. The control circuit of claim 1, wherein, The checking circuit is configured to set an overflow flag bit of the register to be invalid if the second conversion result has been read by the central processing unit; The checking circuit is configured to set the overflow flag bit of the register to be valid if the second conversion result has not been read by the central processing unit.

6. The control circuit of claim 1, wherein, The checking circuit is configured to control the write pointer of the buffer to remain unchanged if the second conversion result has been read by the central processing unit; The checking circuit is configured to control the write pointer of the buffer to be incremented by one and store the first conversion result in the buffer space corresponding to the write pointer if the second conversion result has not been read by the central processing unit.

7. A control method of an analog-to-digital converter, characterized by, The method is applied to the control circuit of claim 1, and the method comprises: generating, by the analog-to-digital converter, a conversion completion signal after the conversion of the channel is completed to obtain a first conversion result, and generating an interrupt signal when the first conversion result is stored in the buffer; the register is configured to store the first conversion result of the corresponding channel based on a write signal; checking, by the checking circuit, whether a second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit based on the conversion completion signal; if the second conversion result has been read by the central processing unit, a write signal is generated; if the second conversion result has not been read by the central processing unit, the first conversion result is stored in the buffer; reading, by the central processing unit, the first conversion result from the register when the interrupt signal is not detected; and reading, by the central processing unit, the second conversion result from the register when the interrupt signal is detected.

8. The method of claim 7, wherein, The method further comprises: storing, by the inspection circuit, a channel number of the first conversion result corresponding channel to the buffer if the second conversion result is not read by the central processing unit.

9. The method of claim 7, wherein, The method further comprises: reading, by the central processing unit, the second conversion result from the register when the interrupt signal is detected.

10. The method of claim 7, wherein, The inspection, by the inspection circuit, of whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit based on the conversion completion signal comprises: acquiring, by the inspection circuit, a read flag bit of the register from the register based on the conversion completion signal; determining whether the second conversion result has been read by the central processing unit according to the read flag bit.

11. The method of claim 7, wherein, The method further comprises: setting, by the inspection circuit, an overflow flag bit of the register to invalid if the second conversion result has been read by the central processing unit; setting, by the inspection circuit, the overflow flag bit of the register to valid if the second conversion result has not been read by the central processing unit.

12. The method of claim 7, wherein, The method further comprises: controlling, by the inspection circuit, the write pointer of the buffer to remain unchanged if the second conversion result has been read by the central processing unit. The storing, by the inspection circuit, of the first conversion result to the buffer if the second conversion result has not been read by the central processing unit comprises: controlling, by the inspection circuit, the write pointer of the buffer to increase by one and storing the first conversion result to the buffer space corresponding to the write pointer if the second conversion result has not been read by the central processing unit.

13. A chip comprising the control circuit of the analog-to-digital converter according to any one of claims 1-6.

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