Five-state comparator with metastable state detection and correction and five-state quantitative successive approximation method

Abstract

The invention relates to a five-state comparator with metastable state detection and correction, and the comparator comprises a pre-stage pre-amplification circuit which is used for carrying out the pre-amplification of an input differential signal, and then outputting a signal to a post-stage latch circuit; the post-stage latch circuit latches and outputs a comparison result of the comparator through a plurality of MOS (Metal Oxide Semiconductor) tubes; the strong metastable state detection and setting circuit is used for detecting whether the comparator is in a strong metastable state or not and carrying out output setting on the comparator, and if the comparator is detected to be in the strong metastable state, a strong metastable state identification bit is generated; the metastable state detection circuit is used for detecting and identifying whether the comparator is in a metastable state or not, and if the comparator is detected to be in the metastable state, a metastable state identification bit is generated; the clock circuit is used for generating clock signals corresponding to a working clock, a metastable state detection clock and a strong metastable state detection clock of the comparator; and the coding circuit is used for combining the output of the comparator and the metastable state identification bit so as to output a digital output result. The quantization efficiency can be greatly improved.

Description

Technical Field

[0001] The present application relates to the technical field of analog integrated circuits, and in particular to a five-state comparator with metastable detection and correction and a five-state quantization successive approximation method. Background Art

[0002] A dynamic comparator is a module that compares the voltages across its inputs under clock control. It typically has two phases: a comparison phase and a reset phase. During the reset phase, the voltages at the internal nodes of the circuit are reset. During the comparison phase, the output node flips after a certain comparison time, depending on the magnitude of the input voltages. A key characteristic of a comparator is that the time required to obtain the output increases as the difference between the input voltages decreases. When the difference between the input voltages is too small, the comparator may not be able to complete the comparison within the specified comparison phase time, resulting in a metastable state.

[0003] Dynamic comparators are widely used in analog-to-digital converters (ADCs), such as successive approximation register (SAR) ADCs. High-performance SAR ADCs require high-speed and high-precision comparators. However, due to the short comparison time allocated to the comparator, the comparator is prone to metastable states, which limits the overall conversion speed and accuracy. In SAR ADCs, when the comparator experiences metastable states, it can affect the normal operation of the circuit, preventing the conversion of all bits. This can cause the system to generate flickering codes, seriously affecting the ADC's performance.

[0004] Existing metastability suppression techniques primarily perform an exclusive-OR operation on the comparator's output voltage, using the XOR result as a comparison result flag. After delaying the comparison clock for a certain period of time, if the comparator fails to output the correct logic result within the set delay time and the comparison result flag remains 0, a metastable state is considered to have occurred. Combinatorial logic circuits and triggers are then used to set the voltages at the comparator output, which has experienced metastable conditions, to 1 and 0 via PMOS and NMOS transistors. This comparator metastable detection method requires the output result to be set only after passing through the exclusive-OR gate, combinational logic, and triggers. The delays in the metastable detection and setting paths are significant, and the comparator output voltage may flip during the detection and setting process. This often results in significant errors and prevents accurate metastable detection results. Furthermore, setting the voltages at the comparator output, which has experienced metastable conditions, to 1 and 0 fails to capture the voltage difference between the comparator inputs during the metastable state, reducing comparator accuracy. Furthermore, the inclusion of NMOS and PMOS transistors at the comparator's ends introduces additional comparator offset voltage.

[0005] In addition, conventional comparators can usually only obtain two output results in one comparison, which limits the SARADC to quantization through the two-state binary division successive approximation method. When the continuous analog input signal approaches the reference quantization line of 1 / 2, 1 / 4, etc., the output decision time of the comparator will be significantly extended, resulting in a longer ADC conversion time. Moreover, the successive approximation method of bisecting a voltage region with a reference quantization line is not an efficient quantization method. N times of successive approximation can only obtain 1 / 2 at most. N quantization accuracy.

[0006] In summary, conventional comparators in the prior art can usually only obtain two output results in one comparison. When the continuous signal of the analog input approaches the reference quantization lines that are divided into two equal parts, such as 1 / 2 and 1 / 4, the output decision time of the comparator will be significantly extended, resulting in problems such as longer ADC conversion time. The applicant has made corresponding explorations to solve this problem. Summary of the Invention

[0007] The purpose of the present application is to solve the above problems and provide a five-state comparator with metastable detection and correction, a five-state quantization successive approximation method, an electronic device, a computer device, and a computer-readable storage medium.

[0008] In order to meet the various objectives of this application, this application adopts the following technical solutions:

[0009] A five-state comparator with metastable detection and correction is proposed to meet one of the purposes of this application, including:

[0010] A front-stage pre-amplifier circuit, which is used to pre-amplify the input differential signal and then output the signal to the rear-stage latch circuit;

[0011] The post-stage latch circuit latches and outputs the comparison result of the comparator through multiple MOS tubes;

[0012] A strong metastable state detection and setting circuit, which is used to detect whether the comparator is in a strong metastable state and set the output of the comparator, and if the strong metastable state is detected, generate a strong metastable state flag;

[0013] a metastable state detection circuit, which is used to detect and identify whether the comparator is in a metastable state, and if a metastable state is detected, generate a metastable state flag bit;

[0014] A clock circuit, configured to generate clock signals corresponding to the comparator's operating clock, metastable detection clock, and strong metastable detection clock;

[0015] The encoding circuit is used to combine the output of the comparator and the metastable flag bit to output a digital output result.

[0016] Optionally, the front-stage pre-amplifier circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor, wherein the gates of the first MOS transistor and the second MOS transistor are respectively connected to a positive input signal VIP and a negative input signal VIN, and the sources of the first MOS transistor and the second MOS transistor are commonly connected to ground;

[0017] The drain of the first MOS transistor is connected to the third MOS transistor, and the drain of the second MOS transistor is connected to the fourth MOS transistor;

[0018] The gates of the third MOS transistor and the fourth MOS transistor, and the gates of the fifth MOS transistor and the sixth MOS transistor are commonly connected to a comparison clock signal CLKC;

[0019] The drain of the third MOS tube is connected to the fifth MOS tube, the drain of the fourth MOS tube is connected to the sixth MOS tube, and the sources of the fifth MOS tube and the sixth MOS tube are commonly connected to a power supply voltage.

[0020] Optionally, the post-stage latch circuit includes a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor, a twenty-first MOS transistor, and a twenty-second MOS transistor;

[0021] The gates of the seventh MOS tube and the eighth MOS tube are connected to the third MOS tube and the fourth MOS tube, the thirteenth MOS tube and the fourteenth MOS tube, and the fifteenth MOS tube and the sixteenth MOS tube respectively;

[0022] The sources of the seventh MOS transistor and the eighth MOS transistor are connected to a power supply voltage together with the sources of the nineteenth MOS transistor and the twentieth MOS transistor;

[0023] The drain of the seventh MOS transistor is connected to the ninth MOS transistor and the fifteenth MOS transistor respectively, and the drain of the eighth MOS transistor is connected to the tenth MOS transistor and the sixteenth MOS transistor respectively;

[0024] The gate of the ninth MOS transistor is connected to the eleventh MOS transistor, the twelfth MOS transistor and the fourteenth MOS transistor;

[0025] The gate of the tenth MOS transistor is connected to the eleventh MOS transistor, the twelfth MOS transistor and the thirteenth MOS transistor;

[0026] The drain of the ninth MOS transistor is connected to the nineteenth MOS transistor and the twenty-first MOS transistor, and the drain of the tenth MOS transistor is connected to the twentieth MOS transistor and the twenty-second MOS transistor;

[0027] Sources of the eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor, the fourteenth MOS transistor, the fifteenth MOS transistor, the nineteenth MOS transistor, the twentieth MOS transistor, the twenty-first MOS transistor and the twenty-second MOS transistor are commonly connected to the ground.

[0028] Optionally, the strong metastable state detection and setting circuit includes a seventeenth MOS transistor, an eighteenth MOS transistor, a twenty-third MOS transistor, a twenty-fourth MOS transistor, a twenty-fifth MOS transistor, a twenty-sixth MOS transistor, a twenty-seventh MOS transistor, a twenty-eighth MOS transistor, a twenty-ninth MOS transistor, a thirtieth MOS transistor, a thirty-first MOS transistor, a thirty-second MOS transistor, a thirty-third MOS transistor, a thirty-fourth MOS transistor, a thirty-fifth MOS transistor, and a thirty-sixth MOS transistor, wherein the strong metastable state flag includes a P-end strong metastable state flag MD_sp and an N-end strong metastable state flag MD_sn;

[0029] The drain of the seventeenth MOS tube is connected to the twenty-first MOS tube, and the drain of the eighteenth MOS tube is connected to the twenty-second MOS tube;

[0030] The gate of the seventeenth MOS transistor is connected to the twenty-ninth MOS transistor, the thirty-first MOS transistor, the thirty-third MOS transistor, and the thirty-fifth MOS transistor, and the gate of the eighteenth MOS transistor is connected to the thirtieth MOS transistor, the thirty-second MOS transistor, the thirty-fourth MOS transistor, and the thirty-sixth MOS transistor;

[0031] The sources of the seventeenth MOS transistor and the eighteenth MOS transistor, and the twenty-seventh MOS transistor, the twenty-eighth MOS transistor, the thirty-first MOS transistor, the thirty-second MOS transistor, the thirty-fifth MOS transistor, and the thirty-sixth MOS transistor are connected to the ground.

[0032] The gate of the twenty-seventh MOS tube is connected to the nineteenth MOS tube and the twenty-first MOS tube, and the gate of the twenty-eighth MOS tube is connected to the twentieth MOS tube and the twenty-second MOS tube;

[0033] The drain of the twenty-seventh MOS transistor is connected to the twenty-fifth MOS transistor, and the twenty-eighth MOS transistor is connected to the twenty-sixth MOS transistor;

[0034] The gates of the twenty-fifth MOS transistor and the twenty-sixth MOS transistor are commonly connected to the strong metastable detection clock CLKCD_s;

[0035] The drain of the twenty-fifth MOS transistor is connected to the twenty-third MOS transistor, the twenty-ninth MOS transistor, the thirty-first MOS transistor, the thirty-third MOS transistor, and the thirty-fifth MOS transistor;

[0036] The drain of the twenty-sixth MOS transistor is connected to the twenty-fourth MOS transistor, the thirtieth MOS transistor, the thirty-second MOS transistor, the thirty-fourth MOS transistor and the thirty-sixth MOS transistor;

[0037] The gates of the twenty-third MOS transistor and the twenty-fourth MOS transistor are commonly connected to the comparison clock signal CLKC, and the sources of the twenty-third MOS transistor and the twenty-fourth MOS transistor are commonly connected to the power supply voltage as well as the twenty-ninth MOS transistor, the thirtieth MOS transistor, the thirty-third MOS transistor, and the thirty-fourth MOS transistor.

[0038] Optionally, the metastable state detection circuit includes a 37th MOS transistor, a 38th MOS transistor, a 39th MOS transistor, a 40th MOS transistor, a 41st MOS transistor, a 42nd MOS transistor, a 43rd MOS transistor M43, a 44th MOS transistor, a 45th MOS transistor, a 46th MOS transistor, a 47th MOS transistor, a 48th MOS transistor, a 49th MOS transistor, and a 50th MOS transistor, wherein the metastable state flag includes a P-end metastable state flag MD_p and an N-end metastable state flag MD_n;

[0039] The gate of the 41st MOS transistor is connected to the 19th MOS transistor and the 21st MOS transistor, and the 42nd MOS transistor is connected to the 20th MOS transistor and the 22nd MOS transistor;

[0040] The drain of the 41st MOS tube is connected to the 39th MOS tube, and the drain of the 42nd MOS tube is connected to the 40th MOS tube;

[0041] The gates of the thirty-ninth MOS transistor and the fortieth MOS transistor are commonly connected to the metastable detection clock CLKCD; the drain of the thirty-ninth MOS transistor is connected to the thirty-seventh MOS transistor, the forty-third MOS transistor, the forty-fifth MOS transistor, the forty-seventh MOS transistor, and the forty-ninth MOS transistor; the drain of the fortieth MOS transistor is connected to the thirty-eighth MOS transistor, the forty-fourth MOS transistor, the forty-sixth MOS transistor, the forty-eighth MOS transistor, and the fiftieth MOS transistor;

[0042] The gates of the thirty-seventh MOS transistor and the thirty-eighth MOS transistor are commonly connected to the comparison clock signal CLKC, and the sources of the thirty-seventh MOS transistor and the thirty-eighth MOS transistor are commonly connected to the power supply voltage as well as the forty-third MOS transistor, the forty-fourth MOS transistor, the forty-seventh MOS transistor, and the forty-eighth MOS transistor;

[0043] The drain of the forty-fifth MOS transistor is connected to the forty-third MOS transistor, the forty-seventh MOS transistor, and the forty-ninth MOS transistor, and the drain of the forty-sixth MOS transistor is connected to the forty-fourth MOS transistor, the forty-eighth MOS transistor, and the fiftieth MOS transistor;

[0044] The sources of the forty-fifth MOS transistor and the forty-sixth MOS transistor are connected to the ground together with the forty-first MOS transistor, the forty-second MOS transistor, the forty-ninth MOS transistor and the fiftieth MOS transistor.

[0045] Optionally, the clock circuit includes a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a first delay unit DLY1, a second delay unit DLY2 and a first D flip-flop, wherein:

[0046] The input of the first AND gate AND1 is connected to the output P-end strong metastable flag MD_sp and the N-end strong metastable flag MD_sn of the strong metastable detection and setting circuit, and the output is connected to the clock signal end of the first D flip-flop. The input D end of the first D flip-flop is grounded, the reset end of the first D flip-flop is connected to the start clock EN, and the output is the strong metastable flag MD_s;

[0047] When EN is 1, its output MD_s is 1; MD_s is connected together with the clock CLK to the input of the second AND gate AND2, and the output of the second AND gate AND2 is connected to the comparison clock signal CLKC; the comparison clock signal CLKC is simultaneously connected to the input of the first delay unit DLY1 and the second delay unit DLY2, and their outputs are respectively the metastable detection clock CLKCD and the strong metastable detection clock CLKCD_s;

[0048] The input of the third AND gate AND3 is connected to the output P-end metastable flag MD_p and N-end metastable flag MD_n of the metastable detection circuit, and the output is connected to the metastable flag MD.

[0049] Optionally, the input of the encoding circuit is connected to the P-end comparison output TP and the N-end comparison output TN of the post-stage latch circuit and the metastable identification bit MD in the clock circuit, and the output is a three-bit binary digital output result, which are DOUT1, DOUT2 and DOUT3 from low to high, respectively, where DOUT1 represents the least significant bit, DOUT2 represents the second lowest bit, DOUT3 represents the most significant bit, and DOUT = (TP+TN not) + (TP+TN not) & MD not + MD.

[0050] A five-state quantization successive approximation method proposed to meet another purpose of the present application is applied to any of the above-mentioned five-state comparators with metastable detection and correction, comprising:

[0051] Step (1): During the first approximation, the input signal is compared with 1 / 2 of the quantization reference value. If the input signal is greater than 1 / 2 + 3 / 2, N+3 , it is marked as the first state;

[0052] If the input signal is less than 1 / 2-3 / 2 N+3 , it is marked as the second state;

[0053] If the input signal is between 1 / 2-3 / 2 N+3 to 1 / 2+3 / 2 N+3 If the input signal is between , it means that the preliminary interval where the input signal is located has been found, and the next approximation is not performed. Within the preliminary interval, the state is further subdivided into the third state, the fourth state, and the fifth state according to the specific range of the input signal;

[0054] Among them, if the input signal is 1 / 2+1 / 2 N+3 to 1 / 2+3 / 2 N+3 Between, it is marked as the third state;

[0055] If the input signal is between 1 / 2-3 / 2 N+3 to 1 / 2-1 / 2 N+3 Between, it is marked as the fourth state,

[0056] If the input signal is within 1 / 2±1 / 2 N+3 , it is marked as the fifth state;

[0057] If the approximation result is the first state or the second state, the next approximation is performed and step (2) is continued;

[0058] Step (2): perform a second successive approximation according to the state of the first successive approximation; if the result of the first successive approximation is the first state, then compare the input signal with 3 / 4±3 / 2 N+3 and 3 / 4±1 / 2 N+3 The intervals are compared to produce one of five approximation states;

[0059] If the result of the first successive approximation is the second state, the input signal and 1 / 4±3 / 2 N+3 and 1 / 4±1 / 2 N+3 Interval comparison, resulting in one of five approximation states;

[0060] If the successive approximation is the third state, the fourth state or the fifth state, it means that the signal interval has been found and the approximation process ends; if the successive approximation is the first state or the second state, the next approximation is continued and the process goes to step (3);

[0061] Step (3) and so on, repeat the above approximation process until the Nth successive approximation is completed. If the third state, the fourth state or the fifth state is obtained during a certain successive approximation comparison process, it indicates that the signal interval has been determined and the approximation process is completed.

[0062] Optionally, when no metastable state occurs in the i-th conversion, i is an integer greater than or equal to 2 and less than or equal to N, then the three-digit binary quantization result D(i) finally output by the bit conversion is equal to DOUT(i);

[0063] If the i-th conversion is metastable, the quantization result D(i) of the current bit to the quantization result D(2) of the second lowest bit are all equal to 010, and the quantization result D(1) of the lowest bit is equal to DOUT(i) obtained by the current bit comparison;

[0064] Finally, the high-order quantization result is shifted two bits to the left and added to the low-order digital result. N conversions are performed to obtain N groups of three-bit binary quantization results. After adding two shifted bits, (N+2) valid quantization bits are obtained.

[0065] Compared with the prior art, the present application addresses the problem that conventional comparators in the prior art can usually only obtain two output results in one comparison. When the continuous analog input signal approaches the reference quantization line of 1 / 2, 1 / 4, etc., the output decision time of the comparator will be significantly prolonged, resulting in a longer ADC conversion time. The present application includes but is not limited to the following beneficial effects:

[0066] First, the present invention overcomes the shortcomings of existing successive approximation analog-to-digital converters, such as the inability to obtain reliable logical results due to metastable states, which limits the comparison speed and accuracy. It also overcomes the disadvantage that existing successive approximation analog-to-digital converters can only perform inefficient two-state quantization due to the comparator output having only two states.

[0067] Secondly, the present application divides the metastable state of the comparator into strong metastable state and weak metastable state by setting two metastable detection boundary values ​​of 1 / 8LSB and 3 / 8LSB. When the differential input of the comparator is less than 1 / 8LSB, it is a strong metastable state. When the differential input of the comparator is between 1 / 8LSB and 3 / 8LSB, it is a weak metastable state. When the differential input of the comparator is greater than 3 / 8LSB, no metastable state occurs. Compared with the traditional two-state comparator, the present application has five valid output results for each comparison, which can suppress the metastable state while using the metastable information to improve the accuracy.

[0068] Third, the five-state comparator of the present application adopts a fully differential structure, which can directly perform metastable detection on both ends of the comparator's output at the same time without going through an XOR gate, and after detecting the occurrence of a strong metastable state, the voltage at both ends of the comparator's output can be directly set, without going through combinational logic and triggers to set the voltage at both ends of the comparator's output. The metastable detection and correction circuit of the present application is faster and more accurate.

[0069] Fourthly, the present application uses two identical NMOS transistors to set the comparator when a strong metastable state occurs, setting both ends of the comparator output to 11 in the reset state. The traditional solution uses one NMOS and one PMOS transistor to set both ends of the comparator output to 10, which is an invalid output result. The present application also encodes the output of the comparator after the metastable state occurs and the metastable state flag as a valid comparison result through a new simple logic circuit, corresponding to the smaller input differential voltage value of the comparator at this time. This overcomes the disadvantage of the traditional two-state comparator that requires a long comparison decision time when the differential input is very small. This method can perform metastable detection and correction without introducing additional offset voltage, thereby improving the accuracy of the comparator.

[0070] Fifth, this application proposes a new simple logic circuit, consisting of a low-cost conventional adder with low speed requirements, an inverter, and an AND gate. This circuit can logically combine the comparator's comparison output signals TP and TN and the metastable state flag MD to produce a binary valid digital output DOUT = (TP + TN NOT) + (TP + TN NOT) & MD NOT + MD. This circuit can achieve five valid digital outputs per comparison, while a conventional comparator's digital DOUT = DP or DN NOT, where DN and DN NOT are the inverses of each other. This application can also encode the comparison result after the comparator enters a metastable state as a valid digital output, corresponding to the comparator's smaller input differential voltage value at this time.

[0071] Sixth, the five-state quantization successive approximation method proposed in this application can greatly improve the quantization efficiency compared to the traditional two-state quantization successive approximation method. One quantization has five different effective quantization results, which can accurately quantize the analog input signal within the full range of 0 to 1, and effectively identify and process metastable states. If the input differential signal size is within 3 / 8 of the quantization accuracy during a certain successive approximation comparison process, it indicates that the signal interval has been determined and the approximation process is completed. The quantization of N bits has (2 N+2 -3) quantization results, compared with the traditional two-state quantization, can improve the quantization accuracy by nearly 2 bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0073] Figure 1 Schematic diagram of a five-state comparator with metastable detection and correction in an embodiment of the present application;

[0074] Figure 2 Schematic diagram of the operating waveforms of a five-state comparator with metastable detection and correction in an embodiment of the present application;

[0075] Figure 3 Schematic diagram of five valid digital output results output by a five-state comparator in an embodiment of the present application;

[0076] Figure 4 A schematic diagram showing a comparison of the mathematical forms of the five-state successive approximation method and the conventional two-state successive approximation method in an embodiment of the present application;

[0077] Figure 5 Schematic diagram of the working process of the five-state successive approximation analog-to-digital converter in an embodiment of the present application;

[0078] Figure 6 Schematic diagram of simulation results of a conventional two-state approximation analog-to-digital converter according to an embodiment of the present application;

[0079] Figure 7 FIG. 1 is a schematic diagram of simulation results of a five-state successive approximation analog-to-digital converter according to an embodiment of the present application. DETAILED DESCRIPTION

[0080] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and are not to be construed as limiting the present application.

[0081] It will be understood by those skilled in the art that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. In addition, "connected" or "coupled" as used herein may include wireless connections or wireless couplings. The term "and / or" used herein includes all or any units and all combinations of one or more associated listed items.

[0082] Unless expressly stated to be mutually exclusive, the various embodiments disclosed in this application may be cross-combined with the relevant technical features of the various embodiments to flexibly construct new embodiments, as long as such combination does not deviate from the creative spirit of this application and can meet the needs of the prior art or resolve certain deficiencies in the prior art. Those skilled in the art should be aware of such flexibility.

[0083] See also Figure 1 In one embodiment, the five-state comparator with metastable detection and correction of the present application includes:

[0084] A front-stage pre-amplifier circuit 1 is used to pre-amplify the input differential signal and then output the signal to the rear-stage latch circuit;

[0085] The post-stage latch circuit 2 latches and outputs the comparison result of the comparator through multiple MOS tubes;

[0086] A strong metastable state detection and setting circuit 3, which is used to detect whether the comparator is in a strong metastable state and set the output of the comparator, and if the strong metastable state is detected, generate a strong metastable state flag;

[0087] a metastable state detection circuit 4, which is used to detect and identify whether the comparator is in a metastable state, and if a metastable state is detected, generate a metastable state flag;

[0088] A clock circuit 5, which is used to generate clock signals corresponding to the working clock, metastable detection clock and strong metastable detection clock of the comparator;

[0089] The encoding circuit 6 is used to combine the output of the comparator and the metastable flag to output a digital output result.

[0090] In some embodiments, the front-stage pre-amplifier circuit includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6, wherein the gates of the first MOS transistor M1 and the second MOS transistor M2 are connected to the positive input signal VIP and the negative input signal VI N, respectively, and the sources of the first MOS transistor M1 and the second MOS transistor M2 are commonly connected to the ground;

[0091] The drain of the first MOS transistor M1 is connected to the third MOS transistor M3, and the drain of the second MOS transistor M2 is connected to the fourth MOS transistor M4;

[0092] The gates of the third MOS transistor M3 and the fourth MOS transistor M4, and the gates of the fifth MOS transistor M5 and the sixth MOS transistor M6 are commonly connected to the comparison clock signal CLKC;

[0093] The drain of the third MOS transistor M3 is connected to the fifth MOS transistor M5 , the drain of the fourth MOS transistor M4 is connected to the sixth MOS transistor M6 , and the sources of the fifth MOS transistor M5 and the sixth MOS transistor M6 are connected to the power supply voltage.

[0094] In some embodiments, the post-stage latch circuit includes a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a nineteenth MOS transistor M19, a twentieth MOS transistor M20, a twenty-first MOS transistor M21, and a twenty-second MOS transistor M22.

[0095] The gates of the seventh MOS transistor M7 and the eighth MOS transistor M8 are respectively connected to the third MOS transistor M3 and the fourth MOS transistor M4, the thirteenth MOS transistor M13 and the fourteenth MOS transistor M14, the fifteenth MOS transistor M15 and the sixteenth MOS transistor M16;

[0096] The sources of the seventh MOS transistor M7 and the eighth MOS transistor M8 and the nineteenth MOS transistor M19 and the twentieth MOS transistor M20 are connected to a power supply voltage;

[0097] The drain of the seventh MOS transistor M7 is connected to the ninth MOS transistor M9 and the fifteenth MOS transistor M15 respectively, and the drain of the eighth MOS transistor M8 is connected to the tenth MOS transistor M10 and the sixteenth MOS transistor M16 respectively;

[0098] The gate of the ninth MOS transistor M9 is connected to the eleventh MOS transistor M11, the twelfth MOS transistor M12 and the fourteenth MOS transistor M14;

[0099] The gate of the tenth MOS transistor M10 is connected to the eleventh MOS transistor M11, the twelfth MOS transistor M12, and the thirteenth MOS transistor M13;

[0100] The drain of the ninth MOS transistor M9 is connected to the nineteenth MOS transistor M19 and the twenty-first MOS transistor M21, and the drain of the tenth MOS transistor M10 is connected to the twentieth MOS transistor M20 and the twenty-second MOS transistor M22;

[0101] Sources of the eleventh MOS transistor M11, the twelfth MOS transistor M12, the thirteenth MOS transistor M13, the fourteenth MOS transistor M14, the fifteenth MOS transistor M15, the nineteenth MOS transistor M19, the twentieth MOS transistor M20, the twenty-first MOS transistor M21 and the twenty-second MOS transistor M22 are commonly connected to the ground.

[0102] In some embodiments, the strong metastable state detection and setting circuit includes a seventeenth MOS transistor M17, an eighteenth MOS transistor M18, a twenty-third MOS transistor M23, a twenty-fourth MOS transistor M24, a twenty-fifth MOS transistor M25, a twenty-sixth MOS transistor M26, a twenty-seventh MOS transistor M27, a twenty-eighth MOS transistor M28, a twenty-ninth MOS transistor M29, a thirtieth MOS transistor M30, a thirty-first MOS transistor M31, a thirty-second MOS transistor M32, a thirty-third MOS transistor M33, a thirty-fourth MOS transistor M34, a thirty-fifth MOS transistor M35, and a thirty-sixth MOS transistor M36, wherein the strong metastable state flag includes a P-end strong metastable state flag MD_sp and an N-end strong metastable state flag MD_sn.

[0103] The drain of the seventeenth MOS transistor M17 is connected to the twenty-first MOS transistor M21, and the drain of the eighteenth MOS transistor M18 is connected to the twenty-second MOS transistor M22.

[0104] The gate of the seventeenth MOS transistor M17 is connected to the twenty-ninth MOS transistor M29, the thirty-first MOS transistor M31, the thirty-third MOS transistor M33, and the thirty-fifth MOS transistor M35. The gate of the eighteenth MOS transistor M18 is connected to the thirtieth MOS transistor M30, the thirty-second MOS transistor M32, the thirty-fourth MOS transistor M34, and the thirty-sixth MOS transistor M36.

[0105] The sources of the seventeenth MOS transistor M17 and the eighteenth MOS transistor M18, as well as the twenty-seventh MOS transistor M27, the twenty-eighth MOS transistor M28, the thirty-first MOS transistor M31, the thirty-second MOS transistor M32, the thirty-fifth MOS transistor M35, and the thirty-sixth MOS transistor M36 are connected to the ground.

[0106] The gate of the twenty-seventh MOS transistor M27 is connected to the nineteenth MOS transistor M19 and the twenty-first MOS transistor M21, and the gate of the twenty-eighth MOS transistor M28 is connected to the twentieth MOS transistor M20 and the twenty-second MOS transistor M22;

[0107] The drain of the twenty-seventh MOS transistor M27 is connected to the twenty-fifth MOS transistor M25, and the twenty-eighth MOS transistor M28 is connected to the twenty-sixth MOS transistor M26;

[0108] The gates of the twenty-fifth MOS transistor M25 and the twenty-sixth MOS transistor M26 are commonly connected to the strong metastable detection clock CLKCD_s;

[0109] The drain of the twenty-fifth MOS transistor M25 is connected to the twenty-third MOS transistor 23, the twenty-ninth MOS transistor M29, the thirty-first MOS transistor M31, the thirty-third MOS transistor M33 and the thirty-fifth MOS transistor M35;

[0110] The drain of the twenty-sixth MOS transistor M26 is connected to the twenty-fourth MOS transistor M24, the thirtieth MOS transistor M30, the thirty-second MOS transistor M32, the thirty-fourth MOS transistor M34 and the thirty-sixth MOS transistor M36;

[0111] The gates of the twenty-third MOS transistor 23 and the twenty-fourth MOS transistor M24 are commonly connected to the comparison clock signal CLKC, and the sources of the twenty-third MOS transistor 23 and the twenty-fourth MOS transistor M24 and the twenty-ninth MOS transistor M29, the thirtieth MOS transistor M30, the thirty-third MOS transistor M33, and the thirty-fourth MOS transistor M34 are commonly connected to the power supply voltage.

[0112] In some embodiments, the metastable detection circuit includes a 37th MOS transistor M37, a 38th MOS transistor M38, a 39th MOS transistor M39, a 40th MOS transistor M40, a 41st MOS transistor M41, a 42nd MOS transistor M42, a 43rd MOS transistor M43, a 44th MOS transistor M44, a 45th MOS transistor M45, a 46th MOS transistor M46, a 47th MOS transistor M47, a 48th MOS transistor M48, a 49th MOS transistor M49, and a 50th MOS transistor M50, wherein the metastable flag includes a P-terminal metastable flag MD_p and an N-terminal metastable flag MD_n.

[0113] The gate of the forty-first MOS transistor M41 is connected to the nineteenth MOS transistor M19 and the twenty-first MOS transistor M21, and the forty-second MOS transistor M42 is connected to the twentieth MOS transistor M20 and the twenty-second MOS transistor M22.

[0114] The drain of the forty-first MOS transistor M41 is connected to the thirty-ninth MOS transistor M39 , and the drain of the forty-second MOS transistor M42 is connected to the fortieth MOS transistor M40 ;

[0115] The gates of the thirty-ninth MOS transistor M39 and the fortieth MOS transistor M40 are commonly connected to the metastable detection clock CLKCD; the drain of the thirty-ninth MOS transistor M39 is connected to the thirty-seventh MOS transistor M37, the forty-third MOS transistor M43, the forty-fifth MOS transistor M45, the forty-seventh MOS transistor M47, and the forty-ninth MOS transistor M49; the drain of the fortieth MOS transistor M40 is connected to the thirty-eighth MOS transistor M38, the forty-fourth MOS transistor M44, the forty-sixth MOS transistor M46, the forty-eighth MOS transistor M48, and the fiftieth MOS transistor M50.

[0116] The gates of the thirty-seventh MOS transistor M37 and the thirty-eighth MOS transistor M38 are commonly connected to the comparison clock signal CLKC, and the sources of the thirty-seventh MOS transistor M37 and the thirty-eighth MOS transistor M38 and the forty-third MOS transistor M43, the forty-fourth MOS transistor M44, the forty-seventh MOS transistor M47, and the forty-eighth MOS transistor M48 are commonly connected to a power supply voltage;

[0117] The drain of the forty-fifth MOS transistor M45 is connected to the forty-third MOS transistor M43, the forty-seventh MOS transistor M47, and the forty-ninth MOS transistor M49. The drain of the forty-sixth MOS transistor M46 is connected to the forty-fourth MOS transistor M44, the forty-eighth MOS transistor M48, and the fiftieth MOS transistor M50.

[0118] The sources of the forty-fifth MOS transistor M45 and the forty-sixth MOS transistor M46 are connected to the ground together with the forty-first MOS transistor M41, the forty-second MOS transistor M42, the forty-ninth MOS transistor M49 and the fiftieth MOS transistor M50.

[0119] In some embodiments, the clock circuit includes a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a first delay unit DLY1, a second delay unit DLY2 and a first D flip-flop, wherein:

[0120] The input of the first AND gate AND1 is connected to the output P-end strong metastable flag MD_sp and the N-end strong metastable flag MD_sn of the strong metastable detection and setting circuit, and the output is connected to the clock signal end of the first D flip-flop. The input D end of the first D flip-flop is grounded, the reset end of the first D flip-flop is connected to the start clock EN, and the output is the strong metastable flag MD_s;

[0121] When EN is 1, its output MD_s is 1; MD_s is connected together with the clock CLK to the input of the second AND gate AND2, and the output of the second AND gate AND2 is connected to the comparison clock signal CLKC; the comparison clock signal CLKC is simultaneously connected to the input of the first delay unit DLY1 and the second delay unit DLY2, and their outputs are respectively the metastable detection clock CLKCD and the strong metastable detection clock CLKCD_s;

[0122] The input of the third AND gate AND3 is connected to the output P-end metastable flag MD_p and N-end metastable flag MD_n of the metastable detection circuit, and the output is connected to the metastable flag MD.

[0123] In some embodiments, the input of the encoding circuit is connected to the P-end comparison output TP and the N-end comparison output TN of the post-stage latch circuit and the metastable flag MD in the clock circuit, and the output is a three-bit binary digital output result, from low to high, respectively, DOUT1, DOUT2 and DOUT3, where DOUT1 represents the least significant bit, DOUT2 represents the second lowest bit, and DOUT3 represents the most significant bit, where DOUT = (TP + TN not) + (TP + TN not) & MD not + MD, which can achieve 5 valid digital outputs in one comparison, while the digital DOUT of a conventional comparator = DP or DN not, and DN and DN not are the inverses of each other.

[0124] As can be seen from the above embodiments, the present application proposes a new simple logic circuit, which is composed of a low-cost conventional adder with low speed requirements, an inverter, and an AND gate. It can logically combine the comparator's comparison output signals TP and TN and the metastable state flag MD to obtain the final digital output Dout = (DP + DN not) + (DP + DN not) & MD not + MD, which can achieve five valid digital outputs in a single comparison. In contrast, the digital Dout of a conventional comparator = DP or DN not, where DN and DN not are the inverses of each other. The present application can also encode the comparison result after the comparator enters a metastable state as a valid digital output result, corresponding to the smaller input differential voltage value of the comparator at this time.

[0125] In a further embodiment, the operation process of the five-state comparator with metastable detection and correction proposed in this application can be divided into two processes: a reset phase and a comparison phase, which include:

[0126] During the reset phase, the comparison clock signal CLKC, the metastable detection clock CLKCD, and the strong metastable detection clock CLKCD_s are all at a low level; the fifth MOS transistor M5 and the sixth MOS transistor M6 in the front-stage pre-amplifier circuit 1 are turned on, the third MOS transistor M3 and the fourth MOS transistor M4 are turned off, and their outputs Vop1 and Von1 are at a high level; the MOS transistors M7, M8, M9, M10, M11, M12, M21, and M22 of the rear-stage latch circuit 2 are turned off, and the MOS transistors M13, M14, M15, M16, M19, and M20 are turned on, and the outputs TP and TN of the rear-stage latch circuit 2 are both 1. The strong metastable detection and setting circuit 3 and the metastable detection circuit 4 also enter the reset state, and their output P-end strong metastable flag MD_sp, N-end strong metastable flag MD_sn, P-end metastable flag MD_p, and N-end metastable flag MD_n are all 0.

[0127] During the comparison stage, the comparison clock signal CLKC starts to rise to a high level. The metastability detection clock CLKCD is the clock obtained by delaying CLKC at the first detection time t, and the strong metastability detection clock CLKCD_s is the clock obtained by delaying CLKC at the second detection time ts. Here, the first detection time t is the time required for the comparator output result when the comparison input is 1 / 8 LSB, and the second detection time ts is the time required for the comparator output result when the comparison input is 3 / 8 LSB. The magnitude of the second detection time ts is greater than that of the first detection time t. During the comparison stage, the fifth MOS transistor M5 and the sixth MOS transistor M6 in the pre-stage preamplification circuit 1 are turned off, and the third MOS transistor M3 and the fourth MOS transistor M4 are turned on. Their outputs Vop1 and Von1 decrease at different rates according to the magnitudes of VIP and VIN, and the signal preamplified in the first stage is latched in the post-stage latch circuit 2.

[0128] If the outputs TP and TN of the comparator flip before the rising edge of CLKCD arrives, it means that no metastability occurs in the comparison. The metastability flag bit MD is 0, and the strong metastability flag bit MD_s is 1. At this time, if TP = 1 and TN = 0, the comparison result is VIP - VIN > 3 / 8 LSB. At this time, if TP = 0 and TN = 1, the comparison result is VIP - VIN < -3 / 8 LSB;

[0129] If the outputs TP and TN of the comparator do not flip when the rising edge of CLKCD arrives, it means that the comparator has metastability, and the metastability flag bit MD is 1; then, if the outputs TP and TN of the comparator still do not flip when the rising edge of CLKCD_s arrives, it means that the metastability of the comparator is strong metastability, and the strong metastability flag bit MD_s is 0. The strong metastability detection and setting circuit 3 quickly sets the output terminals TP and TN of the comparator to 11 through the MOS transistors M17 and M18, without waiting to complete the setting after passing through combinational logic and flip-flops, and resets CLKC to a low level through the second AND gate AND2. The comparison result is -1 / 8 LSB < VIP - VIN < 1 / 8 LSB;

[0130] If the outputs TP and TN of the comparator do not flip when the rising edge of CLKCD arrives, but the outputs TP and TN of the comparator flip when the rising edge of CLKCD_s arrives, it means that the metastability that occurs in the comparator is weak metastability, the metastability flag bit MD is 1, and the strong metastability flag bit MD_s is also 1; at this time, if TP = 1 and TN = 0, the comparison result is 1 / 8 LSB < VIP - VIN < 3 / 8 LSB. At this time, if TP = 0 and TN = 1, the comparison result is -3 / 8 LSB < VIP - VIN < -1 / 8 LSB. [[ID=X]] [[ID=Y]]

[0131] In some embodiments, see Figure 2 The main node voltage operating waveforms of the five-state comparator with metastable detection and correction under different input signal conditions are as follows: Figure 2 As shown in the figure, EN is the system reset clock, CLK is the compare enable clock, CLKC is the compare clock, VIN is the N-terminal input signal of the comparator, VIP is the P-terminal input signal of the comparator, CLKCD is the metastability detection clock, CLKCD_s is the strong metastability detection clock, TP is the P-terminal output signal of the comparator, TN is the N-terminal output signal of the comparator, MD is the metastability flag signal, and MD_s is the strong metastability flag signal. The metastability detection time t is the delay from the rising edge of the compare clock CLKC to the metastability detection clock CLKCD, and the strong metastability detection time ts is the delay from the rising edge of the compare clock CLKC to the strong metastability detection clock CLKCD_s.

[0132] For further examples, please refer to Figure 1 and Figure 2 The five-state comparator with metastable detection and correction of the present application generates five different output results when the working state is described, which includes:

[0133] When the system reset signal EN is high, Figure 1 As shown in the clock circuit 5 in FIG, the high-level EN signal sets the strong metastable flag MD_s to 1 through the D flip-flop. Then, the comparison enable clock CLK first rises, CLKC is high, and the first comparison cycle begins. After the first rising edge of CLKC, the comparator performs the first comparison. When the metastable detection clock CLKCD first rises, the comparator output TP is 0 and TN is 1. The first comparison has been completed, indicating that no metastable state has occurred. Figure 1 The metastable detection circuit 4 outputs MD_p as 0, MD_n as 0, and the metastable flag MD after passing through the AND gate is 0; when the strong metastable detection clock CLKCD_s first rises, the comparator output TP is still 0, TN is 1, Figure 1 The strong metastable detection and setting circuit 3 in the circuit outputs MD_p as 0 and MD_n as 1. After passing through the AND gate, MD_spn is 0 and is not triggered. Figure 1 In the D flip-flop of clock circuit 5, the strong metastable flag MD_s is still 1, and the corresponding input signal range is VIP-VI N<-0.375LSB.

[0134] Similarly, when the second rising edge of the comparison enable clock CLK arrives, the second comparison cycle begins. After the second rising edge of CLKC arrives, the comparator performs the second comparison. When the second rising edge of the metastability detection clock CLKCD arrives, the comparator output TP is 1 and TN is 0, indicating that the second comparison has output the result. At this time, the metastability flag bit MD is 0, and the strong metastability flag bit MD_s is 1. The corresponding input signal range at this time is VIP-VI N>0.375LSB.

[0135] In the third comparison cycle, when the third rising edge of the metastable detection clock CLKCD arrives, the comparator outputs TP and TN are both 1, and the third comparison has not yet output a result. This indicates that the third comparison has occurred in a metastable state, and the metastable flag MD is 0. When the third rising edge of the strong metastable detection clock CLKCD_s arrives, the comparator output TP is 0 and TN is 1. The metastable state of the comparator is a weak metastable state, and the strong metastable flag MD_s is 1. At this time, the corresponding input signal range is -0.375LSB <VIP-VI N<0.125LSB。

[0136] In the fourth comparison cycle, when the fourth rising edge of the metastable detection clock CLKCD arrives, the comparator outputs TP and TN are both 1, and the fourth comparison has not yet output a result. This indicates that the fourth comparison has occurred in a metastable state, and the metastable flag MD is 0. When the fourth rising edge of the strong metastable detection clock CLKCD_s arrives, the comparator output TP is 1, TN is 0, and the metastable state of the comparator is a weak metastable state. The strong metastable flag MD_s is 1, and the corresponding input signal interval is 0.125LSB. <VIP-VI N<0.375LSB。

[0137] In the fifth comparison cycle, when the fifth rising edge of the metastable detection clock CLKCD arrives, the comparator outputs TP and TN are both 1, and the fifth comparison has not yet output the result. This indicates that the fifth comparison has occurred in a metastable state, and the metastable flag MD is 1. When the fifth rising edge of the strong metastable detection clock CLKCD_s arrives, the comparator outputs TP and TN are also 1. Figure 1 The strong metastable detection and setting circuit 3 in the output MD_sp is 1, MD_sn is 1, so that Figure 1 in Figure 1 The strong metastable detection and setting circuit 3 in M17 and M18 is turned on, TP and TN are quickly set to 1, the current comparison result is no longer affected by the metastable state, and the outputs TP and TN are both set to 1; and MD_sp and MD_sn are 1 after the AND gate, triggering Figure 1In the D flip-flop of the 5-clock circuit, the strong metastable flag MD_s is 0, CLKC will be reset to a low level, and the comparator will also enter the reset state as a whole. The metastable state of the comparator is a strong metastable state, and the corresponding input signal range is 0.125LSB. <VIP-VI N<0.375LSB。

[0138] By combining the three output signals obtained from a single comparison of the comparator, namely the comparison output signals TP and TN and the metastable flag MD, through a new simple logic combination, the digital output Dout = (DP + DN not) + (DP + DN not) & MD not + MD can be achieved. Five valid digital outputs can be achieved from a single comparison. For further explanation, the specific five comparison outputs, the relationship between the comparison results and the digital output, and the conversion are as follows: Figure 3 As shown, the digital output of a conventional comparator can only be Dout=DP or DN not, where DN and DN not are the inversions of each other.

[0139] A five-state quantization successive approximation method proposed to meet one of the objectives of the present application is applied to any of the above-mentioned five-state comparators with metastable detection and correction, comprising:

[0140] Step (1): During the first approximation, the input signal is compared with 1 / 2 of the quantization reference value. If the input signal is greater than 1 / 2 + 3 / 2, N+3 , it is marked as the first state;

[0141] If the input signal is less than 1 / 2-3 / 2 N+3 , it is marked as the second state;

[0142] If the input signal is between 1 / 2-3 / 2 N+3 to 1 / 2+3 / 2 N+3 If the input signal is between , it means that the preliminary interval where the input signal is located has been found, and the next approximation is not performed. Within the preliminary interval, the state is further subdivided into the third state, the fourth state, and the fifth state according to the specific range of the input signal;

[0143] Among them, if the input signal is 1 / 2+1 / 2 N+3 to 1 / 2+3 / 2 N+3 Between, it is marked as the third state;

[0144] If the input signal is between 1 / 2-3 / 2 N+3 to 1 / 2-1 / 2 N+3 Between, it is marked as the fourth state,

[0145] If the input signal is within 1 / 2±1 / 2 N+3 , it is marked as the fifth state;

[0146] If the approximation result is the first state or the second state, the next approximation is performed and step (2) is continued;

[0147] Step (2): perform a second successive approximation according to the state of the first successive approximation; if the result of the first successive approximation is the first state, then compare the input signal with 3 / 4±3 / 2 N+3 and 3 / 4±1 / 2 N+3 The intervals are compared to produce one of five approximation states;

[0148] If the result of the first successive approximation is the second state, the input signal and 1 / 4±3 / 2 N+3 and 1 / 4±1 / 2 N+3 Interval comparison, resulting in one of five approximation states;

[0149] If the successive approximation is the third state, the fourth state or the fifth state, it means that the signal interval has been found and the approximation process ends; if the successive approximation is the first state or the second state, the next approximation is continued and the process goes to step (3);

[0150] Step (3) and so on, repeat the above approximation process until the Nth successive approximation is completed. If the third state, the fourth state or the fifth state is obtained during a certain successive approximation comparison process, it indicates that the signal interval has been determined and the approximation process is completed.

[0151] Specifically, based on the aforementioned five-state comparator with metastable detection and correction, the present application further provides a five-state quantization successive approximation method that can be applied to an N-bit successive approximation ADC. The method can accurately quantize analog input signals within the full scale range of 0 to 1 and effectively identify and process metastable states, comprising the following steps:

[0152] Step 100: During the first approximation, the input signal is compared with 1 / 2 of the quantization reference value:

[0153] If the input signal is greater than 1 / 2 plus an offset adjusted according to N (specifically 3 / 2 N+3 ), it is marked as state 1; if the signal is less than 1 / 2-3 / 2 N+3 If the signal is between 1 / 2 plus the offset and 1 / 2, the signal is in 1 / 2±3 / 2. N+3 If the signal is within the range, it means that the range where the signal is located has been found and no further approximation is performed. Within this range, it is further subdivided into state 3, state 4 and state 5 according to the specific range of the signal. At this time, if the input signal is greater than 1 / 2+1 / 2 N+3 and is less than 1 / 2+3 / 2 N+3 , it is marked as state three. At this time, if the input signal is greater than 1 / 2-3 / 2N+3 And less than 1 / 2-1 / 2 N+3 , it is marked as state 4. At this time, if the input signal is at 1 / 2±1 / 2 N+3 , it is marked as state five.

[0154] If the approximation result is state 1 or state 2, the next approximation is performed and the process goes to step 200;

[0155] Step 200: Perform a second successive approximation based on the state of the first successive approximation. If the result of the first successive approximation is state 1, the signal is compared with the two boundary values ​​of 3 / 4 (3 / 4 plus and minus the offset), i.e., with 3 / 4±3 / 2. N+3 and 3 / 4±1 / 2 N+3 Interval comparison generates one of five possible approximation states; if the first successive approximation result is state 2, the signal continues to be 1 / 4±3 / 2 N+3 and 1 / 4±1 / 2 N+3 The interval comparison generates one of five possible approximation states; if the successive approximation is state three, state four, or state five, it means that the signal interval has been found and the approximation process ends; if the successive approximation is state one or state two, the next approximation is continued.

[0156] Step 300, and so on, repeat the above approximation process until the Nth successive approximation is completed. If the state is state 3, state 4 or state 5 during a successive approximation comparison process, it indicates that the signal interval has been determined and the approximation process ends.

[0157] In some embodiments, when no metastable state occurs in the i-th conversion, i is an integer greater than or equal to 2 and less than or equal to N, then the three-digit binary quantization result D(i) ultimately output by the bit conversion is equal to DOUT(i);

[0158] If the i-th conversion is metastable, the quantization result D(i) of the current bit to the quantization result D(2) of the second lowest bit are all equal to 010, and the quantization result D(1) of the lowest bit is equal to DOUT(i) obtained by the current bit comparison;

[0159] Finally, the high-order quantization result is shifted two bits to the left and added to the low-order digital result. N conversions are performed to obtain N groups of three-bit binary quantization results. After adding two shifted bits, (N+2) valid quantization bits are obtained.

[0160] The above method can generate 2 by N times of successive approximation comparison. N+2-3 different quantization results; provides a more refined quantization mapping for input signals in the range of 0 to 1. For signals with inputs of 0 to 1, the corresponding digital mappings are 000…000, 000…001,…, 111…100 (N+2-bit binary output), and the corresponding digital output is (N+2)-bit binary code. The quantization signal-to-noise ratio is 20*log(2 N+2 -3), close to an N+2-bit two-state successive approximation quantization signal-to-noise ratio (20*log(2 N+2 )), thereby achieving higher precision and higher speed analog-to-digital conversion while processing the metastable state.

[0161] In some embodiments, the above method is further described using the example where N is equal to 2. Figure 4 As shown, Figure 4 The following is a schematic diagram of the mathematical form of the successive approximation method for five-state quantization proposed in this application and the traditional two-state quantization successive approximation method when N is 2, that is, the two approximation processes. It can be seen that in the traditional two-state quantization successive approximation method, each conversion needs to be strictly approximated with a single reference quantization line, i.e., 1 / 2, 1 / 4 and 3 / 4, and two complete successive approximations need to be completed, resulting in a total of 00, 01, 10, 11, and 4 comparison results. The five-state quantization successive approximation method proposed in this application approximates the interval of the reference quantization line. When it approaches the position of 1 / 16 of the reference quantization line, the signal interval has been found, and there is no need to perform the next approximation. A total of 13 comparison results can be generated: 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100,

[0162] like Figure 5As shown, this is a flowchart of the workflow of the five-state successive approximation analog-to-digital converter of the embodiment of the present application. For an N-bit five-state SAR ADC, after sampling, comparison begins. In the (k)th comparison, whether the comparator is in a metastable state is determined based on whether the comparison time tcomp is greater than the metastable detection time tw. If tcopm is less than tw, no metastable state occurs in the comparison, MD(k) is 0, TP(k) is not equal to TN(k), and TP(k) and TN(k) are not set. TP(k) and TN(k) are the corresponding comparison results. If tcopm is greater than tw, metastable state occurs in the comparison, and the next comparison is not performed. MD(k) is 1. Further, whether the comparison time tcomp is greater than the strong metastable detection time ts is determined to determine whether the comparator's metastable state is a strong metastable state. If tcopm is greater than tw and less than ts, the metastable state in which the comparison occurs is a weak metastable state, and the next comparison is not performed. TP(k) is not equal to TN(k), and TP(k) and TN(k) are not set. TP(k) and TN(k) are the corresponding comparison results. If tcopm is greater than tw and greater than ts, the metastable state in which the comparison occurs is a strong metastable state, and the next comparison is not performed. TP(k) and TN(k) are set, and both TP(k) and TN(k) are set to 1.

[0163] For the digital output coding of the five-state successive approximation analog-to-digital converter of the embodiment of the present application, a new combinational logic circuit is used. The three-digit binary digital result DOUT(k) obtained by the k-th conversion is DOUT(k) = (DP(k) + DN(k) not) + (DP(k) + DN(k) not) & MD(k) not + MD(k). If no metastable state occurs in the i-th conversion, i is an integer greater than or equal to 2 and less than or equal to N, and the three-digit binary quantization result D(i) finally output by the conversion of this bit is equal to DOUT(i); if a metastable state occurs in the i-th conversion, the quantization result D(i) of the current bit to the quantization result D(2) of the second lowest bit are all equal to 010, and the lowest bit quantization result D(1) is equal to DOUT(i) obtained by the current bit comparison; finally, the high-bit quantization result is shifted two bits to the left and then added to the low-bit digital result. N groups of three-digit binary quantization results are obtained by N conversions, and after the 2-bit addition, (N+2) valid quantization bits are obtained.

[0164] In order to further verify the technical effect of the present application, as another embodiment, the inventor conducted the following experiment. In a 40nm CMOS process, a SAR ADC with a 7-bit conversion and a 600MHz sampling rate was designed. The same simulation experiment was conducted on the traditional two-state comparator and two-state quantization circuit and the five-state comparator and five-state quantization circuit with metastable detection and correction of the present application. The same simulation conditions were used, and the same parts of the tubes, such as the input / output tubes, were of the same size and the same load capacitance. The two structures were compared. The simulation results are shown in the figure. Figure 6 and Figure 7 As shown. Figure 6 It can be seen that the signal-to-noise and distortion ratio (SNDR) of the circuit using the traditional two-state comparator and two-state quantization is 39.65dB, and the spurious free dynamic range (SFDR) is 53.79dB; Figure 7 It can be seen that after adopting the five-state comparator and five-state quantization circuit of this application, the SNDR is 53.90dB and the SFDR is 72.06dB. It can be seen that after adopting this application, the SNDR is improved by 14.25dB, which shows that this technology can suppress metastability while reducing the impact of the noise performance of the comparator, and use metastable information for effective quantization coding, improving the quantization accuracy by nearly 2 bits.

[0165] As can be seen from the above embodiments, compared with the prior art, the present application addresses the problem that conventional comparators in the prior art can usually only obtain two output results in one comparison. When the continuous analog input signal approaches the reference quantization lines such as 1 / 2 and 1 / 4, the output decision time of the comparator will be significantly prolonged, resulting in a longer ADC conversion time. The present application includes but is not limited to the following beneficial effects:

[0166] First, the present invention overcomes the shortcomings of existing successive approximation analog-to-digital converters, such as the inability to obtain reliable logical results due to metastable states, which limits the comparison speed and accuracy. It also overcomes the disadvantage that existing successive approximation analog-to-digital converters can only perform inefficient two-state quantization due to the comparator output having only two states.

[0167] Secondly, the present application divides the metastable state of the comparator into strong metastable state and weak metastable state by setting two metastable detection boundary values ​​of 1 / 8LSB and 3 / 8LSB. When the differential input of the comparator is less than 1 / 8LSB, it is a strong metastable state. When the differential input of the comparator is between 1 / 8LSB and 3 / 8LSB, it is a weak metastable state. When the differential input of the comparator is greater than 3 / 8LSB, no metastable state occurs. Compared with the traditional two-state comparator, the present application has five valid output results for each comparison, which can suppress the metastable state while using the metastable information to improve the accuracy.

[0168] Third, the five-state comparator of the present application adopts a fully differential structure, which can directly perform metastable detection on both ends of the comparator's output at the same time without going through an XOR gate, and after detecting the occurrence of a strong metastable state, the voltage at both ends of the comparator's output can be directly set, without going through combinational logic and triggers to set the voltage at both ends of the comparator's output. The metastable detection and correction circuit of the present application is faster and more accurate.

[0169] Fourthly, the present application uses two identical NMOS transistors to set the comparator when a strong metastable state occurs, setting both ends of the comparator output to 11 in the reset state. The traditional solution uses one NMOS and one PMOS transistor to set both ends of the comparator output to 10, which is an invalid output result. The present application also encodes the output of the comparator after the metastable state occurs and the metastable state flag as a valid comparison result through a new simple logic circuit, corresponding to the smaller input differential voltage value of the comparator at this time. This overcomes the disadvantage of the traditional two-state comparator that requires a long comparison decision time when the differential input is very small. This method can perform metastable detection and correction without introducing additional offset voltage, thereby improving the accuracy of the comparator.

[0170] Fifth, this application proposes a new simple logic circuit, consisting of a low-cost conventional adder with low speed requirements, an inverter, and an AND gate. This circuit can logically combine the comparator's comparison output signals TP and TN and the metastable state flag MD to produce a binary valid digital output DOUT = (TP + TN NOT) + (TP + TN NOT) & MD NOT + MD. This circuit can achieve five valid digital outputs per comparison, while a conventional comparator's digital DOUT = DP or DN NOT, where DN and DN NOT are the inverses of each other. This application can also encode the comparison result after the comparator enters a metastable state as a valid digital output, corresponding to the comparator's smaller input differential voltage value at this time.

[0171] Sixth, the five-state quantization successive approximation method proposed in this application can greatly improve the quantization efficiency compared to the traditional two-state quantization successive approximation method. One quantization has five different valid quantization results, which can accurately quantize the analog input signal within the full range of 0 to 1, and effectively identify and process metastable states. If the size of the input differential signal is within 3 / 8 of the quantization accuracy during a certain successive approximation comparison process, it indicates that the signal interval has been determined and the approximation process is completed. N-bit quantization has (2N+2-3) quantization results, which can improve the quantization accuracy by nearly 2 bits compared to the traditional two-state quantization.

[0172] The above description is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A five-state comparator with metastable detection and correction, characterized in that: include: A front-stage pre-amplifier circuit, which is used to pre-amplify the input differential signal and then output the signal to the rear-stage latch circuit; The post-stage latch circuit latches and outputs the comparison result of the comparator through multiple MOS tubes; A strong metastable state detection and setting circuit, which is used to detect whether the comparator is in a strong metastable state and to set the output of the comparator, and if the strong metastable state is detected, a strong metastable state flag is generated; A metastable state detection circuit, which is used to detect and identify whether the comparator is in a metastable state, and if the comparator is detected to be in a metastable state, a metastable state identification bit is generated; A clock circuit, which is used to generate clock signals corresponding to the working clock, metastable detection clock and strong metastable detection clock of the comparator; The encoding circuit is used to combine the output of the comparator and the metastable flag bit to output a digital output result.

2. A five-state comparator with metastable detection and correction according to claim 1, characterized in that: The front-stage pre-amplification circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor, wherein the gates of the first MOS transistor and the second MOS transistor are respectively connected to a positive input signal VIP and a negative input signal VIN, and the sources of the first MOS transistor and the second MOS transistor are commonly connected to the ground; The drain of the first MOS tube is connected to the third MOS tube, and the drain of the second MOS tube is connected to the fourth MOS tube; The gates of the third MOS tube and the fourth MOS tube, and the gates of the fifth MOS tube and the sixth MOS tube are commonly connected to a comparison clock signal CLKC; The drain of the third MOS tube is connected to the fifth MOS tube, the drain of the fourth MOS tube is connected to the sixth MOS tube, and the sources of the fifth MOS tube and the sixth MOS tube are commonly connected to a power supply voltage.

3. A five-state comparator with metastable detection and correction according to claim 1, characterized in that: The post-stage latch circuit includes a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube and a twenty-second MOS tube; Wherein, the gates of the seventh MOS tube and the eighth MOS tube are respectively connected to the third MOS tube and the fourth MOS tube, the thirteenth MOS tube and the fourteenth MOS tube, the fifteenth MOS tube and the sixteenth MOS tube; The source electrodes of the seventh MOS tube and the eighth MOS tube are connected to the power supply voltage together with the nineteenth MOS tube and the twentieth MOS tube; The drain of the seventh MOS tube is connected to the ninth MOS tube and the fifteenth MOS tube respectively, and the drain of the eighth MOS tube is connected to the tenth MOS tube and the sixteenth MOS tube respectively; The gate of the ninth MOS tube is connected to the eleventh MOS tube, the twelfth MOS tube and the fourteenth MOS tube; The gate of the tenth MOS tube is connected to the eleventh MOS tube, the twelfth MOS tube and the thirteenth MOS tube; The drain of the ninth MOS tube is connected to the nineteenth MOS tube and the twenty-first MOS tube, and the drain of the tenth MOS tube is connected to the twentieth MOS tube and the twenty-second MOS tube; Sources of the eleventh MOS tube, the twelfth MOS tube, the thirteenth MOS tube, the fourteenth MOS tube, the fifteenth MOS tube, the nineteenth MOS tube, the twentieth MOS tube, the twenty-first MOS tube and the twenty-second MOS tube are connected to the ground in common.

4. A five-state comparator with metastable detection and correction according to claim 1, characterized in that: The strong metastable detection and setting circuit includes a seventeenth MOS tube, an eighteenth MOS tube, a twenty-third MOS tube, a twenty-fourth MOS tube, a twenty-fifth MOS tube, a twenty-sixth MOS tube, a twenty-seventh MOS tube, a twenty-eighth MOS tube, a twenty-ninth MOS tube, a thirtieth MOS tube, a thirty-first MOS tube, a thirty-second MOS tube, a thirty-third MOS tube, a thirty-fourth MOS tube, a thirty-fifth MOS tube, and a thirty-sixth MOS tube, wherein the strong metastable flag includes a P-end strong metastable flag MD_sp and an N-end strong metastable flag MD_sn; Wherein, the drain of the seventeenth MOS tube is connected to the twenty-first MOS tube, and the drain of the eighteenth MOS tube is connected to the twenty-second MOS tube; The gate of the seventeenth MOS tube is connected to the twenty-ninth MOS tube, the thirty-first MOS tube, the thirty-third MOS tube and the thirty-fifth MOS tube, and the gate of the eighteenth MOS tube is connected to the thirtieth MOS tube, the thirty-second MOS tube, the thirty-fourth MOS tube and the thirty-sixth MOS tube; The source electrodes of the seventeenth MOS tube and the eighteenth MOS tube are connected to the ground together with the twenty-seventh MOS tube, the twenty-eighth MOS tube, the thirty-first MOS tube, the thirty-second MOS tube, the thirty-fifth MOS tube, and the thirty-sixth MOS tube; The gate of the 27th MOS tube is connected to the 19th MOS tube and the 21st MOS tube, and the gate of the 28th MOS tube is connected to the 20th MOS tube and the 22nd MOS tube; The drain of the twenty-seventh MOS tube is connected to the twenty-fifth MOS tube, and the twenty-eighth MOS tube is connected to the twenty-sixth MOS tube; The gates of the twenty-fifth MOS transistor and the twenty-sixth MOS transistor are commonly connected to the strong metastable detection clock CLKCD_s; The drain of the twenty-fifth MOS tube is connected to the twenty-third MOS tube, the twenty-ninth MOS tube, the thirty-first MOS tube, the thirty-third MOS tube and the thirty-fifth MOS tube; The drain of the twenty-sixth MOS tube is connected to the twenty-fourth MOS tube, the thirtieth MOS tube, the thirty-second MOS tube, the thirty-fourth MOS tube and the thirty-sixth MOS tube; The gates of the twenty-third MOS tube and the twenty-fourth MOS tube are commonly connected to the comparison clock signal CLKC, and the sources of the twenty-third MOS tube and the twenty-fourth MOS tube are commonly connected to the power supply voltage as well as the twenty-ninth MOS tube, the thirtieth MOS tube, the thirty-third MOS tube, and the thirty-fourth MOS tube.

5. A five-state comparator with metastable detection and correction according to claim 1, characterized in that: The metastable detection circuit includes a thirty-seventh MOS tube, a thirty-eighth MOS tube, a thirty-ninth MOS tube, a forty-first MOS tube, a forty-second MOS tube, a forty-third MOS tube M43, a forty-fourth MOS tube, a forty-fifth MOS tube, a forty-sixth MOS tube, a forty-seventh MOS tube, a forty-eighth MOS tube, a forty-ninth MOS tube, and a fiftieth MOS tube, wherein the metastable flag includes a P-end metastable flag MD_p and an N-end metastable flag MD_n; Wherein, the gate of the 41st MOS tube is connected to the 19th MOS tube and the 21st MOS tube, and the 42nd MOS tube is connected to the 20th MOS tube and the 22nd MOS tube; The drain of the forty-first MOS tube is connected to the thirty-ninth MOS tube, and the drain of the forty-second MOS tube is connected to the fortieth MOS tube; The gates of the thirty-ninth MOS tube and the fortieth MOS tube are commonly connected to the metastable detection clock CLKCD; the drain of the thirty-ninth MOS tube is connected to the thirty-seventh MOS tube, the forty-third MOS tube, the forty-fifth MOS tube, the forty-seventh MOS tube, and the forty-ninth MOS tube; the drain of the fortieth MOS tube is connected to the thirty-eighth MOS tube, the forty-fourth MOS tube, the forty-sixth MOS tube, the forty-eighth MOS tube, and the fiftieth MOS tube; The gates of the thirty-seventh MOS tube and the thirty-eighth MOS tube are commonly connected to the comparison clock signal CLKC, and the sources of the thirty-seventh MOS tube and the thirty-eighth MOS tube are commonly connected to the power supply voltage as well as the forty-third MOS tube, the forty-fourth MOS tube, the forty-seventh MOS tube and the forty-eighth MOS tube; The drain of the forty-fifth MOS tube is connected to the forty-third MOS tube, the forty-seventh MOS tube and the forty-ninth MOS tube, and the drain of the forty-sixth MOS tube is connected to the forty-fourth MOS tube, the forty-eighth MOS tube and the fiftieth MOS tube; The sources of the forty-fifth MOS tube and the forty-sixth MOS tube are connected to the ground together with the forty-first MOS tube, the forty-second MOS tube, the forty-ninth MOS tube and the fiftieth MOS tube.

6. A five-state comparator with metastable detection and correction according to any one of claims 1 to 5, characterized in that: The clock circuit includes a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a first delay unit DLY1, a second delay unit DLY2 and a first D flip-flop, wherein: The input of the first AND gate AND1 is connected to the output P-end strong metastable flag MD_sp and N-end strong metastable flag MD_sn of the strong metastable detection and setting circuit, and the output is connected to the clock signal end of the first D flip-flop, the input D end of the first D flip-flop is grounded, the reset end of the first D flip-flop is connected to the start clock EN, and the output is the strong metastable flag MD_s; When EN is 1, its output MD_s is 1; MD_s is connected to the input end of the second AND gate AND2 together with the clock CLK, and the output end of the second AND gate AND2 is connected to the comparison clock signal CLKC; the comparison clock signal CLKC is simultaneously connected to the input ends of the first delay unit DLY1 and the second delay unit DLY2, and their outputs are respectively the metastable detection clock CLKCD and the strong metastable detection clock CLKCD_s; The input of the third AND gate AND3 is connected to the output P-end metastable flag MD_p and N-end metastable flag MD_n of the metastable detection circuit, and the output is connected to the metastable flag MD.

7. A five-state comparator with metastable detection and correction according to any one of claims 1 to 5, characterized in that: The input of the encoding circuit is connected to the P-end comparison output TP and the N-end comparison output TN of the post-stage latch circuit and the metastable identification bit MD in the clock circuit, and the output is a three-bit binary digital output result, which are DOUT1, DOUT2 and DOUT3 from low to high, respectively, where DOUT1 represents the least significant bit, DOUT2 represents the second lowest bit, DOUT3 represents the most significant bit, and DOUT=(TP+TN not)+(TP+TN not)&MD not+MD.

8. A five-state quantization successive approximation method, applied to the five-state comparator with metastable detection and correction as claimed in claims 1 to 7, characterized in that: include: Step (1), at the first approximation, compare the input signal with 1 / 2 of the quantization reference value. If the input signal is greater than 1 / 2 + 3 / 2 N+3 , it is marked as the first state; If the input signal is less than 1 / 2-3 / 2 N+3 , then it is marked as the second state; If the input signal is between 1 / 2-3 / 2 N+3 to 1 / 2+3 / 2 N+3 If the input signal is between , it means that the preliminary interval where the input signal is located has been found, and the next approximation is not performed. Within the preliminary interval, according to the specific range of the input signal, it is further subdivided into a third state, a fourth state and a fifth state; Among them, if the input signal is 1 / 2+1 / 2 N+3 to 1 / 2+3 / 2 N+3 If the state is between , it is marked as the third state; If the input signal is between 1 / 2-3 / 2 N+3 to 1 / 2-1 / 2 N+3 Between, it is marked as the fourth state, If the input signal is within 1 / 2±1 / 2 N+3 , then it is marked as the fifth state; If the approximation result is the first state or the second state, the next approximation is performed and step (2) is continued; Step (2), performing a second successive approximation according to the state of the first successive approximation; if the result of the first successive approximation is the first state, then the input signal is compared with 3 / 4±3 / 2 N+3 and 3 / 4±1 / 2 N+3 The intervals are compared, and one of five approximation states is produced; If the result of the first successive approximation is the second state, the input signal and 1 / 4±3 / 2 N+3 and 1 / 4±1 / 2 N+3 Interval comparison, producing one of five approximation states; If the successive approximation is the third state, the fourth state or the fifth state, it means that the signal interval has been found and the approximation process ends; if the successive approximation is the first state or the second state, the next approximation is continued and the process goes to step (3); Step (3), and so on, repeat the above approximation process until the Nth successive approximation is completed. If the third state, the fourth state or the fifth state is obtained in a certain successive approximation comparison process, it indicates that the signal interval has been determined and the approximation process is terminated.

9. A five-state quantization successive approximation method according to claim 8, characterized in that: include: When no metastable state occurs in the i-th conversion, i is an integer greater than or equal to 2 and less than or equal to N, then the three-bit binary quantization result D(i) finally output by the bit conversion is equal to DOUT(i); If the i-th conversion is metastable, the quantization result D(i) of the current bit to the quantization result D(2) of the second lowest bit are all equal to 010, and the quantization result D(1) of the lowest bit is equal to DOUT(i) obtained by the current bit comparison; Finally, the high-order quantization result is shifted two bits to the left and added to the low-order digital result. N conversions are performed to obtain N groups of three-bit binary quantization results. After 2-bit shifted addition, (N+2) valid quantization bits are obtained.

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