High-precision slope generator and two-step single-slope analog-to-digital converter

Abstract

The invention discloses a high-precision slope generator and a two-step single-slope analog-to-digital converter. The slope generator comprises a band-gap reference source circuit, a voltage-current conversion circuit, a weight current DAC current source array, a charging and discharging current regulation and control circuit, a mode switching circuit and a biasing circuit. In the invention, the quantization process of the ramp generator is decomposed into two stages of coarse quantization and fine quantization, the quantization time is greatly reduced, and one output stage can be combined with the DAC type ramp generator and the capacitance integration type ramp generator, so that the area and the power consumption in chip design are saved, the compatibility of the ramp generator is improved, and the power consumption is reduced. The problems of linearity and stability introduced by the stepped slope under high-speed and high-precision application are solved, and the design complexity is reduced.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, and in particular relates to a high-precision ramp generator and a two-step single-slope analog-to-digital converter. Background Art

[0002] Single-Slope Analog-to-Digital Converter (SS-ADC) has been widely used in modern CMOS (Complementary Metal Oxide Semiconductor) image sensors. As an important part of SS-ADC, the ramp generator is responsible for generating the quantization ramp and quantizing the pixel signal in conjunction with comparator and counter circuits. Its performance determines the accuracy and conversion speed of SS-ADC, which directly affects the resolution and readout frame rate of the image sensor.

[0003] As the pixel array of CMOS image sensors becomes larger and larger, and the performance becomes higher and higher, the overall readout circuit architecture that only uses column-parallel ADCs can no longer meet application requirements. In order to improve performance, various SS-ADCs have also been designed and used, such as multi-slope SS-ADCs, multi-slope SS-ADCs, and TDC-compatible SS-ADCs. The SS-ADCs of the above structures can be collectively referred to as two-step SS-ADCs, among which the multi-slope two-step SS-ADCs are used and studied more frequently. The principle is to divide the quantization of a pixel signal into two times, and divide the quantization process of M-bit precision into C-bit coarse quantization and F-bit fine quantization, and satisfy M=C+F. First, use the coarse quantization slope to find the voltage range of the pixel signal. The characteristic of the coarse slope is a large voltage span. Suppose the quantization range is V range , then the voltage of the coarse quantization ramp changes each time is V range / 2 C After determining a specific small interval, a fine slope is then connected, which can reduce the clock cycle occupied by quantization by 2 M Optimized to 2 C +2 F , while greatly improving the quantization speed, the signal quantization with M-bit accuracy is completed. Its disadvantage is that it requires a high design complexity of the ramp generator. When the number of coarse quantization ramp bits is 2 C , then 2 C The ramp generator has two fine ramp voltages with the same slope and different voltage ranges, which requires high design complexity and power consumption. Therefore, as an important part of the SS-ADC to achieve two-step quantization, it is necessary to further improve and optimize the ramp generator. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a high-precision ramp generator and a two-step single-slope analog-to-digital converter.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0006] A high-precision ramp generator has a DAC type ramp generator working mode and a capacitor integration type ramp generator working mode, including

[0007] Bandgap reference source circuit, used to generate reference voltage V bg ;

[0008] Voltage-current conversion circuit, used to convert the reference voltage V bg Converted into a stable current I c , and mirror current I c Provides a current source array and a charge and discharge current control circuit to a weighted current DAC;

[0009] The weighted current DAC current source array is used to output a step voltage V in the DAC type ramp generator working mode. dac ;

[0010] The charge and discharge current control circuit is used to output the charge and discharge current I in the capacitor integral ramp generator working mode. charge ;

[0011] The mode switching circuit is used to switch the ramp voltage V according to the ladder ramp voltage V in the DAC type ramp generator working mode. dac Output a periodically changing step-type ramp signal; and in the capacitor integral ramp generator working mode according to the charge and discharge current I charge Outputting a linearly varying ramp signal; and

[0012] Bias circuit for generating the ramp start voltage V ref Provided to the mode switching circuit.

[0013] Furthermore, the voltage-current conversion circuit includes an operational amplifier A1, a resistor R BG and PMOS tube P0, the in-phase output terminal of the operational amplifier A1 is connected to the reference voltage V bg , the inverting input of the operational amplifier A1 is connected through the resistor R BG grounded; the inverting input terminal of the operational amplifier A1 is also electrically connected to the drain of the PMOS tube P0, the output terminal of the operational amplifier A1 is electrically connected to the gate of the PMOS tube P0, and the source of the PMOS tube P0 is connected to the supply voltage.

[0014] Furthermore, the weighted current DAC current source array includes a resistor R DACand n-stage mirror current source circuits, each of which includes a mirror tube unit and a current source control switch, the sources of the n mirror tube units are connected to the power supply voltage, the gates of the n mirror tube units are electrically connected to the output end of the operational amplifier A1, and the drain of each mirror tube unit is connected to the resistor R through a current source control switch. DAC The first end is electrically connected to the resistor R DAC The second end is grounded.

[0015] Furthermore, the mirror tube units of each level of the mirror current source circuit respectively include 2 i-1 There are reference PMOS tubes connected in parallel, where i represents the number of stages of the mirror current source circuit, 1≤i≤n.

[0016] Further, the charge and discharge current control circuit includes a PMOS tube P1, an NMOS tube N0, an NMOS tube N1 and an NMOS tube N2, the source of the PMOS tube P1 is connected to the power supply voltage, the gate of the PMOS tube P1 is electrically connected to the output end of the operational amplifier A1, the drain of the PMOS tube P1 is electrically connected to the drain of the NMOS tube N0, the gate of the NMOS tube N0, the drain of the NMOS tube N1 and the gate of the NMOS tube N2 respectively, the sources of the NMOS tube N0, the NMOS tube N1 and the NMOS tube N2 are all grounded, the gate of the NMOS tube N1 is connected to the mode control signal Vbn, and the drain of the NMOS tube N2 is used to output the charge and discharge current I charge When the high-precision ramp generator works in the DAC type ramp generator working mode, the control signal Vbn turns on the NMOS tube N1; when the high-precision ramp generator works in the capacitor integration type ramp generator working mode, the control signal Vbn turns off the NMOS tube N1.

[0017] Furthermore, the width-to-length ratio of the NMOS transistor N2 is obtained by reducing or enlarging the width-to-length ratio of the NMOS transistor N0 according to a predetermined ratio.

[0018] Furthermore, the mode switching circuit includes

[0019] The ramp signal output buffer circuit is used to work as a buffer driver stage in the DAC type ramp generator working mode to drive the step-type ramp voltage V dac Forming a step-type ramp voltage; and working as an integral operation circuit in the capacitor integral ramp generator working mode, with the ramp starting voltage V ref is the reference voltage, through the charge and discharge current I charge forming a linear ramp voltage; and

[0020] The switched capacitor circuit includes the ramp sampling capacitor C s, used to connect the step-type ramp signal to the ramp sampling capacitor C in the DAC type ramp generator working mode s The upper plate of the ramp starts at voltage V ref Connect the ramp sampling capacitor C s The lower plate of the capacitor is used to output a ramp signal; and in the capacitor integral ramp generator working mode, the linear ramp voltage is connected to the ramp sampling capacitor C s The lower plate uses the principle of capacitor charge conservation to output a linear ramp voltage as a ramp signal V ramp .

[0021] Furthermore, the ramp signal output buffer circuit includes an operational amplifier A2, a linear ramp capacitor C RAMP , Input control switch Input control switch Capacitor Control Switch and capacitor controlled switches The operational amplifier A2 is an input-output rail-to-rail operational amplifier. The in-phase input terminal of the operational amplifier A2 is controlled by an input switch. Connect the ramp starting voltage V of the bias circuit output ref , the non-inverting input of the operational amplifier A2 is also controlled by the input switch Connect the weighted current DAC current source array to the output of the step voltage V dac The inverting input terminal of the operational amplifier A2 is connected to the charge and discharge current I output by the charge and discharge current control circuit charge , the inverting input of the operational amplifier A2 is switched via a capacitor and the linear ramp capacitor C RAMP The series circuit is electrically connected to its output terminal, and the inverting input terminal of the operational amplifier A2 is also controlled by a capacitor switch. electrically connected to its output terminal;

[0022] When the high-precision ramp generator works in the DAC type ramp generator working mode, the input control switch Open, input control switch Closed, capacitor controlled switch Open, capacitor controlled switch Closed; when the high-precision ramp generator works in the capacitor integration ramp generator working mode, the input control switch Close, input control switch Open, capacitor controlled switch Closed, capacitor controlled switch Open.

[0023] Furthermore, the switch capacitor circuit also includes a capacitor control switch Capacitor Control Switch and capacitor controlled switches The ramp sampling capacitor C s The lower plate controls the switch through the capacitor is electrically connected to the output terminal of the operational amplifier A2, the ramp sampling capacitor C s The lower plate also controls the switch through the capacitor Connect the ramp starting voltage V of the bias circuit output ref ; The slope sampling capacitor C s The upper plate controls the switch through the capacitor is electrically connected to the output terminal of the operational amplifier A2, the ramp sampling capacitor C s The upper plate also serves as the output of a high-precision ramp generator to output a linear ramp voltage V ramp ;

[0024] When the high-precision ramp generator works in the DAC type ramp generator working mode, the capacitor controls the switch and capacitor controlled switches Closed, capacitor controlled switch When the high-precision ramp generator works in the capacitor integral ramp generator mode, the capacitor controls the switch. and capacitor controlled switches Open, capacitor controlled switch closure.

[0025] A two-step single slope analog-to-digital converter, comprising a ramp generator, a column comparator, a counter, a memory and a digital logic control module, wherein the ramp generator adopts a high-precision ramp generator; the non-inverting input end of the column comparator is electrically connected to the output end of the ramp generator, and the inverting input end of the column comparator is used to connect the pixel signal V output by the pixel output end. sig The output end of the column comparator is electrically connected to a counter, the counter is electrically connected to a memory, the memory is used to output the analog-to-digital conversion result, and the memory is also electrically connected to a digital logic control module, the digital logic control module is used to generate a control signal, and the control signal is used to switch the working mode of the ramp generator.

[0026] In the present invention, the quantization process of the ramp generator is decomposed into two stages, namely, coarse quantization and fine quantization, which greatly reduces the quantization time. Moreover, a DAC-type ramp generator and a capacitor-integrated ramp generator can be combined with one output stage, which saves area and power consumption in chip design, improves the compatibility of the ramp generator, solves the linearity and stability problems introduced by the step-type ramp in high-speed and high-precision applications, and reduces the design complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0028] Figure 1 It is a structural block diagram of an embodiment of a high-precision ramp generator of the present invention.

[0029] Figure 2 The circuit diagram is a voltage-current conversion circuit, a weighted current DAC current source array, a charge and discharge current control circuit, and a mode switching circuit.

[0030] Figure 3 This is an equivalent ramp generator circuit when the present embodiment works in the DAC type ramp generator working mode.

[0031] Figure 4 This is an equivalent ramp generator circuit when the present embodiment works in the capacitor integration ramp generator working mode.

[0032] Figure 5 It is a structural block diagram of an embodiment of a two-step single-slope analog-to-digital converter of the present invention.

[0033] Figure 6 Figure 2 is a timing diagram of the relevant voltages in the two-step SS-ADC.

[0034] The accompanying drawings in the specification are numeraled as follows:

[0035] Bandgap reference source circuit-1; voltage-current conversion circuit-2; weighted current DAC current source array-3; charge and discharge current control circuit-4; mode switching circuit-5; ramp signal output buffer circuit-51; switch capacitor circuit-52; bias circuit-6; mirror tube unit-PM1, PM2, ..., PMn; control switch Ramp generator-100; pixel output terminal-200; column comparator-300; counter-400; memory-500; digital logic control module-600. DETAILED DESCRIPTION

[0036] The following describes the implementation methods of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other without conflict.

[0037] At present, the implementation methods of the existing ramp generator can be divided into the following two categories. One is to use the current to integrate the capacitor to generate a ramp voltage, which is called a capacitor integration type ramp generator. This type of ramp generator can generate a continuous linear ramp signal, and can achieve a linear ramp output with different slopes according to the size of the capacitor and the charge and discharge current. It is characterized by adjustable slope of the ramp voltage, simple structure, good linearity, and good noise performance. However, the voltage accuracy is not high, and the continuous voltage form is poorly compatible with SS-ADCs with complex structures such as two-step, making it difficult to be accurately sampled. Another way is to use a digital-to-analog converter (DAC) to implement it. The DAC type ramp generator can generate a step-type step voltage as a ramp signal. It has high voltage accuracy and excellent ramp resolution, but as the number of DAC bits increases, its structure becomes more and more complex, and it also introduces obvious stability, speed, noise and other problems in different applications.

[0038] There is a patent publication number for a two-step single-slope analog-to-digital converter with a multi-slope architecture. It uses two precision current-steering DACs to generate slopes, and divides one quantization into two coarse and fine quantizations, which greatly improves the conversion speed of the SS-ADC. The ramp signal is accessed by capacitive coupling, which is compatible with the switching and connection between coarse and fine ramp voltages, solving the problems of high complexity of the ramp generator and slope connection in the traditional two-step SS-ADC. However, in the application of high-speed, large-array CMOS image sensors, the system operating frequency and the number of DAC bits are increased, which significantly reduces the slope linearity, and the design difficulty increases sharply under limited area and power consumption requirements. At the same time, the influence of DAC-type ramp voltage settling time and burr noise under high-speed and high-precision requirements is also difficult to solve.

[0039] See also Figure 1 , Figure 1 The structure block diagram of an embodiment of the high-precision ramp generator of the present invention. The high-precision ramp generator of this embodiment includes a bandgap reference source circuit 1, a voltage-current conversion circuit 2, a weighted current DAC current source array 3, a charge and discharge current control circuit 4, a mode switching circuit 5 and a bias circuit 6. The high-precision ramp generator of this embodiment has two working modes: a DAC type ramp generator working mode and a capacitor integration type ramp generator working mode. When coarse quantization is required, the high-precision ramp generator works in the DAC type ramp generator working mode; when fine quantization is required, the high-precision ramp generator works in the capacitor integration type ramp generator working mode.

[0040] See also Figure 2 The bandgap reference source circuit 1 is used to generate a reference voltage V that is independent of temperature. bg The voltage-current conversion circuit 2 is used to convert the reference voltage V bgConverted into a stable current I c , and mirrors the current I c Provided to the weighted current DAC current source array 3 and the charge and discharge current control circuit 4. The voltage-current conversion circuit 2 may include an operational amplifier A1, a resistor R BG and PMOS tube P0, the in-phase output terminal of the operational amplifier A1 is connected to the reference voltage V bg , the inverting input of the operational amplifier A1 is connected through the resistor R BG The inverting input terminal of the operational amplifier A1 is also electrically connected to the drain of the PMOS tube P0, the output terminal of the operational amplifier A1 is electrically connected to the gate of the PMOS tube P0, and the source of the PMOS tube P0 is connected to the power supply voltage.

[0041] Using the above structure, operational amplifier A1, resistor R BG and PMOS tube P0 form a negative feedback loop, which can bg Convert to a stable value V bg / R BG The current I c and through the gate voltage V of P0 tube G , mirroring the current I c It is provided to the weighted current DAC current source array 3 and the charge and discharge current control circuit 4 to generate the required ramp voltage.

[0042] Please continue reading Figure 2 The weighted current DAC current source array 3 only works in the DAC type ramp generator working mode and is used to output a step voltage V in the DAC type ramp generator working mode. dac The weighted current DAC current source array 3 may include a resistor R DAC and n-stage mirror current source circuits, where n is the number of DAC bits of the DAC type ramp generator. Each of the mirror current source circuits includes a mirror tube unit and a current source control switch, that is, the n-stage mirror current source circuit includes a mirror tube unit PM1, a mirror tube unit PM2, ..., a mirror tube unit PMn, a current source control switch Current source controlled switch ……、Current source control switch The mirror tube units of each stage of the mirror current source circuit respectively include 2 i-1 Reference PMOS tubes are connected in parallel, where i represents the number of stages of the mirror current source circuit, 1≤i≤n. That is, the mirror tube unit PM1 of the first-stage mirror current source circuit includes one reference PMOS tube, the mirror tube unit PM2 of the second-stage mirror current source circuit includes two reference PMOS tubes connected in parallel, and so on. The mirror tube unit PMn of the n-stage mirror current source circuit includes twon-1 The reference PMOS tubes are connected in parallel.

[0043] The sources of the n mirror tube units are all connected to the power supply voltage, and the gates of the n mirror tube units are all electrically connected to the output end of the operational amplifier A1. The drain of each mirror tube unit is respectively connected to the resistor R through a current source control switch. DAC Specifically, the drain of the mirror tube unit PM1 controls the switch through the current source With resistor R DAC The first end is electrically connected to the mirror tube unit PM2, and the drain of the mirror tube unit PM2 is controlled by the current source switch With resistor R DAC The first end of the mirror tube unit PMn is electrically connected to the first end of the mirror tube unit PMn, and .... With resistor R DAC The first end of the resistor R DAC The second end of is grounded. By periodically controlling each current source control switch, currents of different magnitudes can be conducted, thereby DAC Generates a step-type ramp voltage V with a clear voltage value dac .

[0044] Please continue reading Figure 2 The charge and discharge current control circuit 4 only works in the capacitor integral ramp generator working mode, and is used to output the charge and discharge current I in the capacitor integral ramp generator working mode. charge The charge and discharge current control circuit 4 may include a PMOS tube P1, an NMOS tube N0, an NMOS tube N1 and an NMOS tube N2, wherein the width-to-length ratio of the NMOS tube N2 is obtained by reducing or enlarging the width-to-length ratio of the NMOS tube N0 according to a predetermined ratio. The source of the PMOS tube P1 is connected to the power supply voltage, the gate of the PMOS tube P1 is electrically connected to the output end of the operational amplifier A1, the drain of the PMOS tube P1 is electrically connected to the drain of the NMOS tube N0, the gate of the NMOS tube N0, the drain of the NMOS tube N1 and the gate of the NMOS tube N2 respectively, the sources of the NMOS tube N0, the NMOS tube N1 and the NMOS tube N2 are all grounded, the gate of the NMOS tube N1 is connected to the mode control signal Vbn, and the drain of the NMOS tube N2 is used to output the charge and discharge current I charge .

[0045] With the above structure, the NMOS tube N1 is a switch tube. When the high-precision ramp generator works in the capacitor integration ramp generator working mode, the control signal Vbn turns off the NMOS tube N1, so that the charge and discharge current control circuit 4 works normally. GThe mirror current is used to control the current size through the current mirror structure composed of NMOS tube N0 and NMOS tube N2 to generate the charge and discharge current I charge Taking the width-to-length ratio of the NMOS tube N0 as the standard unit, the width-to-length ratio of the NMOS tube N2 is scaled by 1:x, so that the size of the charge-discharge current and the slope of the linear ramp can be controlled. When the high-precision ramp generator works in the DAC-type ramp generator working mode, the control signal Vbn turns on the NMOS tube N1, thereby stopping the charge-discharge current control circuit 4.

[0046] The mode switching circuit 5 has two working modes: a DAC type ramp generator working mode and a capacitor integration type ramp generator working mode. dac Output a periodically changing step-type ramp signal; and in the capacitor integral ramp generator working mode according to the charge and discharge current I charge Output a linearly changing ramp signal. The bias circuit 6 is used to generate a ramp starting voltage V ref Provided to the mode switching circuit 5.

[0047] In this embodiment, the mode switching circuit 5 includes a ramp signal output buffer circuit 51 and a switch capacitor circuit 52. The ramp signal output buffer circuit 51 is used to work as a buffer driver stage in the DAC type ramp generator working mode to drive the step-type ramp voltage V dac Forming a step-type ramp voltage; and working as an integral operation circuit in the capacitor integral ramp generator working mode, with the ramp starting voltage V ref is the reference voltage, through the charge and discharge current I charge A linear ramp voltage is formed.

[0048] The ramp signal output buffer circuit 51 may include an operational amplifier A2, a linear ramp capacitor C RAMP , Input control switch Input control switch Capacitor Control Switch and capacitor controlled switches The operational amplifier A2 is an input-output rail-to-rail operational amplifier. The in-phase input terminal of the operational amplifier A2 is controlled by an input switch. Connect the ramp starting voltage V output by the bias circuit 6 ref , the non-inverting input of the operational amplifier A2 is also controlled by the input switch Connect the step voltage V output by the weighted current DAC current source array 3 dac The inverting input terminal of the operational amplifier A2 is connected to the charge and discharge current I output by the charge and discharge current control circuit 4 charge, the inverting input of the operational amplifier A2 is switched via a capacitor and the linear ramp capacitor C RAMP The series circuit is electrically connected to its output terminal, and the inverting input terminal of the operational amplifier A2 is also controlled by a capacitor switch. Electrically connected to its output terminal.

[0049] The ramp signal output buffer circuit 51 has two working states. When the high-precision ramp generator works in the DAC type ramp generator working mode, the input control switch Open, input control switch Closed, at the same time, the capacitor controls the switch Open, capacitor controlled switch Close the circuit to work as a buffer driver to drive the V output by the previous DAC. dac A stepped ramp signal is formed.

[0050] When the high-precision ramp generator works in the capacitor integration ramp generator mode, the input control switch Close, input control switch Open, at the same time, the capacitor controls the switch Closed, capacitor controlled switch Open, so that the above circuit works as an integral operation circuit, through the capacitor C RAMP Cooperate with the connected charge and discharge current I charge A linear ramp voltage is formed.

[0051] The switched capacitor circuit 52 includes a ramp sampling capacitor C s , used to connect the step-type ramp signal to the ramp sampling capacitor C in the DAC type ramp generator working mode s The upper plate of the ramp starts at voltage V ref Connect the ramp sampling capacitor C s The lower plate of the capacitor is used to output a ramp signal; and in the capacitor integral ramp generator working mode, the linear ramp voltage is connected to the ramp sampling capacitor C s The lower plate uses the principle of capacitor charge conservation to output a linear ramp voltage as a ramp signal V ramp .

[0052] The switched capacitor circuit 52 may also include a capacitor control switch Capacitor Control Switch and capacitor controlled switches The ramp sampling capacitor C s The lower plate controls the switch through the capacitor is electrically connected to the output terminal of the operational amplifier A2, the ramp sampling capacitor C sThe lower plate also controls the switch through the capacitor Connect the ramp starting voltage V output by the bias circuit 6 ref The slope sampling capacitor C s The upper plate controls the switch through the capacitor is electrically connected to the output terminal of the operational amplifier A2, the ramp sampling capacitor C s The upper plate also serves as the output terminal of the high-precision ramp generator to output the ramp voltage V ramp .

[0053] When the high-precision ramp generator works in the DAC type ramp generator working mode, the capacitor controls the switch and capacitor controlled switches Closed, capacitor controlled switch Open, the ramp signal output buffer circuit 51 outputs the stepped ramp signal mounted on the ramp sampling capacitor C s When the high-precision ramp generator works in the capacitor integral ramp generator working mode, the capacitor controls the switch. and capacitor controlled switches Open, capacitor controlled switch Close, and connect the linear ramp voltage output by the ramp signal output buffer circuit 51 to the ramp sampling capacitor C s Lower plate.

[0054] The working principle of this embodiment is as follows:

[0055] In the coarse quantization stage, the high-precision ramp generator works in the DAC type ramp generator working mode to provide a coarse quantization ramp. Its equivalent ramp generator circuit is as follows: Figure 3 At this time, the control signal Vbn is at a high level, which turns on the NMOS tube N1, thereby turning off the charge and discharge current control circuit 4, and the capacitor charge and discharge ramp does not participate in the operation. At the same time, the input control switch Open, input control switch Closed, the output voltage V of the weighted current DAC current source array 3 dac The ramp signal output buffer circuit 51 is connected. The voltage V dac Switching controlled by current source Current source controlled switch ……、Current source control switch The n-channel mirror current source circuit controlled by the resistor R DAC The current source controls the switch. Current source controlled switch ……、Current source control switch The control signal is controlled by the timing control module, thereby controlling the mirror tube unit PM1 to the mirror tube unit PMN tube to mirror the size of I in sequence. c 、2I c 、4I c ,……,2 n-1 I c The current supplied to the resistor R DAC , can realize the rising or falling step-type ramp voltage. DAC The voltage generated on the input control switch needs to pass through the ramp signal output buffer circuit 51 to drive the subsequent circuits with different loads. Open, input control switch Closed, capacitor controlled switch Open, capacitor controlled switch Closed; the ramp signal output buffer circuit 51 is equivalent to a unity gain amplifier, which together constitutes a current steering DAC to work. Then the capacitor controls the switch and capacitor controlled switches Closed, capacitor controlled switch Open and mount the stepped slope output by the current steering DAC on the slope sampling capacitor C s The upper plate outputs a periodically changing step-type ramp signal to provide a rough ramp voltage for the two-step SS-ADC.

[0056] In the fine quantization stage, the high-precision ramp generator works in the capacitor integration ramp generator mode to provide a fine quantization ramp. Its equivalent ramp generator circuit is as follows: Figure 4 At this time, the control signal Vbn is at a low level, so that the NMOS tube N1 is turned off, and the current mirror structure composed of the NMOS tube N0 and the NMOS tube N2 works normally, and the charge and discharge current control circuit 4 generates a charge and discharge current I charge , provided to the inverting input of operational amplifier A2. At the same time, the input control switch Close, input control switch Turn on to stop the DAC type ramp generator and set V ref Connect to the non-inverting input of operational amplifier A2. Capacitor control switch Closed, capacitor controlled switch Open, at this time, the ramp signal output buffer circuit 51 is equivalent to an integral operation circuit. Then the capacitor controls the switch and capacitor controlled switches Open, capacitor controlled switch Close the linear ramp voltage output by the integral operation circuit to the ramp sampling capacitor C s The output voltage is V rampIt is used to provide a fine-scale linear ramp voltage for the two-step SS-ADC. According to the charge conservation principle, the output ramp voltage V ramp for:

[0057]

[0058] Wherein, t represents the time taken by the ramp generator when it works as a capacitive integral ramp generator, that is, the quantization time.

[0059] In this embodiment, the quantization process of the ramp generator is decomposed into two stages, coarse quantization and fine quantization, which greatly reduces the quantization time. In addition, a DAC-type ramp generator and a capacitor-integrated ramp generator can be combined with one output stage, which saves area and power consumption in chip design, improves the compatibility of the ramp generator, solves the linearity and stability problems introduced by the step-type ramp in high-speed and high-precision applications, and reduces the design complexity.

[0060] See also Figure 5 , Figure 5 1 is a structural block diagram of an embodiment of a two-step single slope analog-to-digital converter of the present invention. The two-step single slope analog-to-digital converter of this embodiment includes a ramp generator 100, a column comparator 300, a counter 400, a memory 500 and a digital logic control module 600. The ramp generator 100 adopts a high-precision ramp generator as in any of the above embodiments; the non-inverting input terminal of the column comparator 300 is electrically connected to the output terminal of the ramp generator, and the inverting input terminal of the column comparator 300 is used to connect the pixel signal V output by the pixel output terminal 200. sig The output end of the column comparator 300 is electrically connected to the counter 400, and the counter 400 is electrically connected to the memory 500. The memory 500 is used to output the analog-to-digital conversion result. The memory 500 is also electrically connected to the digital logic control module 600, and the digital logic control module 600 is used to generate a control signal, and the control signal is used to switch the working mode of the ramp generator. The working state of the counter 400 can be controlled by the output signal of the column comparator 300. The memory 500 is used to temporarily store the pixel quantization value. During the working process of the two-step SS-ADC, the memory 500 needs to store the C-bit coarse quantization value and the F-bit fine quantization value, and merge and output the quantization data D. The digital logic control module 600 generates a control signal to switch the working mode of the ramp generator according to the state of the memory 500, completes the switching of the two working states during coarse and fine quantization, and the reset operation after the quantization is completed.

[0061] The working principle of this embodiment is as follows:

[0062] See also Figure 5 and Figure 6When quantization starts, the counter 400 and the ramp generator 100 start working at the same time. The ramp generator 100 first works in the DAC type ramp generator working mode, providing a periodic ramp signal (i.e., a rough ramp voltage) with obvious voltage changes and connected to the non-inverting input terminal of the column comparator 300. The inverting input terminal of the column comparator 300 is connected to the pixel signal to be quantized V SIG The advantage of using a DAC-type ramp generator in the coarse quantization stage is that its ramp voltage has a clear voltage value in each clock cycle, which can be obtained by sampling the ramp capacitor C in the switched capacitor circuit 52. S The ramp voltage value at the end of the coarse quantization is mounted on the upper part, which is convenient for accessing the fine ramp for fine quantization and realizing a fine ramp traversing the entire quantization interval V range , reducing the complexity of the ramp generator design. When the ramp generator starts working, the coarse quantization ramp is in the voltage range V range The highest value of starts to decrease until it traverses the entire quantization interval. In this process, the pixel signal V SIG The voltage range, that is, its lower limit voltage V FL To its upper voltage limit V FH In the figure, the coarse quantization ramps down to V FL , the column comparator 300 flips from high level to low level, the counter 400 completes the counting of the coarse quantization stage and saves the count value to the memory 500, at which time the digital logic control module 600 is triggered to switch the working state of the ramp generator 100, and the voltage V FL is mounted on the ramp sampling capacitor C S Then, the counter 400 and the coercion generator start to work, and the ramp generator 100 switches to the capacitor integration ramp generator working mode, outputs a linear ramp for fine quantization, and starts fine quantization. Figure 4 It can be seen that the linear ramp connected to the non-inverting input of the column comparator 300 will be FL Start with a slope Increases linearly with time and rises to V FH When the column comparator 300 flips from a low level to a high level, the counter 400 completes the counting of the fine quantization stage and stores the count value in the memory 500. The quantization process of a pixel signal is completed by combining the count values ​​of the coarse and fine quantization.

[0063] In this embodiment, the ramp generator 100 combines the functions of the DAC-type ramp generator and the capacitor integration-type ramp generator to decompose the quantization process into two stages: coarse quantization and fine quantization. In the two-step quantization process, the ramp generator 100 outputs a step-type ramp signal in the coarse quantization stage and outputs a linear ramp signal in the fine quantization stage, which makes up for the incompatibility of using a linear ramp in the coarse quantization stage, introduces a linear ramp in the fine quantization stage, and solves the linearity and stability problems introduced by the step-type ramp in high-speed and high-precision applications. It also improves the conversion speed of the SS-ADC and the frame rate of the image sensor, improves the accuracy and stability of the ramp generator in the two-step SS-ADC application, and reduces the design complexity.

[0064] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A high-precision ramp generator, characterized in that: It has DAC type ramp generator working mode and capacitor integration type ramp generator working mode, including Bandgap reference source circuit, used to generate reference voltage V bg ; Voltage-current conversion circuit, used to convert the reference voltage V bg Converted into a stable current I c , and mirror current I c Provides a current source array for a weighted current DAC and a charge and discharge current control circuit; The weighted current DAC current source array is used to output a step voltage V in the DAC type ramp generator working mode. dac ; The charge and discharge current control circuit is used to output the charge and discharge current I in the capacitor integral ramp generator working mode. charge ; The mode switching circuit is used to switch the ramp voltage V according to the ladder ramp voltage V in the DAC type ramp generator working mode. dac Output a periodically changing step-type ramp signal; and in the capacitor integral ramp generator working mode according to the charge and discharge current I charge Output a linearly changing ramp signal; as well as Bias circuit for generating the ramp start voltage V ref Provided to the mode switching circuit.

2. The high-precision ramp generator according to claim 1, characterized in that: The voltage-current conversion circuit includes an operational amplifier A1, a resistor R BG and PMOS tube P0, the in-phase output terminal of the operational amplifier A1 is connected to the reference voltage V bg , the inverting input of the operational amplifier A1 is connected through the resistor R BG grounded; the inverting input terminal of the operational amplifier A1 is also electrically connected to the drain of the PMOS tube P0, the output terminal of the operational amplifier A1 is electrically connected to the gate of the PMOS tube P0, and the source of the PMOS tube P0 is connected to the supply voltage.

3. The high-precision ramp generator according to claim 2, characterized in that: The weighted current DAC current source array includes a resistor R DAC and n-stage mirror current source circuits, each of which includes a mirror tube unit and a current source control switch, the sources of the n mirror tube units are connected to the power supply voltage, the gates of the n mirror tube units are electrically connected to the output end of the operational amplifier A1, and the drain of each mirror tube unit is connected to the resistor R through a current source control switch. DAC The first end is electrically connected to the resistor R DAC The second end is grounded.

4. The high-precision ramp generator according to claim 3, characterized in that: The mirror tube units of each stage of the mirror current source circuit respectively include 2 i-1 There are reference PMOS tubes connected in parallel, where i represents the number of stages of the mirror current source circuit, 1≤i≤n.

5. The high-precision ramp generator according to claim 3, characterized in that: The charge and discharge current control circuit comprises a PMOS tube P1, an NMOS tube N0, an NMOS tube N1 and an NMOS tube N2, the source of the PMOS tube P1 is connected to a power supply voltage, the gate of the PMOS tube P1 is electrically connected to the output end of the operational amplifier A1, the drain of the PMOS tube P1 is electrically connected to the drain of the NMOS tube N0, the gate of the NMOS tube N0, the drain of the NMOS tube N1 and the gate of the NMOS tube N2 respectively, the sources of the NMOS tube N0, the NMOS tube N1 and the NMOS tube N2 are all grounded, the gate of the NMOS tube N1 is connected to a mode control signal Vbn, and the drain of the NMOS tube N2 is used to output a charge and discharge current I charge When the high-precision ramp generator works in the DAC type ramp generator working mode, the control signal Vbn turns on the NMOS tube N1; when the high-precision ramp generator works in the capacitor integration type ramp generator working mode, the control signal Vbn turns off the NMOS tube N1.

6. The high-precision ramp generator according to claim 5, characterized in that: The width-to-length ratio of the NMOS transistor N2 is obtained by reducing or enlarging the width-to-length ratio of the NMOS transistor N0 according to a predetermined ratio.

7. The high-precision ramp generator according to any one of claims 1 to 6, characterized in that: The mode switching circuit includes The ramp signal output buffer circuit is used to work as a buffer driver stage in the DAC type ramp generator working mode to drive the step-type ramp voltage V dac Forming a step-type ramp voltage; and working as an integral operation circuit in the capacitor integral ramp generator working mode, with the ramp starting voltage V ref is the reference voltage, through the charge and discharge current I charge Forming a linear ramp voltage; as well as The switched capacitor circuit includes the ramp sampling capacitor C s , used to connect the step-type ramp signal to the ramp sampling capacitor C in the DAC type ramp generator working mode s The upper plate of the ramp starts at voltage V ref Connect the ramp sampling capacitor C s The lower plate of the capacitor is used to output a ramp signal; and in the capacitor integral ramp generator working mode, the linear ramp voltage is connected to the ramp sampling capacitor C s The lower plate uses the principle of capacitor charge conservation to output a linear ramp voltage as a ramp signal V ramp .

8. The high-precision ramp generator according to claim 7, characterized in that: The ramp signal output buffer circuit includes an operational amplifier A2, a linear ramp capacitor C RAMP , Input control switch Input control switch Capacitor Control Switch and capacitor controlled switches The operational amplifier A2 is an input-output rail-to-rail operational amplifier. The in-phase input terminal of the operational amplifier A2 is controlled by an input switch. Connect the ramp starting voltage V of the bias circuit output ref , the non-inverting input of the operational amplifier A2 is also controlled by the input switch Connect the weighted current DAC current source array to the output of the step voltage V dac The inverting input terminal of the operational amplifier A2 is connected to the charge and discharge current I output by the charge and discharge current control circuit charge , the inverting input of the operational amplifier A2 is switched via a capacitor and the linear ramp capacitor C RAMP The series circuit is electrically connected to its output terminal, and the inverting input terminal of the operational amplifier A2 is also controlled by a capacitor switch. electrically connected to its output terminal; When the high-precision ramp generator works in the DAC type ramp generator working mode, the input control switch Open, input control switch Closed, capacitor controlled switch Open, capacitor controlled switch Closed; when the high-precision ramp generator works in the capacitor integration ramp generator working mode, the input control switch Close, input control switch Open, capacitor controlled switch Closed, capacitor controlled switch Open.

9. The high-precision ramp generator according to claim 8, characterized in that: The switched capacitor circuit further includes a capacitor control switch Capacitor Control Switch and capacitor controlled switches The ramp sampling capacitor C s The lower plate controls the switch through the capacitor is electrically connected to the output terminal of the operational amplifier A2, the ramp sampling capacitor C s The lower plate also controls the switch through the capacitor Connect the ramp starting voltage V of the bias circuit output ref ; The slope sampling capacitor C s The upper plate controls the switch through the capacitor is electrically connected to the output terminal of the operational amplifier A2, the ramp sampling capacitor C s The upper plate also serves as the output of a high-precision ramp generator to output a linear ramp voltage V ramp ; When the high-precision ramp generator works in the DAC type ramp generator working mode, the capacitor controls the switch and capacitor controlled switches Closed, capacitor controlled switch When the high-precision ramp generator works in the capacitor integral ramp generator mode, the capacitor controls the switch. and capacitor controlled switches Open, capacitor controlled switch closure.

10. A two-step single slope analog-to-digital converter, characterized in that: The invention comprises a ramp generator, a column comparator, a counter, a memory and a digital logic control module, wherein the ramp generator adopts the high-precision ramp generator as claimed in any one of claims 1 to 9; the non-inverting input terminal of the column comparator is electrically connected to the output terminal of the ramp generator, and the inverting input terminal of the column comparator is used to connect the pixel signal V output by the pixel output terminal. sig The output end of the column comparator is electrically connected to a counter, the counter is electrically connected to a memory, the memory is used to output the analog-to-digital conversion result, and the memory is also electrically connected to a digital logic control module, the digital logic control module is used to generate a control signal, and the control signal is used to switch the working mode of the ramp generator.

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