Novel sectional type R-2R structure digital-to-analog converter area distribution system

Abstract

The invention discloses a novel sectional type R-2R structure digital-to-analog converter area distribution system, relates to the technical field of electronics, and solves the technical problem that the chip area utilization efficiency is low due to the fact that the same area is distributed for each resistor unit and the difference of contribution of each resistor unit to the overall performance is not fully utilized in the prior art. The area of a resistor unit in a low N-bit R-2R structure is reduced, the area of a resistor unit in a high 11-N-bit R-2R structure and the area of a resistor unit in a high 5-bit thermometer decoding structure are increased, the area allocated to the resistor unit is dynamically adjusted, a larger area is allocated to a key resistor which has a larger influence on linearity, and the linearity of the key resistor is improved. And the area of the resistor with small contribution is properly reduced, so that the area averaging principle in the traditional design is broken, the optimal utilization of resources is realized in a more refined manner, and the linearity of the digital-to-analog converter and the applicability of the digital-to-analog converter in high-resolution and high-precision application are improved.

Description

Technical Field

[0001] The present application belongs to the field of electronic technology, and specifically relates to a novel segmented R-2R structure digital-to-analog converter area allocation system. Background Art

[0002] With the rapid development of digital technology, the demand for conversion between digital and analog signals in human life and production is increasing. As the core device for the interaction between digital and analog signals, the importance of digital-to-analog converters (DACs) is becoming increasingly prominent. Whether in communication systems, audio and video processing, or sensor interfaces and measurement equipment, the performance of digital-to-analog converters directly determines the signal processing capabilities of the system. Modern communication systems have increasing requirements for signal conversion, including higher conversion speeds, higher resolutions, higher accuracy, and lower power consumption, which poses severe challenges to the design of digital-to-analog converters.

[0003] At present, there are many types of structures for the implementation of digital-to-analog converters, including current-type digital-to-analog converters, capacitive digital-to-analog converters, and resistor-type digital-to-analog converters. Among them, the resistor-type digital-to-analog converter has been widely used in many applications due to its simple structure, easy integration, good linearity and high resolution. However, the resistor-type digital-to-analog converter has certain limitations in conversion speed, making it difficult to meet the needs of high-frequency signal processing. Therefore, in order to take into account the requirements of high-speed conversion and high resolution, other structures are usually used, such as thermometer code digital-to-analog converters. This type of digital-to-analog converter can achieve high-speed conversion through parallel structural design, but its linearity and resolution are limited by the complexity of the circuit and the matching performance of the resistor network.

[0004] In a resistor-based digital-to-analog converter, the linearity of the circuit depends mainly on the matching performance of the resistor network. The matching error between resistors will introduce nonlinear distortion, which in turn affects the accuracy and quality of the output signal. In order to improve the matching performance, a common method is to increase the physical area of ​​the resistors in the resistor network, because a larger area can reduce the random errors caused by process deviations. However, this method has a significant cost: Generally speaking, for every 1-bit increase in the linearity of the digital-to-analog converter, the area of ​​the resistor network needs to be increased by about four times. For highly integrated system designs in integrated circuits, the chip area is strictly limited, and the expansion of the resistor area will directly conflict with the layout of other functional modules, severely limiting the performance optimization space of the digital-to-analog converter.

[0005] In addition to improving matching accuracy by increasing the resistor area, calibration circuits can also be used to reduce errors caused by resistor mismatch. Calibration circuits usually include measurement and feedback modules to monitor and compensate for errors in the resistor network in real time. However, the implementation cost of such calibration circuits is extremely high. On the one hand, they require complex circuit design and precise measurement mechanisms; on the other hand, these circuits occupy a large amount of chip area and may introduce additional power consumption, so their practical application is greatly restricted in area-constrained application scenarios.

[0006] In order to ensure matching performance, traditional R-2R DACs usually allocate a consistent area to all resistor units. Although this uniform design is simple, it does not fully utilize the difference in the contribution of each resistor unit to the overall performance, resulting in low chip area utilization efficiency, especially in the design of high-resolution DACs. The area overhead increases significantly. Therefore, further improvements are still needed for R-2R DACs. Summary of the invention

[0007] The present application aims to solve at least one of the technical problems existing in the prior art; to this end, the present application proposes a novel segmented R-2R structure digital-to-analog converter area allocation system, which is used to solve the technical problem that the prior art allocates the same area to each resistor unit, fails to fully utilize the difference in the contribution of each resistor unit to the overall performance, and results in low chip area utilization efficiency.

[0008] To achieve the above-mentioned object, the first aspect of the present application provides a novel segmented R-2R structure digital-to-analog converter area allocation system, comprising: an R-2R structure unit and a thermometer decoding structure unit, wherein the R-2R structure unit and the thermometer decoding structure unit constitute a digital-to-analog converter;

[0009] The R-2R structural unit has only two resistance values, R and 2R. Compared with the multiple resistance values ​​of the traditional weighted resistor digital-to-analog converter, the R-2R structural unit has fewer resistance values. Each R-2R structure is composed of two R resistors connected in series.

[0010] The thermometer decoding structure unit is used to convert the binary input code into an analog output signal after being decoded by the decoder and input into the thermometer structure.

[0011] Further, the internal circuit connection of the digital-to-analog converter includes: Si switch, switch Tj, VSS, VREF; wherein i and j are integers, and i∈[0,10], j∈[0,30];

[0012] The S0 switch is connected to the low-level VSS in a closed state. The S0 switch has the same size as the S1 switch. Starting from the S2 switch, each bit switch control signal is connected to VREF after receiving a high level, and is connected to VSS after receiving a low level. The size of the Si switch is twice the size of the Si-1 switch. The switch size of the switch Tj in the thermometer code array is the same as that of the S10 switch. The output end of the overall digital-to-analog converter array is output through a buffer.

[0013] Furthermore, the R-2R structural unit includes an 11-bit R-2R structure, wherein the resistance unit area in the lower N-bit R-2R structure is reduced, and the resistance unit area in the upper 11-N-bit R-2R structure is increased; wherein N is an integer, N∈(0,12).

[0014] The present application can further reduce the layout area of ​​the digital-to-analog converter while ensuring the overall performance by reducing the area of ​​the resistor unit in the R-2R structure of the lower N bits; the low bits have less impact on the overall output, so the area of ​​its resistor unit can be relatively small; increasing the area of ​​the resistor unit in the R-2R structure of the upper 11-N bits helps to improve the matching accuracy of the high bits, because the high bits have a greater impact on the overall accuracy of the digital-to-analog converter.

[0015] Furthermore, the R-2R structural unit includes an 11-bit R-2R structure, wherein the resistance unit area in the lower 9-bit R-2R structure is reduced, and the resistance unit area in the upper 2-bit R-2R structure is increased.

[0016] Furthermore, the thermometer decoding structure unit includes a high-5-bit thermometer decoding structure, wherein the area of ​​the resistance unit in the high-5-bit thermometer decoding structure is increased.

[0017] The present application can improve the linearity performance of the digital-to-analog converter by increasing the area of ​​the resistor unit in the upper 5-bit thermometer decoding structure, thereby further improving the linearity of the digital-to-analog converter.

[0018] Furthermore, the reducing the area of ​​the resistor unit in the lower N-bit R-2R structure includes:

[0019] Get the original resistance unit area YDS; where YDS=4×4r=16r;

[0020] The area of ​​the resistor unit is reduced to (4-M)×(4-M)r, where M is an integer, M∈(0,4); when the area of ​​the resistor unit is reduced by (4-M)×(4-M)r, the resistance value of the resistor unit remains fixed.

[0021] Furthermore, the area of ​​the resistor unit is reduced to 2×2r.

[0022] Further, the area of ​​the resistor unit in the upper 11-N bits R-2R structure and the upper 5 bits thermometer decoding structure is increased, including:

[0023] The area of ​​the resistance unit is increased to (4+P)×(4+P)r; wherein P is an integer and P>0; when the area of ​​the resistance unit is increased to (4+P)×(4+P)r, the resistance value of the resistance unit remains fixed.

[0024] Through the above steps, the present application dynamically adjusts the area allocated to the resistor unit, allocates a larger area to the key resistors that have a greater impact on linearity, and appropriately reduces the area of ​​the resistors that contribute less, breaking the area averaging principle in traditional design and achieving optimal resource utilization in a more refined manner. At the same time, without significantly increasing the area overhead, the linearity of the digital-to-analog converter is maximized, the impact of resistor matching errors on high-weight resistors is effectively reduced, the distortion caused by integral nonlinearity and differential nonlinearity is significantly reduced, and the applicability of the digital-to-analog converter in high-resolution and high-precision applications is improved.

[0025] The second aspect of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements a new segmented R-2R structure digital-to-analog converter area allocation system according to the first aspect of the present invention.

[0026] Another aspect of the present invention provides a computer program, which, when executed by a processor, implements a novel segmented R-2R structure digital-to-analog converter area allocation system according to the first aspect of the present invention.

[0027] Compared with the prior art, the beneficial effects of this application are:

[0028] 1. This application dynamically adjusts the area allocated to the resistor unit, allocates a larger area to the key resistors that have a greater impact on linearity, and appropriately reduces the area of ​​the resistors that contribute less, breaking the area equalization principle in traditional design and achieving optimal resource utilization in a more refined way.

[0029] 2. This application allocates limited chip area to key positions that can most significantly improve performance, thereby maximizing the linearity of the digital-to-analog converter without significantly increasing area overhead, effectively reducing the impact of resistance matching errors on high-weight resistors, significantly reducing distortion caused by integral nonlinearity and differential nonlinearity, and improving the applicability of the digital-to-analog converter in high-resolution and high-precision applications.

[0030] 3. This application not only improves the performance of the converter through a dynamic area allocation strategy, but also optimizes the area utilization efficiency of the chip. This method improves the integral nonlinearity and differential nonlinearity of the segmented R-2R digital-to-analog converter while maintaining the area unchanged, showing good practical application prospects. It provides a new idea for the design of high-precision, high-resolution digital-to-analog converters, and also provides an effective solution to the contradiction between matching accuracy and area resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 This is a schematic diagram of the structure of the novel segmented R-2R structure digital-to-analog converter of the present application;

[0033] Figure 2 A schematic diagram of the structure of a conventional R-2R structure digital-to-analog converter of the present application;

[0034] Figure 3 A schematic diagram of the resistor structure in the traditional R-2R structure of this application;

[0035] Figure 4 This is a schematic diagram of the low-level resistance structure of the novel segmented R-2R structure of the present application;

[0036] Figure 5 This is a schematic diagram of the high-level resistor structure of the novel segmented R-2R structure of the present application;

[0037] Figure 6 A schematic diagram of differential nonlinearity simulation results of a conventional R-2R structure digital-to-analog converter of the present application;

[0038] Figure 7 A schematic diagram of the integral nonlinearity simulation results of the conventional R-2R structure digital-to-analog converter of the present application;

[0039] Figure 8 A schematic diagram of differential nonlinearity simulation results of the novel segmented R-2R structure digital-to-analog converter of the present application;

[0040] Fig. 9 Schematic diagram of integral nonlinearity simulation results of the novel segmented R-2R structure digital-to-analog converter of the present application. DETAILED DESCRIPTION

[0041] The technical solution of the present application will be described clearly and completely in conjunction with the embodiments below. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

[0042] The first aspect of the present application provides a novel segmented R-2R structure digital-to-analog converter area allocation system, including: an R-2R structure unit and a thermometer decoding structure unit, wherein the R-2R structure unit and the thermometer decoding structure unit constitute a digital-to-analog converter;

[0043] R-2R structural unit: There are only two resistance values, R and 2R. Compared with the multiple resistance values ​​of the traditional weighted resistor digital-to-analog converter, the R-2R structural unit has fewer resistance values. Each R-2R structure is composed of two R resistors connected in series; the traditional weighted resistor digital-to-analog converter may include multiple resistance values ​​such as R, 2R, 4R, 8R, etc.

[0044] Thermometer decoding structure unit: used to convert the binary input code into an analog output signal after being decoded by the decoder and then input into the thermometer structure

[0045] See also Figure 1 , the R-2R structural unit in this embodiment includes an 11-bit R-2R structure, wherein the resistance unit area in the lower N-bit R-2R structure is reduced, and the resistance unit area in the upper 11-N-bit R-2R structure is increased; wherein N is an integer, N∈(0,12), and the specific value is set according to experience. In another preferred embodiment, N is set to 9 because the resistance unit area saved in the lower R-2R structure needs to be used as much as possible by the higher R-2R structure and the thermometer decoding structure;

[0046] The internal circuit connections of the digital-to-analog converter include: Si switch, switch Tj, VSS, VREF; wherein, i and j are integers, and i∈[0, 10], j∈[0, 30]; the S0 switch is always closed and connected to the low-level VSS. The S0 switch has the same size as the S1 switch. Starting from the S2 switch, each bit switch control signal is connected to VREF after receiving a high level, and is connected to VSS after receiving a low level. The size of the Si switch is twice the size of the Si-1 switch. The switch size of the switch Tj in the thermometer code array is the same as that of the S10 switch. The output of the overall digital-to-analog converter array is output through a buffer.

[0047] This embodiment cleverly adopts an area optimization strategy. Specifically, the area of ​​the resistor unit in the low N-bit R-2R structure is reduced. This measure successfully achieves a further reduction in the layout area under the key premise of ensuring that the overall performance of the digital-to-analog converter is not affected, thereby improving the layout efficiency of the integrated circuit and the benefits of manufacturing costs; considering that in the R-2R structure, the low-bit weight is relatively light and the contribution to the overall output is relatively small, therefore, moderately reducing the area of ​​these low-bit resistor units and providing more area for high-bit resistor units can help improve the overall performance; at the same time, for the high 11-N-bit R-2R structure, the present application adopts the opposite strategy, that is, increasing the area of ​​its resistor unit, because the high bit carries a greater weight in the digital-to-analog conversion process and has a more significant decisive role in the overall accuracy; by increasing the area of ​​the high-bit resistor unit, we can effectively improve the matching accuracy between high-bit resistors, thereby improving the conversion accuracy and stability of the entire digital-to-analog converter.

[0048] The thermometer decoding structure unit in this embodiment includes a high-5-bit thermometer decoding structure, wherein the area of ​​the resistor unit in the high-5-bit thermometer decoding structure is increased.

[0049] This embodiment significantly improves the linear performance of the structure by increasing the area of ​​the resistor unit in the upper 5-bit thermometer decoding structure. This is because the high-bit resistor unit plays a vital role in the linearity performance of the digital-to-analog converter. Since the high-bit weight is large, it has a direct and significant impact on the accuracy of the overall output signal. Therefore, optimizing the area of ​​the resistor unit in the upper 5-bit thermometer decoding structure can more effectively control the matching error between resistors and reduce nonlinear distortion.

[0050] In this embodiment, the area of ​​the resistor unit in the R-2R structure of the lower N bits is reduced, including:

[0051] Get the original resistor unit area YDS; where YDS = 4 × 4r = 16r; see Figure 2-Figure 3 ,The standard resistance unit area of ​​each bit of the traditional R-2R structure is 16r;

[0052] Reduce the area of ​​the resistor unit to (4-M)×(4-M)r; where M is an integer, M∈(0,4), and the specific value is set based on experience; when the area of ​​the resistor unit is reduced by (4-M)×(4-M)r, the resistance value of the resistor unit remains unchanged, see Figure 4In another preferred embodiment, M is set to 2; in other embodiments, M can be set to 1 when the area is reduced. The solution adopted is to reduce 7r to become a 3*3 structure, or set M to 3 and reduce 15r to become a 1*1 structure. The resistance values ​​of the resistance units obtained are the same because the series or parallel connection will not change the resistance value, but only the area size.

[0053] In this embodiment, the area of ​​the resistor unit in the upper 11-N bits R-2R structure and the upper 5 bits thermometer decoding structure is increased, including:

[0054] Increase the area of ​​the resistor unit to (4+P)×(4+P)r; where P is an integer, P>0, and the specific value is set based on experience. Figure 5 In this embodiment, P is set to 1 to form a structure with a resistance unit area of ​​5×5r; when the resistance unit area is increased to (4+P)×(4+P)r, the resistance value of the resistance unit remains fixed.

[0055] Through the above steps, this embodiment realizes the dynamic optimization configuration of the resistance unit area; specifically, a larger area is allocated to those key resistors that have a more significant impact on linearity; and the area of ​​resistors with relatively small impact is appropriately reduced; the conventional practice of uniform area distribution in traditional design is abandoned, and a more sophisticated and efficient resource utilization method is adopted; without significantly increasing the area cost, this solution successfully maximizes the linearity performance of the digital-to-analog converter; in addition, it effectively weakens the adverse effects of resistance matching errors on high-weight resistors, and greatly reduces the distortion problems caused by integral nonlinearity and differential nonlinearity, thereby significantly enhancing the applicability and performance of the digital-to-analog converter in high-resolution and high-precision application scenarios.

[0056] In this embodiment, the R-2R segmented digital-to-analog converter of the traditional area allocation scheme uses an R-2R structure for the lower 11 bits and a thermometer code structure for the upper 5 bits. A total of 65 resistor units R are used, and the area of ​​a single resistor unit is 16r. Therefore, the resistor unit area in the traditional scheme is 65×16=1040r; in the improved scheme, the area of ​​28 resistors in the lower 9 bits is changed to 4r, and the area of ​​37 resistors in the upper 7 bits is changed to 25r, so the resistor unit area in the improved scheme is 28×4+37×25=1037r; the overall resistor unit area is changed from 1040r to 1037r, which is reduced by 3r; in order to facilitate the design of the layout, it is hoped not to introduce too many types of resistor units, so it is decided to use two types of resistor unit areas, namely 2×2r and 5×5r.

[0057] The two area allocation schemes for DACs are compared using 200 Monte Carlo simulations. Figure 6-Figure 7, we can see that the integral nonlinearity and differential nonlinearity of the R-2R segmented DAC of the traditional area allocation scheme are -4.052LSB to 2.787LSB and -791.7uLSB to 720.2uLSB respectively, where LSB represents the least significant bit; see Figure 8-Figure 9 It can be seen that the integral nonlinearity and differential nonlinearity of the R-2R segmented digital-to-analog converter using the area allocation scheme of the present application are -3.096LSB to 1.776LSB and -715.3uLSB to 550.8uLSB respectively; by comparison, it can be obtained that the integral nonlinearity and differential nonlinearity performance of the area allocation scheme proposed in the present application are improved, indicating that the overall matching performance of the circuit is improved while the area is optimized.

[0058] The second aspect embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, a new segmented R-2R structure digital-to-analog converter area allocation system is implemented according to the first aspect embodiment of the present application.

[0059] Another aspect of the present application provides a computer program, which, when executed by a processor, implements a novel segmented R-2R structure digital-to-analog converter area allocation system according to the first aspect of the present application.

[0060] Part of the data in the above formula is calculated by removing the dimension and taking its numerical value. The formula is a formula closest to the actual situation obtained by software simulation of a large amount of collected data; the preset parameters and preset thresholds in the formula are set by technical personnel in this field according to actual conditions or obtained through simulation of a large amount of data.

[0061] The above embodiments are only used to illustrate the technical method of the present application and are not intended to limit it. Although the present application has been described in detail with reference to the preferred embodiments, a person of ordinary skill in the art should understand that the technical method of the present application may be modified or replaced by equivalents without departing from the spirit and scope of the technical method of the present application.

Claims

1. A novel segmented R-2R structure digital-to-analog converter area allocation system, characterized in that: include: An R-2R structural unit and a thermometer decoding structural unit, wherein the R-2R structural unit and the thermometer decoding structural unit constitute a digital-to-analog converter; The R-2R structural unit has only two resistance values, R and 2R, and each R-2R structure is composed of two R resistors in series; The thermometer decoding structure unit is used to convert the binary input code into an analog output signal after being decoded by the decoder and input into the thermometer structure.

2. A novel segmented R-2R structure digital-to-analog converter area allocation system according to claim 1, characterized in that: The R-2R structural unit includes an 11-bit R-2R structure, wherein the resistance unit area in the lower N-bit R-2R structure is reduced, and the resistance unit area in the upper 11-N-bit R-2R structure is increased; wherein N is an integer, N∈(0,12).

3. A novel segmented R-2R structure digital-to-analog converter area allocation system according to claim 1, characterized in that: The thermometer decoding structure unit includes a high-5-bit thermometer decoding structure, wherein the area of ​​the resistance unit in the high-5-bit thermometer decoding structure is increased.

4. A novel segmented R-2R structure digital-to-analog converter area allocation system according to claim 3, characterized in that: The step of reducing the resistance unit area in the R-2R structure of the lower N bits includes: Get the original resistance unit area YDS; where YDS=4×4r=16r; The area of ​​the resistor unit is reduced to (4-M)×(4-M)r; wherein M is an integer, M∈(0,4); when the area of ​​the resistor unit is reduced by (4-M)×(4-M)r, the resistance value of the resistor unit remains fixed.

5. A novel segmented R-2R structure digital-to-analog converter area allocation system according to claim 4, characterized in that: Increasing the resistance unit area in the upper 11-N bits R-2R structure and the upper 5 bits thermometer decoding structure, including: Obtain the original resistance unit area YDS; wherein YDS=4×4r=16r; increase the resistance unit area to (4+P)×(4+P)r; wherein P is an integer, P>0; when the resistance unit area is increased to (4+P)×(4+P)r, the resistance value of the resistance unit remains fixed.

6. A novel segmented R-2R structure digital-to-analog converter area allocation system according to claim 2, characterized in that: The R-2R structural unit includes an 11-bit R-2R structure, wherein the resistance unit area in the lower 9-bit R-2R structure is reduced, and the resistance unit area in the upper 2-bit R-2R structure is increased.

7. The novel segmented R-2R structure digital-to-analog converter area allocation system according to claim 1, characterized in that: The internal circuit connection of the digital-to-analog converter includes: Si switch, switch Tj, VSS, VREF; wherein i and j are integers, and i∈[0,10], j∈[0,30]; The S0 switch is connected to the low-level VSS in a closed state. The S0 switch has the same size as the S1 switch. Starting from the S2 switch, each bit switch control signal is connected to VREF after receiving a high level, and is connected to VSS after receiving a low level. The size of the Si switch is twice the size of the Si-1 switch. The switch size of the switch Tj in the thermometer code array is the same as that of the S10 switch. The output end of the overall digital-to-analog converter array is output through a buffer.

8. The novel segmented R-2R structure digital-to-analog converter area allocation system according to claim 3, characterized in that: The resistor unit area is reduced to 2×2r.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the computer program implements a new segmented R-2R structure digital-to-analog converter area allocation system according to any one of claims 1 to 8.

10. A computer program, characterized in that When the computer program is executed by a processor, a novel segmented R-2R structure digital-to-analog converter area allocation system according to any one of claims 1 to 8 is implemented.

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