Continuous time reconfigurable sigma-delta modulator

Abstract

The invention discloses a sigma-delta modulator with reconfigurable continuous time. The sigma-delta modulator comprises two first-order active integrators, a reconfigurable integrator, a multi-bit quantizer, a half-cycle delay circuit and a DAC (Digital-to-Analog Converter) feedback circuit, the first-stage first-order active integrator is connected with the second-stage reconfigurable integrator, an integration result is sent to the third-stage first-order active integrator, the result is sent to the multi-bit quantizer, a final output result is obtained from a quantization result through the encoder, and meanwhile the quantization result is fed back to the integrating circuit through the DAC feedback circuit and the half-cycle demonstration circuit. Negative feedback is realized; according to the reconfigurable integrator, a capacitor parallel connection structure is adopted in a passive mode, the gain of a passive integrating circuit is improved, the performance of the modulator working in the passive mode is further improved, and high precision and lower power consumption are achieved. The continuous time reconfigurable sigma-delta modulator provided by the invention can be applied to the audio field.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuit design, and in particular to a continuous-time reconfigurable sigma-delta modulator. Background Art

[0002] Almost all signals in nature are analog, such as sound, images, pressure, temperature, etc., while signals used for transmission, storage, calculation and display are mostly digital signals. Therefore, ADC is needed to convert the processed analog signals into corresponding digital signals and then send them to digital chips for processing, and then output them through DAC to obtain the information we want. According to the relationship between different sampling frequencies and signal bandwidth, analog-to-digital converters can be divided into two types: Nyquist ADC and oversampling ADC. The traditional Nyquist ADC has a large bandwidth and fast conversion speed, but low accuracy, and cannot meet the current development needs of high-fidelity digital audio and video, medical and health electronics and other equipment towards ultra-high speed, ultra-high precision and low power consumption. The oversampling ADC can have a sampling frequency much higher than twice the signal bandwidth, thereby improving the resolution of the analog-to-digital converter, represented by the Sigma-Delta ADC. The Sigma-Delta ADC increases the sampling frequency, for example, by using 128 times oversampling, so that the noise distribution in the sampling band is flatter to reduce the noise in the band, and then through noise shaping technology, a loop filter is used to shape the noise in the signal band to outside the signal band, and the high-frequency noise is filtered out by a digital filter to improve the signal-to-noise ratio of the circuit, which can meet the requirements of high precision and is easy to achieve low voltage and low power consumption.

[0003] However, in the actual quantization process, due to process and other reasons, there will be some non-ideal factors, such as clock jitter, additional loop delay, DAC nonlinearity, etc., which will reduce the effective number of bits of the modulator and deteriorate the performance such as signal-to-noise ratio and power consumption. At present, continuous-time Sigma-Delta modulators are mainly divided into high-precision and high-speed types. High-precision Sigma-Delta modulators mostly use active integrators as loop filters, which can achieve excellent effective number of bits, but sacrifice power consumption. Passive integrators have low power consumption but poor noise shaping capabilities, which introduces the problem of compromise between power consumption and accuracy. Moreover, most of the current Sigma-Delta modulators use a single working mode and cannot meet multi-mode requirements. Summary of the invention

[0004] The object of the present invention is to provide a continuous-time reconfigurable sigma-delta modulator to address the above-mentioned deficiencies in the prior art, so as to solve the technical problem of the single working mode of the existing continuous-time sigma-delta ADC modulator, thereby realizing a sigma-delta modulator that can switch modes between high precision and low power consumption.

[0005] In view of the prior art and the above-mentioned deficiencies, the present invention is achieved through the following design scheme:

[0006] A continuous-time reconfigurable sigma-delta modulator, characterized in that it comprises the following circuits: a first-stage fully differential active integrator, a second-stage reconfigurable integrator, a third-stage fully differential active integrator, a multi-bit quantizer, an encoder, a feedback DAC1, a feedback DAC2, a half-cycle delay circuit, and a delay unit; wherein the resistor Rf2, the resistor R21, the capacitor C2, the switch SW1, the switch SW2, and the switch SW3 in the second-stage reconfigurable integrator are used for both the active mode and the passive mode of the circuit;

[0007] The two differential signal input ports VINP and VINN of the first-stage fully differential active integrator are signal input terminals of the continuous-time reconfigurable sigma-delta modulator; the output terminal of the first-stage fully differential active integrator is connected to the input terminal of the second-stage reconfigurable integrator; the output terminal of the second-stage reconfigurable integrator is connected to the input terminal of the third-stage fully differential active integrator; the output terminal of the third-stage fully differential active integrator is connected to the input terminal of the multi-bit quantizer; the output terminal of the multi-bit quantizer is connected to the input terminal of the encoder; the output terminal of the multi-bit quantizer is connected to the delay The input end of the unit is connected; the output end of the delay unit is connected to the input end of the half-cycle delay circuit; the output end of the delay unit is connected to the input end of the feedback DAC2; the output end of the delay unit is connected to the input end of the feedback DAC1; the output end of the feedback DAC1 is connected to the input end of the first-stage fully differential active integrator; the output end of the feedback DAC2 is connected to the input end of the third-stage fully differential active integrator; the output end of the half-cycle delay circuit is connected to the input end of the third-stage fully differential active integrator; the input end OUT of the encoder outputs the final quantization result;

[0008] Furthermore, the first-stage fully differential active integrator adopts a fully differential structure, including a first-stage feedforward resistor Rf1, a first-stage integrating resistor R1, a first-stage integrating capacitor C1, and an operational amplifier op1; the first-stage fully differential active integrator is used to perform first-order integration on a differential input signal; wherein the first-stage feedforward resistor Rf1 includes a resistor Rf11 and a resistor Rf12, the first-stage integrating resistor R1 includes a resistor R11 and a resistor R12, and the first-stage integrating capacitor C1 includes a capacitor C11 and a capacitor C12; the signal input terminals VINN and VINP of the continuous-time reconfigurable sigma-delta modulator are simultaneously the input terminals of the first-stage integrating resistors R11 and R12 and the input terminals of the first-stage feedforward resistors Rf11 and Rf12; the output terminal of the first-stage integrating resistor R11 is simultaneously the input terminal of the first-stage integrating capacitor C11 and the input terminal vi1- of the operational amplifier op1; The output end of the first-stage integrating resistor R11 is also the output end of the feedback DAC1; the output end of the first-stage integrating resistor R12 is also the input end of the first-stage integrating capacitor C12 and the input end vi1+ of the operational amplifier op1; the output end of the first-stage integrating resistor R12 is also the output end of the feedback DAC1; the output end of the first-stage integrating capacitor C11 is also the output end vo1+ of the operational amplifier op1 and the input end of the second-stage reconfigurable integrator; the output end of the first-stage integrating capacitor C12 is also the output end vo1- of the operational amplifier op1 and the input end of the second-stage reconfigurable integrator; the output end of the first-stage feed-forward resistor Rf11 is connected to the output end of the third-stage feed-forward resistor Rf31 in the second-stage reconfigurable integrator; the output end of the first-stage feed-forward resistor Rf12 is connected to the output end of the third-stage feed-forward resistor Rf32 in the second-stage reconfigurable integrator;

[0009] Furthermore, the second-stage reconfigurable integrator adopts a fully differential structure, including a second-stage feedforward resistor Rf2, a third-stage feedforward resistor Rf3, a second-stage integral resistor R2, a second-stage integral capacitor C2, a first-stage switch SW1, a second-stage switch SW2, a third-stage switch SW3, an operational amplifier op2, a connection point A, and a connection point B; the second-stage reconfigurable integrator is used to perform a first-order integration on the input signal; wherein the second-stage feedforward resistor Rf2 includes a resistor Rf21 and a resistor Rf22, the third-stage feedforward resistor Rf3 includes a resistor Rf31 and a resistor Rf32, the second-stage integral resistor R2 includes a resistor R21, a resistor R22, a resistor R23, and a resistor R24, and the second-stage integral The capacitor C2 includes a capacitor C21 and a capacitor C22, the first-stage switch SW1 includes a switch SW11 and a switch SW12, the second-stage switch SW2 includes a switch SW21 and a switch SW22, and the third-stage switch SW3 includes a switch SW31 and a switch SW32; the input end of the second-stage integrating resistor R21 is simultaneously the input end of the second-stage feedforward resistor Rf21 and the output end vo1- of the operational amplifier op1 in the first-stage fully differential active integrator; the input end of the second-stage integrating resistor R22 is simultaneously the output end of the second-stage integrating resistor R21 and the input end of the second-stage switch SW21; the input end of the second-stage integrating resistor R23 is simultaneously the input end of the second-stage feedforward resistor Rf21 The input end of the second-stage feed-forward resistor Rf22 is connected to the output end vo1+ of the operational amplifier op1 in the first-stage fully differential active integrator; the input end of the second-stage integrating resistor R24 ​​is also the output end of the second-stage integrating resistor R23 and the input end of the second-stage switch SW22; the input end of the second-stage integrating capacitor C21 is also the output end of the second-stage integrating resistor R22 and the input end vi2- of the operational amplifier op2; the input end of the second-stage integrating capacitor C22 is also the output end of the second-stage integrating resistor R24 ​​and the input end vi2+ of the operational amplifier op2; the input end of the first-stage switch SW11 is connected to the output end of the second-stage feed-forward resistor Rf21 ; The input end of the first-stage switch SW12 is connected to the output end of the second-stage feed-forward resistor Rf22; the input end of the third-stage feed-forward resistor Rf31 is connected to the output end ① of the first-stage switch SW11; the input end of the third-stage feed-forward resistor Rf32 is connected to the output end ① of the first-stage switch SW12; the output end ② of the first-stage switch SW11 is simultaneously the output end of the third-stage feed-forward resistor Rf31 and the input end of the third-stage integrating capacitor C31 in the third-stage fully differential active integrator; the output end ② of the first-stage switch SW12 is simultaneously the output end of the third-stage feed-forward resistor Rf32 and the input end of the third-stage integrating capacitor C32 in the third-stage fully differential active integrator;The output end of the second-stage switch SW21 is simultaneously the output end ① of the third-stage switch SW32 and the input end of the third-stage integrating resistor R31 in the third-stage fully differential active integrator; the output end of the second-stage switch SW22 is simultaneously the output end ① of the third-stage switch SW32 and the input end of the third-stage integrating resistor R32 in the third-stage fully differential active integrator; the input end of the third-stage switch SW31 is simultaneously the output end of the second-stage integrating capacitor C21 and the output end vo2+ of the operational amplifier op2; the input end of the third-stage switch SW32 is simultaneously the output end of the second-stage integrating capacitor C22 and the output end vo2- of the operational amplifier op2; the connection point A is simultaneously the output end ② of the third-stage switch SW31 and the output end of the first-stage feedback resistor Rb2 in the third-stage fully differential active integrator; the connection point B is simultaneously the output end ② of the third-stage switch SW32 and the output end of the first-stage feedback resistor Rb1 in the third-stage fully differential active integrator;

[0010] Further, the third-stage fully differential active integrator adopts a fully differential structure, including a third-stage integrating resistor R3, a third-stage integrating capacitor C3, a first-stage feedback resistor Rb and an operational amplifier op3; the third-stage fully differential active integrator is used to perform a first-order integration on an input signal; wherein the third-stage integrating resistor R3 includes a resistor R31 and a resistor R32, the third-stage integrating capacitor C3 includes an integrating capacitor C31 and an integrating capacitor C32, and the first-stage feedback resistor Rb includes a resistor Rb1 and a resistor Rb2; the input end of the third-stage integrating resistor R31 is simultaneously the output end ① of the third-stage switch SW32 and the output end of the second-stage switch SW21; the input end of the third-stage integrating resistor R32 is simultaneously the output end ① of the third-stage switch SW31 and the output end of the second-stage switch SW22; the input end of the third-stage integrating capacitor C31 is simultaneously the output end of the third-stage integrating resistor R31 and the input end vi3- of the operational amplifier op3 ; The input end of the third-stage integrating capacitor C31 is simultaneously the output end ② of the first-stage switch SW11 and the output end of the feedback DAC2; the input end of the third-stage integrating capacitor C32 is simultaneously the output end of the third-stage integrating resistor R32 and the input end vi3+ of the operational amplifier op3; the input end of the third-stage integrating capacitor C32 is simultaneously the output end ② of the first-stage switch SW12 and the output end of the feedback DAC2; the input end of the first-stage feedback resistor Rb1 is simultaneously the output end of the third-stage integrating capacitor C31 and the input end vo3+ of the operational amplifier op3; the input end of the first-stage feedback resistor Rb2 is simultaneously the output end of the third-stage integrating capacitor C32 and the input end vo3- of the operational amplifier op3; the input end vo3+ of the operational amplifier op3 and the input end vo3- of the operational amplifier op3 are simultaneously the output end of the third-stage fully differential active integrator and the input end of the multi-bit quantizer;

[0011] Furthermore, the half-cycle delay circuit includes a delay unit delay1 and a compensation DACkb; the input end of the multi-bit quantizer is connected to the output end of the third-stage fully differential active integrator; the output end of the multi-bit quantizer is also the input end of the delay unit and the input end of the encoder; the positive output end of the feedback DAC1 is connected to the input end vi1- of the operational amplifier op1 in the first-stage fully differential active integrator in the form of negative feedback; the negative output end of the feedback DAC1 is connected to the input end vi1+ of the operational amplifier op1 in the first-stage fully differential active integrator in the form of negative feedback; the output end of the delay unit is also the input end, The input end of the feedback DAC2 and the input end of the half-cycle delay circuit; the input end of the delay unit delay1 is connected to the output end of the delay unit; the output end of the delay unit delay1 is connected to the input end of the compensation DACkb; the positive output end of the feedback DAC2 is connected to the positive output end of the compensation DACkb, and is connected to the input end vi3- of the operational amplifier op3 in the third-stage fully differential active integrator in the form of negative feedback; the negative output end of the feedback DAC2 is connected to the negative output end of the compensation DACkb, and is connected to the input end vi3+ of the operational amplifier op3 in the third-stage fully differential active integrator in the form of negative feedback.

[0012] The beneficial effects of the present invention are as follows: the present invention realizes a sigma-delta modulator capable of switching between two different modes. Compared with the traditional scheme, the present invention utilizes a reconfigurable integrator to realize the mutual switching between the active integration mode and the passive integration mode. When the sigma-delta modulator is in the active integration mode, high-precision conversion can be realized. When the sigma-delta modulator is in the passive integration mode, a low-power consumption mode can be realized. Moreover, since the passive integration mode uses the integration capacitor parallel connection technology, this technology significantly improves the accuracy of the low-power consumption mode, thereby improving the performance of the sigma-delta modulator, and realizing a high-precision reconfigurable sigma-delta modulator. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. The drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0014] Figure 1 It is a circuit structure diagram of a continuous-time reconfigurable sigma-delta modulator of the present invention;

[0015] Figure 2 A schematic diagram of the output spectrum of a continuous-time reconfigurable sigma-delta modulator of the present invention when a 17.5kHz signal is input in an active working mode;

[0016] Figure 3 The figure is a schematic diagram of the output spectrum of a continuous-time reconfigurable sigma-delta modulator of the present invention when a 17.5 kHz signal is input in a passive working mode. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. Examples of these preferred embodiments are illustrated in the accompanying drawings. The embodiments of the present invention described in the accompanying drawings are merely exemplary and are not limited to these embodiments.

[0018] In addition, it should be noted that in order to avoid obscuring the present invention due to unnecessary details, only structures and / or processing steps closely related to the solutions according to the present invention are shown in the accompanying drawings, while other details that are not closely related to the present invention are omitted.

[0019] Also, in the description of the present invention, the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] In order to illustrate the technical solution of the present invention, a specific embodiment is used below for description, and only the parts related to the embodiment of the present invention are shown.

[0022] See also Figure 1A continuous-time reconfigurable sigma-delta modulator mainly includes the following circuits: a first-stage fully differential active integrator, a second-stage reconfigurable integrator, a third-stage fully differential active integrator, a multi-bit quantizer, an encoder, a feedback DAC1, a feedback DAC2, a half-cycle delay circuit, and a delay unit; wherein the resistor Rf2, the resistor R21, the capacitor C2, the switch SW1, the switch SW2, and the switch SW3 in the second-stage reconfigurable integrator are used for both the active mode and the passive mode of the circuit;

[0023] The two differential signal input ports VINP and VINN of the first-stage fully differential active integrator are signal input terminals of the continuous-time reconfigurable sigma-delta modulator; the output terminal of the first-stage fully differential active integrator is connected to the input terminal of the second-stage reconfigurable integrator; the output terminal of the second-stage reconfigurable integrator is connected to the input terminal of the third-stage fully differential active integrator; the output terminal of the third-stage fully differential active integrator is connected to the input terminal of the multi-bit quantizer; the output terminal of the multi-bit quantizer is connected to the input terminal of the encoder; the output terminal of the multi-bit quantizer is connected to the delay The input end of the unit is connected; the output end of the delay unit is connected to the input end of the half-cycle delay circuit; the output end of the delay unit is connected to the input end of the feedback DAC2; the output end of the delay unit is connected to the input end of the feedback DAC1; the output end of the feedback DAC1 is connected to the input end of the first-stage fully differential active integrator; the output end of the feedback DAC2 is connected to the input end of the third-stage fully differential active integrator; the output end of the half-cycle delay circuit is connected to the input end of the third-stage fully differential active integrator; the input end OUT of the encoder outputs the final quantization result;

[0024] Specifically, the first-stage fully differential active integrator adopts a fully differential structure, including a first-stage feedforward resistor Rf1, a first-stage integrating resistor R1, a first-stage integrating capacitor C1, and an operational amplifier op1; the first-stage fully differential active integrator is used to perform first-order integration on a differential input signal; wherein the first-stage feedforward resistor Rf1 includes a resistor Rf11 and a resistor Rf12, the first-stage integrating resistor R1 includes a resistor R11 and a resistor R12, and the first-stage integrating capacitor C1 includes a capacitor C11 and a capacitor C12; the signal input terminals VINN and VINP of the continuous-time reconfigurable sigma-delta modulator are simultaneously the input terminals of the first-stage integrating resistors R11 and R12 and the input terminals of the first-stage feedforward resistors Rf11 and Rf12; the output terminal of the first-stage integrating resistor R11 is simultaneously the input terminal of the first-stage integrating capacitor C11 and the input terminal vi1- of the operational amplifier op1; The output end of the first-stage integrating resistor R11 is also the output end of the feedback DAC1; the output end of the first-stage integrating resistor R12 is also the input end of the first-stage integrating capacitor C12 and the input end vi1+ of the operational amplifier op1; the output end of the first-stage integrating resistor R12 is also the output end of the feedback DAC1; the output end of the first-stage integrating capacitor C11 is also the output end vo1+ of the operational amplifier op1 and the input end of the second-stage reconfigurable integrator; the output end of the first-stage integrating capacitor C12 is also the output end vo1- of the operational amplifier op1 and the input end of the second-stage reconfigurable integrator; the output end of the first-stage feed-forward resistor Rf11 is connected to the output end of the third-stage feed-forward resistor Rf31 in the second-stage reconfigurable integrator; the output end of the first-stage feed-forward resistor Rf12 is connected to the output end of the third-stage feed-forward resistor Rf32 in the second-stage reconfigurable integrator;

[0025] Specifically, the second-stage reconfigurable integrator adopts a fully differential structure, including a second-stage feedforward resistor Rf2, a third-stage feedforward resistor Rf3, a second-stage integral resistor R2, a second-stage integral capacitor C2, a first-stage switch SW1, a second-stage switch SW2, a third-stage switch SW3, an operational amplifier op2, a connection point A, and a connection point B; the second-stage reconfigurable integrator is used to perform a first-order integration on the input signal; wherein the second-stage feedforward resistor Rf2 includes a resistor Rf21 and a resistor Rf22, the third-stage feedforward resistor Rf3 includes a resistor Rf31 and a resistor Rf32, the second-stage integral resistor R2 includes a resistor R21, a resistor R22, a resistor R23, and a resistor R24, and the second-stage integral resistor R The capacitor C2 includes a capacitor C21 and a capacitor C22, the first-stage switch SW1 includes a switch SW11 and a switch SW12, the second-stage switch SW2 includes a switch SW21 and a switch SW22, and the third-stage switch SW3 includes a switch SW31 and a switch SW32; the input end of the second-stage integrating resistor R21 is simultaneously the input end of the second-stage feedforward resistor Rf21 and the output end vo1- of the operational amplifier op1 in the first-stage fully differential active integrator; the input end of the second-stage integrating resistor R22 is simultaneously the output end of the second-stage integrating resistor R21 and the input end of the second-stage switch SW21; the input end of the second-stage integrating resistor R23 is simultaneously the input end of the second-stage feedforward resistor Rf21 The input end of the second-stage feed-forward resistor Rf22 is connected to the output end vo1+ of the operational amplifier op1 in the first-stage fully differential active integrator; the input end of the second-stage integrating resistor R24 ​​is also the output end of the second-stage integrating resistor R23 and the input end of the second-stage switch SW22; the input end of the second-stage integrating capacitor C21 is also the output end of the second-stage integrating resistor R22 and the input end vi2- of the operational amplifier op2; the input end of the second-stage integrating capacitor C22 is also the output end of the second-stage integrating resistor R24 ​​and the input end vi2+ of the operational amplifier op2; the input end of the first-stage switch SW11 is connected to the output end of the second-stage feed-forward resistor Rf21 ; The input end of the first-stage switch SW12 is connected to the output end of the second-stage feed-forward resistor Rf22; the input end of the third-stage feed-forward resistor Rf31 is connected to the output end ① of the first-stage switch SW11; the input end of the third-stage feed-forward resistor Rf32 is connected to the output end ① of the first-stage switch SW12; the output end ② of the first-stage switch SW11 is simultaneously the output end of the third-stage feed-forward resistor Rf31 and the input end of the third-stage integrating capacitor C31 in the third-stage fully differential active integrator; the output end ② of the first-stage switch SW12 is simultaneously the output end of the third-stage feed-forward resistor Rf32 and the input end of the third-stage integrating capacitor C32 in the third-stage fully differential active integrator;The output end of the second-stage switch SW21 is simultaneously the output end ① of the third-stage switch SW32 and the input end of the third-stage integrating resistor R31 in the third-stage fully differential active integrator; the output end of the second-stage switch SW22 is simultaneously the output end ① of the third-stage switch SW32 and the input end of the third-stage integrating resistor R32 in the third-stage fully differential active integrator; the input end of the third-stage switch SW31 is simultaneously the output end of the second-stage integrating capacitor C21 and the output end vo2+ of the operational amplifier op2; the input end of the third-stage switch SW32 is simultaneously the output end of the second-stage integrating capacitor C22 and the output end vo2- of the operational amplifier op2; the connection point A is simultaneously the output end ② of the third-stage switch SW31 and the output end of the first-stage feedback resistor Rb2 in the third-stage fully differential active integrator; the connection point B is simultaneously the output end ② of the third-stage switch SW32 and the output end of the first-stage feedback resistor Rb1 in the third-stage fully differential active integrator;

[0026] Specifically, the third-stage fully differential active integrator adopts a fully differential structure, including a third-stage integrating resistor R3, a third-stage integrating capacitor C3, a first-stage feedback resistor Rb and an operational amplifier op3; the third-stage fully differential active integrator is used to perform a first-order integration on an input signal; wherein the third-stage integrating resistor R3 includes a resistor R31 and a resistor R32, the third-stage integrating capacitor C3 includes an integrating capacitor C31 and an integrating capacitor C32, and the first-stage feedback resistor Rb includes a resistor Rb1 and a resistor Rb2; the input end of the third-stage integrating resistor R31 is simultaneously the output end ① of the third-stage switch SW32 and the output end of the second-stage switch SW21; the input end of the third-stage integrating resistor R32 is simultaneously the output end ① of the third-stage switch SW31 and the output end of the second-stage switch SW22; the input end of the third-stage integrating capacitor C31 is simultaneously the output end of the third-stage integrating resistor R31 and the input end vi3- of the operational amplifier op3 ; The input end of the third-stage integrating capacitor C31 is simultaneously the output end ② of the first-stage switch SW11 and the output end of the feedback DAC2; the input end of the third-stage integrating capacitor C32 is simultaneously the output end of the third-stage integrating resistor R32 and the input end vi3+ of the operational amplifier op3; the input end of the third-stage integrating capacitor C32 is simultaneously the output end ② of the first-stage switch SW12 and the output end of the feedback DAC2; the input end of the first-stage feedback resistor Rb1 is simultaneously the output end of the third-stage integrating capacitor C31 and the input end vo3+ of the operational amplifier op3; the input end of the first-stage feedback resistor Rb2 is simultaneously the output end of the third-stage integrating capacitor C32 and the input end vo3- of the operational amplifier op3; the input end vo3+ of the operational amplifier op3 and the input end vo3- of the operational amplifier op3 are simultaneously the output end of the third-stage fully differential active integrator and the input end of the multi-bit quantizer;

[0027] Specifically, the half-cycle delay circuit includes a delay unit delay1 and a compensation DACkb; the input end of the multi-bit quantizer is connected to the output end of the third-stage fully differential active integrator; the output end of the multi-bit quantizer is also the input end of the delay unit and the input end of the encoder; the positive output end of the feedback DAC1 is connected to the input end vi1- of the operational amplifier op1 in the first-stage fully differential active integrator in the form of negative feedback; the negative output end of the feedback DAC1 is connected to the input end vi1+ of the operational amplifier op1 in the first-stage fully differential active integrator in the form of negative feedback; the output end of the delay unit is also the input end of the feedback DAC1, the The input end of the feedback DAC2 and the input end of the half-cycle delay circuit; the input end of the delay unit delay1 is connected to the output end of the delay unit; the output end of the delay unit delay1 is connected to the input end of the compensation DACkb; the positive output end of the feedback DAC2 is connected to the positive output end of the compensation DACkb, and is connected to the input end vi3- of the operational amplifier op3 in the third-stage fully differential active integrator in the form of negative feedback; the negative output end of the feedback DAC2 is connected to the negative output end of the compensation DACkb, and is connected to the input end vi3+ of the operational amplifier op3 in the third-stage fully differential active integrator in the form of negative feedback.

[0028] In this example: differential input signals VINP and VINN are input from one end of the first-stage integration resistors R12 and R11, the first-stage fully differential active integrator (101) performs first-order integration on the differential signals through capacitors C11 and C12, and the integrated signals are output from the differential output end of the operational amplifier op1 to the second-stage reconfigurable integrator (102), and at the same time, the differential input signals VINP and VINN are also input to the input ends of the third-stage integration capacitors C32 and C31 in the third-stage fully differential active integrator (103) through the first-stage feedforward resistors Rf12 and Rf11 for addition operation;

[0029] When the circuit operates in the active integration mode, the output terminal ① of the first-stage switch SW1 in the second-stage reconfigurable integrator (102) is turned on, the second-stage switch SW2 is turned off, the output terminal ① of the third-stage switch SW3 is turned on, and the operational amplifier op2 operates normally. The input terminal of the second-stage reconfigurable integrator (102) is connected to the output terminal of the first-stage fully differential active integrator (101). The second-stage reconfigurable integrator (102) performs a first-order integration on the integrated signal output by the first-stage fully differential active integrator (101) through capacitors C21 and C22. The integrated signal is output from the differential output terminal of the operational amplifier op2 and is transmitted through switches SW31 and SW41, respectively. The switch SW32 is input to the third-stage fully differential active integrator (103); at the same time, the differential signal passes through the second-stage feedforward resistors Rf21 and Rf22, passes through the first-stage switches SW11 and SW12 and the third-stage feedforward resistors Rf31 and Rf32, and is output to the input ends of the third-stage integration capacitors C31 and C32 in the third-stage fully differential active integrator (103) for addition operation, thereby reducing the use of one feedback DAC, thereby reducing device expenses; the output signal of the third-stage fully differential active integrator (103) is connected to the connection point B through the first-stage feedback resistor Rb1 and is connected to the connection point A through the first-stage feedback resistor Rb2, thereby playing a feedback role;

[0030] When the circuit operates in the passive integration mode, the output terminal ② of the first-stage switch SW1 in the second-stage reconfigurable integrator (102) is turned on, the second-stage switch SW2 is closed, the output terminal ② of the third-stage switch SW3 is turned on, and the operational amplifier op2 is turned off; the input terminal of the second-stage reconfigurable integrator (102) is connected to the output terminal of the first-stage fully differential active integrator (101); the second-stage reconfigurable integrator (102) performs first-order integration on the integrated signal output by the first-stage fully differential active integrator (101) through capacitors C21 and C22; the integrated signal is output from the input terminals of resistors R22 and R24 and input to the third-stage fully differential active integrator (103); the input terminal of the capacitor C21 is connected to the output terminal ② of the capacitor C21 through the output terminal ② of the capacitor C22. The output end of capacitor C22 is connected to the output end of capacitor C21, and the input end of capacitor C22 is connected to the output end of capacitor C21 through the output end ② of SW31, so as to form a structure in which capacitors C21 and C22 are connected in parallel. This structure improves the gain of the passive integrator, thereby improving the performance of the modulator working in a passive state. At the same time, the differential signal is output to the input end of the third-stage integration capacitors C31 and C32 in the third-stage fully differential active integrator (103) through the second-stage feedforward resistors Rf21 and Rf22 and the first-stage switches SW11 and SW12 for addition operation. The output signal of the third-stage fully differential active integrator (103) is connected to the connection point B through the first-stage feedback resistor Rb1 and is connected to the connection point A through the first-stage feedback resistor Rb2, so as to play a feedback role.

[0031] The input end of the third-stage fully differential active integrator (103) is connected to the output end of the second-stage reconfigurable integrator (102); the integrated signal passing through the second-stage reconfigurable integrator (102) is input from one end of the third-stage integrating resistors R31 and R32, and first-order integration is achieved through capacitors C31 and C32; the integrated signal is output from the differential output end of the operational amplifier op3 to the input end of the multi-bit quantizer (104);

[0032] The output of the third-stage fully differential active integrator (103) is used as the input of the multi-bit quantizer (104). In this example, the multi-bit quantizer is a 4-bit SAR ADC. DAC Capacitor drive, C DAC It consists of capacitor array, comparator, SAR logic and latch;

[0033] The 4-bit binary code output by the multi-bit quantizer (104) is input to the half-cycle delay circuit (108) and the delay unit (109); the feedback signal is delayed by half a cycle through the delay unit (109) and then input to the input end of the feedback DAC1 (106), the input end of the feedback DAC2 (107) and the input end of the half-cycle delay circuit (108); the input end of the feedback DAC1 (106), the feedback DAC2 (107) and the feedback DACkb all adopt a current steering DAC structure; the current signal passing through the half-cycle delay circuit (108) is added to the current signal passing through the feedback DAC2 (107), and then the capacitors C31 and C32 are charged to achieve negative feedback; the current signal passing through the feedback DAC1 (106) charges the capacitors C11 and C12 to achieve negative feedback.

[0034] The embodiment of the present invention is used in the audio field, and the working frequency band is 0-20KHz. It should be noted that the working frequency band of the embodiment is only an example and is not a limitation on the specific working frequency. In actual design, the present invention can be applied to different frequency bands.

[0035] See also Figure 2, transient simulation FFT results of a continuous-time reconfigurable sigma-delta modulator in active mode. Set the resistance values ​​of R11 and R12 to be the same, the resistance values ​​of R21 and R23 to be the same, the resistance values ​​of R22 and R24 to be the same, the resistance values ​​of R31 and R32 to be the same, the resistance values ​​of Rf11 and Rf12 to be the same, the resistance values ​​of Rf21 and Rf22 to be the same, the resistance values ​​of Rf31 and Rf32 to be the same, the resistance values ​​of Rb1 and Rb2 to be the same, the capacitance values ​​of C11 and C12 to be the same, the capacitance values ​​of C21 and C22 to be the same, and the capacitance values ​​of C31 and C32 to be the same. The continuous-time reconfigurable sigma-delta modulator of the present invention has an effective number of bits (ENOB) of 16.89 bits, a power consumption of 767uW, a signal-to-noise ratio (SNR) of 103.46dB, and a spurious-free dynamic range (SFDR) of 108.24dB under an active mode operating voltage of 1.8V, a sampling frequency of 5.12MHz, an input signal frequency of 17.5kHz, and a bandwidth of 20K.

[0036] See also Figure 3 , transient simulation FFT results of a continuous-time reconfigurable sigma-delta modulator in passive mode. Set the resistance values ​​of R11 and R12 to be the same, the resistance values ​​of R21 and R23 to be the same, the resistance values ​​of R22 and R24 to be the same, the resistance values ​​of R31 and R32 to be the same, the resistance values ​​of Rf11 and Rf12 to be the same, the resistance values ​​of Rf21 and Rf22 to be the same, the resistance values ​​of Rb1 and Rb2 to be the same, the capacitance values ​​of C11 and C12 to be the same, the capacitance values ​​of C21 and C22 to be the same, and the capacitance values ​​of C31 and C32 to be the same. The sigma-delta modulator of the present invention has an operating voltage of 1.8V in passive mode, a sampling frequency of 5.12MHz, an input signal frequency of 17.5kHz, and a bandwidth of 20K. The effective number of bits (ENOB) of the sigma-delta modulator is 14.2bits, the power consumption is 580uW, the signal-to-noise ratio (SNR) is 87.29dB, and the spurious-free dynamic range (SFDR) is 92.55dB.

[0037] In addition, it should be noted that in this specification, "includes", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0038] It should be understood that although this specification is described according to implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A continuous-time reconfigurable sigma-delta modulator (100), characterized in that: The invention comprises the following circuits: a first-stage fully differential active integrator (101), a second-stage reconfigurable integrator (102), a third-stage fully differential active integrator (103), a multi-bit quantizer (104), an encoder (105), a feedback DAC1 (106), a feedback DAC2 (107), a half-cycle delay circuit (108), and a delay unit (109); wherein the resistor Rf2, the resistor R21, the capacitor C2, the switch SW1, the switch SW2, and the switch SW3 in the second-stage reconfigurable integrator (102) are used for both the active mode and the passive mode of the circuit; The two differential signal input ports VINP and VINN of the first-stage fully differential active integrator (101) are signal input terminals of the continuous-time reconfigurable sigma-delta modulator (100); the output terminal of the first-stage fully differential active integrator (101) is connected to the input terminal of the second-stage reconfigurable integrator (102); the output terminal of the second-stage reconfigurable integrator (102) is connected to the input terminal of the third-stage fully differential active integrator (103); the output terminal of the third-stage fully differential active integrator (103) is connected to the input terminal of the multi-bit quantizer (104); the output terminal of the multi-bit quantizer (104) is connected to the input terminal of the encoder (105); the output terminal of the multi-bit quantizer (104) is connected to the input terminal of the delay unit (109); The input end of the delay unit (109) is connected to the input end of the half-cycle delay circuit (108); the output end of the delay unit (109) is connected to the input end of the feedback DAC2 (107); the output end of the delay unit (109) is connected to the input end of the feedback DAC1 (106); the output end of the feedback DAC1 (106) is connected to the input end of the first-stage fully differential active integrator (101); the output end of the feedback DAC2 (107) is connected to the input end of the third-stage fully differential active integrator (103); the output end of the half-cycle delay circuit (108) is connected to the input end of the third-stage fully differential active integrator (103); and the input end OUT of the encoder (105) outputs the final quantization result.

2. A continuous-time reconfigurable sigma-delta modulator (100) according to claim 1, characterized in that: The first-stage fully differential active integrator (101) adopts a fully differential structure, comprising a first-stage feedforward resistor Rf1, a first-stage integrating resistor R1, a first-stage integrating capacitor C1, and an operational amplifier op1; the first-stage fully differential active integrator (101) is used to perform first-order integration on a differential input signal; wherein the first-stage feedforward resistor Rf1 comprises a resistor Rf11 and a resistor Rf12, the first-stage integrating resistor R1 comprises a resistor R11 and a resistor R12, and the first-stage integrating capacitor C1 comprises a capacitor C11 and a capacitor C12; the signal input terminals VINN and VINP of the continuous-time reconfigurable sigma-delta modulator (100) are simultaneously the input terminals of the first-stage integrating resistors R11 and R12 and the input terminals of the first-stage feedforward resistors Rf11 and Rf12; the output terminal of the first-stage integrating resistor R11 is simultaneously the input terminal of the first-stage integrating capacitor C11 and the input terminal vi1- of the operational amplifier op1; the first-stage integrating resistor R1 The output end of the first-stage integrating resistor R12 is also the output end of the first-stage integrating capacitor C12 and the input end vi1+ of the operational amplifier op1; the output end of the first-stage integrating resistor R12 is also the output end of the feedback DAC1 (106); the output end of the first-stage integrating capacitor C11 is also the output end vo1+ of the operational amplifier op1 and the input end of the second-stage reconfigurable integrator (102); the output end of the first-stage integrating capacitor C12 is also the output end vo1- of the operational amplifier op1 and the input end of the second-stage reconfigurable integrator (102); the output end of the first-stage feedforward resistor Rf11 is connected to the output end of the third-stage feedforward resistor Rf31 in the second-stage reconfigurable integrator (102); the output end of the first-stage feedforward resistor Rf12 is connected to the output end of the third-stage feedforward resistor Rf32 in the second-stage reconfigurable integrator (102).

3. The continuous-time reconfigurable sigma-delta modulator (100) according to claim 1, characterized in that: The second-stage reconfigurable integrator (102) adopts a fully differential structure, comprising a second-stage feedforward resistor Rf2, a third-stage feedforward resistor Rf3, a second-stage integration resistor R2, a second-stage integration capacitor C2, a first-stage switch SW1, a second-stage switch SW2, a third-stage switch SW3, an operational amplifier op2, a connection point A, and a connection point B; the second-stage reconfigurable integrator (102) is used to perform a first-order integration on an input signal; wherein the second-stage feedforward resistor Rf2 comprises a resistor Rf21 and a resistor Rf22, the third-stage feedforward resistor Rf3 comprises a resistor Rf31 and a resistor Rf32, the second-stage integration resistor R2 comprises a resistor R21, a resistor R22, a resistor R23, and a resistor R24, and the second-stage integration resistor R The capacitor C2 includes a capacitor C21 and a capacitor C22, the first-stage switch SW1 includes a switch SW11 and a switch SW12, the second-stage switch SW2 includes a switch SW21 and a switch SW22, and the third-stage switch SW3 includes a switch SW31 and a switch SW32; the input end of the second-stage integrating resistor R21 is simultaneously the input end of the second-stage feedforward resistor Rf21 and the output end vo1- of the operational amplifier op1 in the first-stage fully differential active integrator (101); the input end of the second-stage integrating resistor R22 is simultaneously the output end of the second-stage integrating resistor R21 and the input end of the second-stage switch SW21; the input end of the second-stage integrating resistor R23 is simultaneously the input end of the second-stage feedforward resistor Rf21 The first-stage fully differential active integrator (101) is connected to the input end of the second-stage integrating resistor Rf22 and the output end vo1+ of the operational amplifier op1 in the first-stage fully differential active integrator (101); the input end of the second-stage integrating resistor R24 ​​is simultaneously the output end of the second-stage integrating resistor R23 and the input end of the second-stage switch SW22; the input end of the second-stage integrating capacitor C21 is simultaneously the output end of the second-stage integrating resistor R22 and the input end vi2- of the operational amplifier op2; the input end of the second-stage integrating capacitor C22 is simultaneously the output end of the second-stage integrating resistor R24 ​​and the input end vi2+ of the operational amplifier op2; the input end of the first-stage switch SW11 is connected to the output end of the second-stage feedforward resistor Rf21; The input end of the first-stage switch SW12 is connected to the output end of the second-stage feedforward resistor Rf22; the input end of the third-stage feedforward resistor Rf31 is connected to the output end ① of the first-stage switch SW11; the input end of the third-stage feedforward resistor Rf32 is connected to the output end ① of the first-stage switch SW12; the output end ② of the first-stage switch SW11 is simultaneously the output end of the third-stage feedforward resistor Rf31 and the input end of the third-stage integrating capacitor C31 in the third-stage fully differential active integrator (103); the output end ② of the first-stage switch SW12 is simultaneously the output end of the third-stage feedforward resistor Rf32 and the input end of the third-stage integrating capacitor C32 in the third-stage fully differential active integrator (103);The output end of the second-stage switch SW21 is simultaneously the output end ① of the third-stage switch SW32 and the input end of the third-stage integrating resistor R31 in the third-stage fully differential active integrator (103); the output end of the second-stage switch SW22 is simultaneously the output end ① of the third-stage switch SW32 and the input end of the third-stage integrating resistor R32 in the third-stage fully differential active integrator (103); the input end of the third-stage switch SW31 is simultaneously the output end of the second-stage integrating capacitor C21 and the operational amplifier op2 The output terminal vo2+ of the third-stage switch SW32; the input terminal of the third-stage switch SW32 is simultaneously the output terminal of the second-stage integration capacitor C22 and the output terminal vo2- of the operational amplifier op2; the connection point A is simultaneously the output terminal ② of the third-stage switch SW31 and the output terminal of the first-stage feedback resistor Rb2 in the third-stage fully differential active integrator (103); the connection point B is simultaneously the output terminal ② of the third-stage switch SW32 and the output terminal of the first-stage feedback resistor Rb1 in the third-stage fully differential active integrator (103). ; 4. The continuous-time reconfigurable sigma-delta modulator (100) according to claim 1, characterized in that: The third-stage fully differential active integrator (103) adopts a fully differential structure, comprising a third-stage integrating resistor R3, a third-stage integrating capacitor C3, a first-stage feedback resistor Rb and an operational amplifier op3; the third-stage fully differential active integrator (103) is used to perform first-order integration on an input signal; wherein the third-stage integrating resistor R3 comprises a resistor R31 and a resistor R32, the third-stage integrating capacitor C3 comprises an integrating capacitor C31 and an integrating capacitor C32, and the first-stage feedback resistor Rb comprises a resistor Rb1 and a resistor Rb2; the input end of the third-stage integrating resistor R31 is simultaneously the output end ① of the third-stage switch SW32 and the output end of the second-stage switch SW21; the input end of the third-stage integrating resistor R32 is simultaneously the output end ① of the third-stage switch SW31 and the output end of the second-stage switch SW22; the input end of the third-stage integrating capacitor C31 is simultaneously the output end of the third-stage integrating resistor R31 and the input end vi3- of the operational amplifier op3; The input end of the integrating capacitor C31 is simultaneously the output end ② of the first-stage switch SW11 and the output end of the feedback DAC2 (107); the input end of the third-stage integrating capacitor C32 is simultaneously the output end of the third-stage integrating resistor R32 and the input end vi3+ of the operational amplifier op3; the input end of the third-stage integrating capacitor C32 is simultaneously the output end ② of the first-stage switch SW12 and the output end of the feedback DAC2 (107); the input end of the first-stage feedback resistor Rb1 is simultaneously the output end of the third-stage integrating capacitor C31 and the input end vo3+ of the operational amplifier op3; the input end of the first-stage feedback resistor Rb2 is simultaneously the output end of the third-stage integrating capacitor C32 and the input end vo3- of the operational amplifier op3; the input end vo3+ of the operational amplifier op3 and the input end vo3- of the operational amplifier op3 are simultaneously the output end of the third-stage fully differential active integrator (103) and the input end of the multi-bit quantizer (104).

5. The continuous-time reconfigurable sigma-delta modulator (100) according to claim 1, characterized in that: The half-cycle delay circuit (108) comprises a delay unit delay1 and a compensation DACkb; the input end of the multi-bit quantizer (104) is connected to the output end of the third-stage fully differential active integrator (103); the output end of the multi-bit quantizer (104) is simultaneously the input end of the delay unit (109) and the input end of the encoder (105); the positive output end of the feedback DAC1 (106) is connected to the input end vi1- of the operational amplifier op1 in the first-stage fully differential active integrator (101) in a negative feedback form; the negative output end of the feedback DAC1 (106) is connected to the input end vi1+ of the operational amplifier op1 in the first-stage fully differential active integrator (101) in a negative feedback form; the output end of the delay unit (109) is simultaneously the input end of the feedback DAC1 The input end of the delay unit delay1 is connected to the output end of the delay unit (109); the output end of the delay unit delay1 is connected to the input end of the compensation DACkb; the positive output end of the feedback DAC2 (107) is connected to the positive output end of the compensation DACkb, and is connected to the input end vi3- of the operational amplifier op3 in the third-stage fully differential active integrator (103) in a negative feedback form; the negative output end of the feedback DAC2 (107) is connected to the negative output end of the compensation DACkb, and is connected to the input end vi3+ of the operational amplifier op3 in the third-stage fully differential active integrator (103) in a negative feedback form.

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