FPGA implementation method of LDPC decoder based on CCDSD standard

Abstract

The invention relates to an FPGA (Field Programmable Gate Array) implementation method of an LDPC (Low Density Parity Check) decoder based on a CCDSD standard, belonging to the technical field of information. The method comprises the following steps: storing a code stream into a channel RAM top layer module, initializing node information, and setting a check matrix; corresponding node information is taken out and transmitted to a check node updating module for check node updating, and the updated node information is stored in a corresponding check RAM block; variable node information is obtained in the variable RAM module according to the variable node updating addressing mode, the variable node information is updated, and the updated variable node information is stored in a variable RAM block according to the same addressing mode; a sign bit of each code word is taken out and transmitted to a hard decision module for LDPC verification, and if verification is passed, decoding is ended; and if the verification is not passed, carrying out iterative updating on the verification node and the variable node until the end. According to the invention, the accuracy of a decoding result can be ensured.

Description

Technical Field

[0001] The invention belongs to the field of information technology and relates to an FPGA implementation method of an LDPC decoder based on the CCDSD standard. Background Art

[0002] In digital communication systems, low-density parity-check (LDPC) codes are widely used due to their excellent error correction performance and low decoding complexity. In particular, in fields such as aerospace communications, LDPC codes have become one of the standards for data transmission. As an authoritative consulting organization for space data systems, CCDSD (Consultative Committee for Space Data Systems) has formulated a series of standards for LDPC codes.

[0003] However, the decoding process of LDPC codes is relatively complex, especially when processing large-scale data. Traditional decoding methods have bottlenecks in processing speed and resource consumption, and are difficult to meet the needs of high-speed and real-time communication. Therefore, it is particularly important to develop an efficient and low-power LDPC decoder.

[0004] LDPC decoders based on FPGA (field programmable gate array) have attracted much attention due to their parallel processing capabilities and programmability. FPGA allows developers to customize the hardware structure according to specific algorithms, thereby achieving efficient data processing. However, it is not easy to map the LDPC decoding algorithm to FPGA, especially when processing large-scale LDPC codes, such as the (8192,4096) LDPC code of the CCDSD standard. Existing FPGA implementation methods often have problems such as low resource utilization, slow decoding speed or high hardware complexity. Therefore, an improved FPGA implementation method is urgently needed to improve the performance and efficiency of the LDPC decoder. Summary of the invention

[0005] In view of this, the object of the present invention is to provide an FPGA implementation method of an LDPC decoder based on the CCDSD standard.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] An FPGA implementation method of an LDPC decoder based on the CCDSD standard, the method comprising the following steps:

[0008] S1, storing the acquired code stream in the channel RAM top-level module according to the preset addressing mode, initializing the node information of the code words stored in several channel RAM blocks, and setting the check matrix;

[0009] S2, respectively taking out the corresponding node information from the corresponding channel RAM block and transferring it to the check node update module to update the check node, and storing the updated node information in the corresponding check RAM block;

[0010] S3, obtaining variable node information in the variable RAM module according to the variable node update addressing mode, updating the variable node information, and storing the updated variable node information in the variable RAM block according to the same addressing mode;

[0011] S4. Take out the sign bit of each codeword and pass it into the hard decision module for LDPC check. If the check passes, the decoding is completed; if the check fails, the check node and the variable node are iteratively updated until the check passes or the maximum iteration round is reached.

[0012] Further, in step S1, a plurality of preset depths and widths of N are configured in the channel RAM top module. q The code stream is transferred to the top layer of the channel RAM and is stored in the corresponding channel RAM block according to the following addressing method:

[0013] The read address of each RAM block is …, Channel_addr7, each read address takes the natural sequence number of the code element; the minimum expansion and algorithm is used for encoding, and the node information is initialized as the prior log-likelihood function of the code element:

[0014]

[0015] Where N0 is the noise power spectral density, y is the received codeword, p(0) represents the prior probability density corresponding to information bit 0, and p(1) represents the prior probability density corresponding to information bit 1.

[0016] Further, in step S1, a (8192, 4096) check matrix based on the CCDSD standard is constructed, which is expressed as:

[0017]

[0018] Among them I M is the unit matrix, 0 M is a zero matrix, Π2~Π8 are circulant matrices, and the position of element i in the i-th row and the π-th row k (i) column, where

[0019]

[0020] In the formula, θ k To find the preset constant for the position of element i in the kth RAM block, φ k(·) is the value function, floor() represents the floor function, and M represents the total number of rows in the block matrix.

[0021] Further, in step S2, the check RAM top-level module configures a number of single-port check RAM blocks with preset depth and width, and takes out the corresponding LLR data from the channel RAM block according to the specified clock cycle. The check node number to be updated is j, and then the corresponding LLR data is assigned in sequence according to the position of the connected variable node, and the corresponding LLR data is taken out from the corresponding channel RAM block respectively, and is transmitted to the check node update module to update the check node, wherein the probability information transmitted from the jth check node to the ith variable node is expressed as:

[0022] q ij (b) = Pr(c i =b|S i ,y i ,M c (~j))

[0023] In the formula, y i is the i-th code element in the codeword, S i Indicates all containing variable c i The event that all the verification equations of M are satisfied; c (~j) represents all information except the check node j, c i is the i-th variable node, corresponding to the i-th column of the check matrix; b = 0, 1 is the information bit restored after the received codeword makes a hard decision; take its log-likelihood ratio L(q ij ):

[0024]

[0025] The verification node update module completes the following operations:

[0026]

[0027] In the formula, q i′j is the probability information transmitted from variable node i′ to check node j, r ji is the probability information transmitted from the check node j to the variable node i, L(·) is the logarithmic ratio, α i′j is L(q i′j ), β i′j For its amplitude part, “V i \i" represents the set of variable nodes connected to check node i.

[0028] Further, in step S2, after each check node is updated, a total of ω is generated r probability information, respectively denoted as where i0, ..., ω connected to j r variable node number;

[0029] Set the bit width to N w (N w ≥N q ), first concatenate to ω r ·N w Length of the fragment and push 48N q The shift register Concat of length, so the data in Concat is updated every 8 clock cycles; every 8 clock cycles, the spliced ​​data is stored in the top module of the verification RAM;

[0030] Assume that the current check node number is j, then the addressing method of the Concat function to store the concatenated data in the top level of the check RAM is:

[0031] Check_block_num=j / 512

[0032] Check_block_num_addr=(j mod 512) / 8

[0033] Among them, Check_block_num is the number of the check RAM block, and Check_block_num_addr is the address in each check RAM block.

[0034] Further, in step S3, the variable RAM top-level module configures a number of variable RAM blocks with a preset depth and width, and obtains probability information from the verification RAM module according to the following addressing method:

[0035] Check_block_num=j / 512

[0036] Check_block_num_addr=(j mod 512) / 8

[0037] outer_offset = (j mod 8) - 6*N q

[0038] inner_offset = π k (j)

[0039] The probability information involved in each variable node is obtained in the spliced ​​fragment according to the above-mentioned addressing method, wherein the probability information transmitted from the i-th check node to the j-th variable node is expressed as:

[0040] r ij (b) = Pr(f i =0|c i =b,M v (~i))

[0041] In the formula, "f i =0" means the i-th verification equation has passed the verification, M v (~i) means excluding variable node c i All information except i is the i-th variable node, corresponding to the i-th column of the check matrix;

[0042] In the minimum expansion sum, take its log-likelihood ratio L(q ij ):

[0043]

[0044] Substitute it into the variable node update module and perform the following calculations:

[0045]

[0046] In the formula, L(·) is the logarithmic ratio, “C i \j" indicates the node c with the variable i The set of connected check nodes except check node j;

[0047] At the same time, the symbol posterior probability is updated according to the following formula:

[0048]

[0049] The updated probability information is still assembled by concat in the same addressing mode and stored in the top layer of variable RAM until all variable nodes are updated.

[0050] Further, in step S4, each time the check node and the variable node are updated, an LDPC check is performed through the hard decision module, wherein the check method is:

[0051] p=cH T

[0052] Where c is the LDPC binary codeword obtained by hard decision, H is the check matrix, and p is the check result vector;

[0053] If the check passes (ie, p=0), the decoding ends; if not, the next round of check node update begins until the check passes or the maximum number of iterations is reached.

[0054] The beneficial effects of the present invention are:

[0055] The present invention significantly improves the speed of LDPC decoding by processing the update of check nodes and variable nodes in parallel. In particular, when processing large-scale LDPC codes, the improvement in decoding speed is particularly obvious. Through reasonable hardware resource allocation and optimized data access strategy, the resource consumption of FPGA-implemented LDPC decoder is reduced, which helps to reduce hardware costs and improve the overall performance of the system. The minimum expansion and algorithm is used for decoding. While maintaining low complexity, the algorithm has excellent error correction performance. Through precise verification and iterative update process, the present invention can ensure the accuracy of the decoding result.

[0056] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0058] Figure 1 It is a schematic diagram of the structure of the channel RAM top-level module of the present invention;

[0059] Figure 2 Schematic diagram of the (8192,4096) check matrix based on the CCDSD standard of the present invention;

[0060] Figure 3 It is a schematic diagram of the structure of the top-level module of the verification RAM of the present invention;

[0061] Figure 4 It is a schematic diagram of the structure of the variable RAM top-level module of the present invention;

[0062] Figure 5 A schematic diagram of the data structure in the verification RAM module;

[0063] Figure 6 It is a schematic diagram of the connection relationship and information transmission between the check nodes and variable nodes of the present invention. DETAILED DESCRIPTION

[0064] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0065] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0066] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0067] See also Figure 1 to Figure 6 , which is an FPGA implementation method of an LDPC decoder based on the CCDSD standard.

[0068] Example

[0069] This embodiment provides a detailed process of an FPGA implementation method of an LDPC decoder based on the CCDSD standard, which includes the following steps:

[0070] S1, storing the acquired code stream in the channel RAM top-level module according to the preset addressing mode, initializing the node information of the code words stored in several channel RAM blocks, and setting the check matrix;

[0071] S2, respectively taking out the corresponding node information from the corresponding channel RAM block and transferring it to the check node update module to update the check node, and storing the updated node information in the corresponding check RAM block;

[0072] S3, obtaining variable node information in the variable RAM module according to the variable node update addressing mode, updating the variable node information, and storing the updated variable node information in the variable RAM block according to the same addressing mode;

[0073] S4. Take out the sign bit of each codeword and pass it into the hard decision module for LDPC check. If the check passes, the decoding is completed; if the check fails, the check node and the variable node are iteratively updated until the check passes or the maximum iteration round is reached.

[0074] In step S1 of this embodiment, Figure 1 As shown, 8 channels with a depth of 8192 and a width of N are configured in the top module of the channel RAM. q The code stream is transferred to the top layer of the channel RAM and is stored in the 8 channel RAM blocks according to the following addressing method:

[0075] The read address of each RAM block is …, Channel_addr7, each read address takes the natural sequence number of the code element; wherein the first natural sequence number starts from 0. The present invention adopts the minimum spread sum algorithm for encoding, wherein the node information is initialized to the prior log-likelihood probability of the code element, and the specific initialization process is:

[0076]

[0077] Where N0 is the noise power spectral density, y is the received codeword, p(0) represents the prior probability density corresponding to information bit 0, and p(1) represents the prior probability density corresponding to information bit 1.

[0078] The (4096,8192) LDPC check matrix H generation method specified by CCDSD (The Consultative Committee for Space Data Systems) is:

[0079]

[0080] Among them I M is the identity matrix, 0 M is a zero matrix, and Π1 to Π8 are circulant matrices. The schematic diagram of H matrix (6144*10240) is as follows Figure 2 As shown, during decoding, rows 0 to 2047 and columns 4096 to 6143 are deleted, and the codeword is parity-checked using the (8192, 4096) check matrix based on the CCDSD standard:

[0081]

[0082] Among them I M is the unit matrix, 0 M is a zero matrix, Π2~Π8 are circulant matrices, and the position of element i in the i-th row and the π-th row k (i) column, where

[0083]

[0084] In the formula, θ k To find the preset constant for the position of element i in the kth RAM block, φ k (·) is the value function, floor() represents the floor function, and M represents the total number of rows in the block matrix. k and φ k The specific values ​​of (·) are shown in Table 1 below:

[0085] Table 1

[0086] k <![CDATA[θ k ]]> <![CDATA[φ k (0,M)]]> <![CDATA[φ k (1,M)]]> <![CDATA[φ k (2,M)]]> <![CDATA[φ k (3,M)]]> l 3 16 0 0 0 2 0 103 53 8 35 3 1 105 74 119 97 4 2 0 45 89 112 5 2 50 47 31 64 6 3 29 0 122 93 7 0 115 59 1 99 8 l 30 102 69 94

[0087] In step S2 of this embodiment, eight memory cells with a depth of 64 and a width of 48N are configured in the top-level module of the verification RAM. w A single-port check RAM block is a Block RAM. One check node is updated in each clock cycle. The check node number to be updated is j. Then, according to the position of the variable node connected to it, addr0, addr1, ..., addr5 are assigned in sequence. The corresponding LLR data is taken out from Channel RAM#0, #1, #2, #3, #4, and #5 respectively, and passed to the check node update module.

[0088] The probability information transmitted from the jth check node to the ith variable node is expressed as:

[0089] q ij (b) = Pr(c i =b|S i ,y i ,M c (~j))

[0090] In the formula, y i is the i-th code element in the codeword, S i Indicates all containing variable c i The event that all the verification equations of M are satisfied; c (~j) represents all information except the check node j, c i is the i-th variable node, corresponding to the i-th column of the check matrix; b=0, 1 is the information bit restored after the received code symbol makes a hard decision.

[0091] In the minimum expansion sum, take its log-likelihood ratio L(q ij):

[0092]

[0093] The verification node update module completes the following operations:

[0094]

[0095] In the formula, q i′j is the probability information transmitted from variable node i′ to check node j, r ji is the probability information transmitted from the check node j to the variable node i, L(·) is the logarithmic ratio, α i′j is L(q i′j ), β i′j For its amplitude part, “V i \i" represents the set of variable nodes connected to check node i.

[0096] After each check node is updated, a total of ω is generated r = 6 probability information, recorded as Among them, i0, i1, i2, i3, i4, and i5 are the numbers of the six variable nodes connected to j.

[0097] Set the bit width to N w (N w ≥N q ), first splice into 6N w Length of the fragment and push 48N q The length of the shift register Concat, so the data in Concat is updated every 8 clock cycles. Every 8 clock cycles, the spliced ​​data is stored in the top-level module of the check RAM, such as Figure 3 shown.

[0098] Assuming that the current check node number is j, the addressing method of the Concat function to store the concatenated data in the top level of the check RAM is:

[0099] Check_block_num=j / 512

[0100] Check_block_num_addr=(j mod 512) / 8

[0101] Among them, Check_block_num is the number of the check RAM block, and Check_block_num_addr is the address in each check RAM block.

[0102] In step S3 of this embodiment, eight variables with a depth of 64 and a width of 48N are configured in the variable RAM top-level module. wThe spliced ​​data is stored in the variable RAM top module every 8 clock cycles, such as Figure 4 shown.

[0103] Each clock cycle updates 8 variable nodes. Specifically, taking node i=2048 as an example, it is connected to 3 check nodes, which are numbered 0, 2988, and 3169. Figure 5 As shown, according to the description of the check RAM data in step S2, the data of each address is composed of 8 check nodes, so the offset of the information of the 2988th check node in the data is (2988mod 8)*6*N w , which is the outer offset. At the same time, the 2048th variable node ranks second in the check, so there is also an offset N within the check q , that is, the inner layer offset. In summary, when the variable node is updated, the addressing method in the top layer of Check RAM is:

[0104] Check_block_num=j / 512

[0105] Check_block_num_addr=(j mod 512) / 8

[0106] outer_offset=(j mod 8)*6*N q

[0107] inner_offset = π k (j)

[0108] The probability information involved in each variable node is obtained in the spliced ​​fragment according to the above-mentioned addressing method, wherein the probability information transmitted from the i-th check node to the j-th variable node is expressed as:

[0109] r ij (b) = Pr(f i =0|c i =b,M v (~i))

[0110] In the formula, "f i =0" means the i-th verification equation has passed the verification, M v (~i) means excluding variable node c i All information except i is the i-th variable node, corresponding to the i-th column of the check matrix;

[0111] In the minimum expansion sum, take its log-likelihood ratio L(q ij ):

[0112]

[0113] Substitute it into the variable node update module and perform the following calculations:

[0114]

[0115] In the formula, L(·) is the logarithmic ratio, “C i \j" indicates the node c with the variable i The set of connected check nodes excluding check node j.

[0116] The updated probability information is still assembled by concat in the same addressing mode and stored in the top layer of variable RAM. After 1024 cycles, the variable node update is completed.

[0117] At the same time, the symbol posterior probability is updated according to the following formula:

[0118]

[0119] In step S4 of this embodiment, Figure 6 The schematic diagram of the connection relationship and information transmission between the check node and the variable node is shown. Under the above minimum spread sum algorithm, N0 only produces a proportional scaling effect, so N0 in the log-likelihood probability representation can be removed, that is, the quantized codeword y itself can be used as the LLR data in the minimum spread sum algorithm. Each time the check node and the variable node are updated, an LDPC check is performed through the hard decision module, where the check method is:

[0120] p=cH T

[0121] Where c is the LDPC binary codeword obtained by hard decision, H is the check matrix, and p is the check result vector;

[0122] If the verification passes, the decoding ends. If not, the next round of verification node update begins.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. An FPGA implementation method of an LDPC decoder based on the CCDSD standard, characterized in that: The method comprises the following steps: S1, storing the acquired code stream in the channel RAM top-level module according to the preset addressing mode, initializing the node information of the code words stored in several channel RAM blocks, and setting the check matrix; S2, respectively taking out the corresponding node information from the corresponding channel RAM block and transferring it to the check node update module to update the check node, and storing the updated node information in the corresponding check RAM block; S3, obtaining variable node information in the variable RAM module according to the variable node update addressing mode, updating the variable node information, and storing the updated variable node information in the variable RAM block according to the same addressing mode; S4. Take out the sign bit of each codeword and pass it into the hard decision module for LDPC check. If the check passes, the decoding is completed; if the check fails, the check node and the variable node are iteratively updated until the check passes or the maximum iteration round is reached.

2. The FPGA implementation method of the LDPC decoder based on the CCDSD standard according to claim 1, characterized in that: In step S1, a plurality of preset depths and widths of N are configured in the channel RAM top module. q The code stream is transferred to the top layer of the channel RAM and stored in the corresponding channel RAM blocks according to the following addressing method: The read address of each RAM block is recorded as Each read address takes the natural sequence number of the code element it fetches; The minimum expansion and algorithm is used for encoding, and the node information is initialized as the prior log-likelihood function of the code element: Where N0 is the noise power spectral density, y is the received codeword, p(0) represents the prior probability density corresponding to information bit 0, and p(1) represents the prior probability density corresponding to information bit 1.

3. The FPGA implementation method of the LDPC decoder based on the CCDSD standard according to claim 2, characterized in that: In step S1, a (8192, 4096) check matrix based on the CCDSD standard is constructed, which is expressed as: Among them I M is the unit matrix, 0 M is a zero matrix, Π2~Π8 are circulant matrices, and the position of element i in the i-th row and the π-th row k (i) column, where Where θ k To find the preset constant for the position of element i in the kth RAM block, φ k (·) is the value function, floor() represents the floor function, and M represents the total number of rows in the block matrix.

4. The FPGA implementation method of the LDPC decoder based on the CCDSD standard according to claim 3, characterized in that: In step S2, the check RAM top-level module configures several single-port check RAM blocks with preset depth and width, and takes out the corresponding LLR data from the channel RAM block according to the specified clock cycle. The check node number to be updated is j, and then the corresponding LLR data is assigned in sequence according to the position of the connected variable node, and the corresponding LLR data is taken out from the corresponding channel RAM block respectively, and is transmitted to the check node update module to update the check node, wherein the probability information transmitted from the jth check node to the ith variable node is expressed as: q ij (b)=Pr(c i =b|S i ,y i ,M c (~j)) In the formula, y i is the i-th code element in the codeword, S i Indicates all the variables containing c i The event that all the verification equations of M are satisfied; c (~j) represents all information except the check node j, c i is the i-th variable node, corresponding to the i-th column of the check matrix; b = 0, 1, is the information bit restored after the received codeword makes a hard decision; take its log-likelihood ratio L(q ij ): The verification node update module completes the following operations: In the formula, q i′j is the probability information transmitted from variable node i′ to check node j, r ji is the probability information transmitted from the check node j to the variable node i, L(·) is the logarithmic ratio, α i′j is L(q i′j ), β i′j For its amplitude part, "V i \i" represents the set of variable nodes connected to check node i.

5. The FPGA implementation method of the LDPC decoder based on the CCDSD standard according to claim 4, characterized in that: In step S2, after each check node is updated, a total of ω is generated. r probability information, respectively denoted as in ω connected to j r variable node number; Set the bit width to N w (N w ≥N q ), first concatenate to ω r ·N w Length of the fragment and push into 48N q The shift register Concat of length, so the data in Concat is updated every 8 clock cycles; every 8 clock cycles, the spliced ​​data is stored in the top module of the verification RAM; Assume that the current check node number is j, then the addressing method of the Concat function to store the concatenated data in the top level of the check RAM is: Check_block_num=j / 512 Check_block_num_addr=(j mod 512) / 8 Among them, Check_block_num is the number of the check RAM block, and Check_block_num_addr is the address in each check RAM block.

6. The FPGA implementation method of the LDPC decoder based on the CCDSD standard according to claim 5, characterized in that: In step S3, the variable RAM top-level module configures several variable RAM blocks with a preset depth and width, and obtains probability information from the verification RAM module according to the following addressing method: Check_block_num=j / 512 Check_block_num_addr=(j mod 512) / 8 outer_offset=(j mod 8)*6*N q inner_offset=π k (j) The probability information involved in each variable node is obtained in the spliced ​​fragment according to the above-mentioned addressing method, wherein the probability information transmitted from the i-th check node to the j-th variable node is expressed as: r ij (b)=Pr(f i =0|c i =b,M v (~i)) In the formula, "f i =0" means the i-th verification equation has passed the verification, M v (~i) means excluding variable node c i All information except i is the i-th variable node, corresponding to the i-th column of the check matrix; In the minimum expansion sum, take its log-likelihood ratio L(q ij ): Substitute it into the variable node update module and perform the following calculations: In the formula, L(·) is the logarithmic ratio, "C i \j" indicates the node c with the variable i The set of connected check nodes except check node j; At the same time, the symbol posterior probability is updated according to the following formula: The updated probability information is still assembled by concat in the same addressing mode and stored in the top layer of variable RAM until all variable nodes are updated.

7. The FPGA implementation method of the LDPC decoder based on the CCDSD standard according to claim 6, characterized in that: In step S4, each time the check node and the variable node are updated, an LDPC check is performed through the hard decision module, wherein the check method is: p=cH T Where c is the LDPC binary codeword obtained by hard decision, H is the check matrix, and p is the check result vector; If the check passes (ie, p=0), the decoding ends; if not, the next round of check node update begins until the check passes or the maximum number of iterations is reached.

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