Ethernet PHY chip debugging method and device, electronic equipment and medium

Abstract

The invention provides an Ethernet PHY chip debugging method and device, electronic equipment and a medium, and the method comprises the steps: configuring a data transmission mode of a PHY chip based on the obtained address information of a target register of the to-be-debugged PHY chip under the condition that the connection state of a state register of the to-be-debugged PHY chip is connected, and in the corresponding data transmission mode, the receiving clock delay duration and / or the sending clock delay duration of the PHY chip are / is detected based on the MAC module. For different PHY chips, the SOC in the FPGA can configure the data transmission mode of the PHY chip according to the obtained address information of the target register of the PHY chip, so that the receiving clock delay durations of the different PHY chips are detected, and / or the sending clock delay durations are detected, and all codes in the FPGA do not need to be recompiled, so that the data transmission efficiency is improved. And the debugging efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a debugging method, device, electronic device and medium for an Ethernet PHY chip. Background Art

[0002] With the development of new energy vehicles, automotive Ethernet came into being. Due to its high transmission rate, low-cost time synchronization function, etc., automotive Ethernet meets the needs of advanced assisted driving, automatic driving and unmanned driving, and thus develops rapidly.

[0003] In the field of automotive Ethernet communications, it is essential to debug the accuracy of the clock delay setting of the PHY (Port Physical Layer) chip to ensure the reliability of data transmission in the communication link. When selecting PHY chips, there are many types of PHY chips. In related technologies, the code in the FPGA is a hardware description language code that is solidified into the FPGA. For different PHY debugging, it is necessary to perform a compilation project on all the codes in the FPGA so that the FPGA can be debugged for different PHY chips. This is time-consuming and has low debugging efficiency. Therefore, how to debug PHY to improve debugging efficiency is a technical problem that needs to be solved. Summary of the invention

[0004] The present application proposes a debugging method, device, electronic device and medium for an Ethernet PHY chip. By setting a SOC module in an FPGA, the SOC module can configure the data transmission mode of the PHY chip according to the address information of the target register of the PHY chip obtained for different PHY chips, so as to test the receiving clock delay time and / or the sending clock delay time of different PHY chips. Compared with the mode configuration for different PHY chips in the related art, all codes in the FPGA need to be recompiled, which improves the debugging efficiency.

[0005] In one aspect, an embodiment of the present application provides a debugging method for an Ethernet PHY chip, including:

[0006] When it is determined that the connection state of the status register of the PHY chip to be debugged is connected, configuring the data transmission mode of the PHY chip based on the address information of the target register of the PHY chip to be debugged;

[0007] In response to the data transmission mode being a receiving mode, synchronously sending a set first clock signal and a first data packet to the PHY chip through the MAC module; wherein the first clock signal is used by the PHY chip in the receiving mode to collect the first data packet sent synchronously with the first clock signal according to the first clock signal and the receiving clock delay time in the configuration data of the PHY chip to obtain a second data packet;

[0008] Acquire a second data packet collected by the PHY chip;

[0009] Based on the comparison result of the first data packet and the second data packet, detecting the delay duration of the receiving clock of the PHY chip;

[0010] and / or, in response to the data transmission mode being a sending mode, acquiring a third data packet collected by the MAC module; wherein the third data packet is obtained by the MAC module receiving the second clock signal and the fourth data packet synchronously sent by the PHY chip, and collecting the fourth data packet sent synchronously with the second clock signal according to the second clock signal and the sending clock delay time of the PHY chip carried by the second clock signal;

[0011] Acquire a fourth data packet sent by the PHY chip;

[0012] Based on the comparison result of the third data packet and the fourth data packet, the delay duration of the sending clock of the PHY chip is detected.

[0013] Another aspect of the present application provides a method for debugging an Ethernet PHY chip, including:

[0014] Determine that the connection state of the status register of the PHY chip to be debugged is connected, and determine the data transmission mode of the PHY chip; wherein the data transmission mode is obtained by configuring the PHY chip by the SOC based on the address information of the target register of the PHY chip to be debugged obtained;

[0015] In response to the data transmission mode of the PHY chip to be debugged being configured as the receiving mode, a first data packet sent synchronously with the first clock signal is collected using the set first clock signal sent by the received SOC module through the MAC module and the receiving clock delay duration in the configuration data of the PHY chip to obtain a second data packet; wherein the second data packet is used by the SOC module to detect the receiving clock delay duration of the PHY chip based on the comparison result of the first data packet and the second data packet;

[0016] And / or, in response to the data transmission mode being configured as the sending mode, a fourth data packet and the second clock signal of the PHY chip are synchronously sent to the MAC module; wherein the second clock signal is used by the MAC module to collect the fourth data packet sent synchronously with the second clock signal according to the second clock signal and the sending clock delay duration of the PHY chip carried by the second clock signal, to obtain a third data packet; wherein the third data packet is used by the SOC module to detect the sending clock delay duration of the PHY chip based on the comparison result of the third data packet and the fourth data packet.

[0017] Another aspect of the present application provides a debugging device for an Ethernet PHY chip, including:

[0018] a configuration module, configured to configure a data transmission mode of the PHY chip to be debugged based on address information of a target register of the PHY chip to be debugged when determining that the connection state of the status register of the PHY chip to be debugged is connected;

[0019] a sending module, configured to synchronously send a set first clock signal and a first data packet to the PHY chip through a MAC module in response to the data transmission mode being a receiving mode; wherein the first clock signal is used by the PHY chip in the receiving mode to collect the first data packet sent synchronously with the first clock signal according to the first clock signal and the receiving clock delay time in the configuration data of the PHY chip to obtain a second data packet;

[0020] A first acquisition module, used to acquire a second data packet collected by the PHY chip;

[0021] A first detection module, configured to detect a delay duration of a receiving clock of the PHY chip based on a comparison result of the first data packet and the second data packet;

[0022] And / or, a second acquisition module, configured to acquire a third data packet collected by the MAC module in response to the data transmission mode being a sending mode; wherein the third data packet is obtained by the MAC module receiving the second clock signal and the fourth data packet synchronously sent by the PHY chip, and collecting the fourth data packet sent synchronously with the second clock signal according to the second clock signal and the sending clock delay time of the PHY chip carried by the second clock signal;

[0023] A third acquisition module, used to acquire a fourth data packet sent by the PHY chip;

[0024] The second detection module is used to detect the delay duration of the sending clock of the PHY chip based on the comparison result of the third data packet and the fourth data packet.

[0025] Another aspect of the present application provides a debugging device for an Ethernet PHY chip, including:

[0026] A determination module, used to determine that the connection state of the status register of the PHY chip to be debugged is connected, and to determine the data transmission mode of the PHY chip; wherein the data transmission mode is obtained by configuring the PHY chip by the SOC based on the address information of the target register of the PHY chip to be debugged obtained;

[0027] A processing module, configured to, in response to the data transmission mode of the PHY chip to be debugged being configured as a receiving mode, collect a first data packet sent synchronously with the first clock signal using a set first clock signal sent by the received SOC module through the MAC module and a receiving clock delay duration in the configuration data of the PHY chip to obtain a second data packet; wherein the second data packet is used by the SOC module to detect the receiving clock delay duration of the PHY chip based on a comparison result of the first data packet and the second data packet;

[0028] And / or, the processing module is also used to synchronously send a fourth data packet and the second clock signal of the PHY chip to the MAC module in response to the data transmission mode being configured as a sending mode; wherein the second clock signal is used by the MAC module to collect the fourth data packet sent synchronously with the second clock signal according to the second clock signal and the sending clock delay duration of the PHY chip carried by the second clock signal, to obtain a third data packet; wherein the third data packet is used by the SOC module to detect the sending clock delay duration of the PHY chip based on the comparison result of the third data packet and the fourth data packet.

[0029] Another aspect of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method described in the first aspect or the second aspect is implemented.

[0030] Another aspect of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method described in the first aspect or the method described in the second aspect is implemented.

[0031] Another aspect of the present application provides a computer program product on which a computer program is stored. When the program is executed by a processor, the method described in the first aspect or the second aspect is implemented.

[0032] The debugging method, device, electronic device and medium of the Ethernet PHY chip proposed in the present application, when determining that the connection state of the status register of the PHY chip to be debugged is connected, configure the data transmission mode of the PHY chip based on the address information of the target register of the PHY chip to be debugged, in response to the data transmission mode being the receiving mode, synchronously send a set first clock signal and a first data packet to the PHY chip through the MAC module, obtain a second data packet collected by the PHY chip, and detect the receiving clock delay duration of the PHY chip based on the comparison result of the first data packet and the second data packet; and / or, in response to the data transmission mode being the sending mode, obtain a third data packet collected by the MAC module, obtain a fourth data packet, and detect the sending clock delay duration of the PHY chip based on the comparison result of the third data packet and the fourth data packet. The present application sets a SOC module in the FPGA, so that for different PHY chips, the SOC can configure the data transmission mode of the PHY chip according to the address information of the target register of the PHY chip obtained, so as to test the receiving clock delay time and / or sending clock delay time of different PHY chips. Compared with the related art of testing different PHY chips, it is necessary to recompile all the codes in the FPGA, which reduces the difficulty and improves the debugging efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0034] Figure 1 A flowchart of another method for debugging an Ethernet PHY chip provided in an embodiment of the present application;

[0035] Figure 2 A flowchart of another method for debugging an Ethernet PHY chip provided in an embodiment of the present application;

[0036] Figure 3 A schematic diagram of a debugging structure of an Ethernet PHY chip provided in an embodiment of the present application;

[0037] Figure 4 A flowchart of another method for debugging an Ethernet PHY chip provided in an embodiment of the present application;

[0038] Figure 5 A schematic diagram of a debugging structure of another Ethernet PHY chip provided in an embodiment of the present application;

[0039] Figure 6 A flowchart of a debugging method for an Ethernet PHY chip provided in an embodiment of the present application;

[0040] Figure 7 A schematic diagram of a debugging structure of another Ethernet PHY chip provided in an embodiment of the present application;

[0041] Figure 8 A flowchart of a debugging method for an Ethernet PHY chip provided in an embodiment of the present application;

[0042] Fig. 9 A schematic diagram of the structure of a debugging device for an Ethernet PHY chip provided in an embodiment of the present application;

[0043] Fig.10 A schematic diagram of the structure of a debugging device for an Ethernet PHY chip provided in an embodiment of the present application;

[0044] Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0046] The following describes the Ethernet PHY chip debugging method, device, electronic device and medium of the embodiments of the present application with reference to the accompanying drawings.

[0047] Figure 1 A flowchart of a debugging method for an Ethernet PHY chip provided in an embodiment of the present application.

[0048] The execution subject of the embodiment of the present application is a system on chip (SOC) module in FPGA. As an implementation method, a field programmable gate array (FPGA) includes two online programming interfaces (Joint Test Action Group, JTAG), called JTAG1 and JTAG2. Among them, JTAG2: is used to connect the computer PC and the SOC circuit, and generate the SOC module based on EDA software, including configuring the operating frequency, external cache size, external bus interface and base address information of the SOC module, etc. Among them, the debugging logic for debugging the PHY chip is set in the SOC module. The debugging logic is implemented based on C code, with low development difficulty and modification difficulty. To adapt to the debugging of different PHY chips, only part of the code needs to be modified, which improves reusability. Among them, the code in the SOC module will be downloaded to the FPGA and become an online debugging tool. For different PHY chips, only the relevant parameters in the SOC module need to be modified. Compared with the related technology, modifying the debugging parameters requires updating all the codes based on the hardware description language Verilog in the Media Access Control layer protocol (Media Access Control, MAC) module in the FPGA, and generating a BIT file to complete the code update, which reduces the development work on the FPGA, reduces the workload in the MAC module, and improves the debugging efficiency.

[0049] like Figure 1 As shown, the method comprises the following steps:

[0050] Step 101: When it is determined that the connection state of the status register of the PHY chip to be debugged is connected, the data transmission mode of the PHY chip to be debugged is configured based on the address information of the target register of the PHY chip to be debugged.

[0051] In an embodiment of the present application, when it is determined that the connection state of the status register of the PHY chip is connected, that is, the FPGA and the PHY chip are in a connected state, the data transmission mode of the PHY chip is configured, wherein the data transmission mode includes a sending mode and a receiving mode.

[0052] In one implementation of the embodiment of the present application, C language code is run in the SOC module, which is more flexible and configurable. The code in the SOC can be pre-generated according to the type of the PHY chip to be debugged and downloaded to the SOC. The downloaded code includes the address information of the registers of each configured PHY chip. In the case of different PHY chips to be detected or different registers of the PHY chip, the address information of the target register of the Ethernet physical layer PHY chip to be detected can be determined from the pre-stored address information of the registers of each PHY chip based on the selection instruction sent by the user through the button or the screen operation.

[0053] In another implementation of the embodiment of the present application, since there are many types of PHY chips, it is impossible to build in the address information of the registers of all PHY chips. Since the code in the SOC is easy to change, the address information of the registers of the PHY chip to be debugged can be obtained by updating the code in the SOC to adapt to different PHY chips.

[0054] Among them, the data transmission mode of the PHY chip is configured. As an implementation method, the address information of the target register of the PHY chip to be debugged and the identifier of the data transmission mode are obtained, wherein the target register refers to a register in the PHY chip used to configure the data transmission mode of the PHY chip. The address information of the target register of the PHY chip to be debugged and the identifier of the data transmission mode are converted into data recognizable by the protocol of the PHY chip through the MAC module, and then the identifier of the data transmission mode recognizable by the PHY chip is sent to the target register of the PHY chip corresponding to the address information, so that the target register of the PHY chip sets the data transmission mode of the PHY chip according to the identifier of the data transmission mode.

[0055] Step 102, in response to the data transmission mode being the receiving mode, synchronously sending a set first clock signal and a first data packet to the PHY chip through the MAC module, obtaining a second data packet collected by the PHY chip, and detecting the receiving clock delay duration of the PHY chip based on a comparison result of the first data packet and the second data packet, and / or, in response to the data transmission mode being the sending mode, obtaining a third data packet collected by the MAC module, obtaining a fourth data packet collected by the PHY chip, and detecting the sending clock delay duration of the PHY chip based on a comparison result of the third data packet and the fourth data packet.

[0056] In one implementation of the embodiment of the present application, in response to the data transmission mode of the PHY chip being the receiving mode, that is, the data transmission mode of the FPGA is the packet sending mode, the SOC module controls the packet sending module in the FPGA chip to generate a data packet and sends it to the PHY chip. At the same time, a set first clock signal is synchronously sent to the PHY chip, which is called the first data packet to distinguish it from subsequent data packets. The first data packet can be a UDP (User Datagram Protocol) packet, a TCP (Transmission Control Protocol) packet, an ARP (Address Resolution Protocol) packet of the address resolution protocol, etc., that is, the protocol corresponding to the first data packet is not limited in the embodiment of the present application.

[0057] In another implementation of the embodiment of the present application, the FPGA includes a MAC module, namely, a MAC IP. In the receiving mode of the PHY chip, the SOC module controls the packet sending module to generate a first data packet and sends the first data packet to the MAC module. The MAC module is used to send the first data packet and the set clock signal to the PHY chip synchronously, wherein the set clock signal can be the clock signal of the MAC module. The first clock signal is used for the PHY chip in the receiving mode to collect the first data packet sent synchronously with the first clock signal according to the first clock signal and the receiving clock delay time in the configuration data of the PHY chip to obtain the second data packet. In the related art, the rising edge of the clock signal is usually used to trigger the receiving end to collect the signal. In the present application, in order to improve the accuracy of receiving the data in the first data packet, the configuration data of the PHY chip includes the receiving clock delay time. Through the receiving clock delay time set in the PHY chip, when the rising edge of the receiving clock arrives, data is not collected, but a time delay is performed based on the rising edge, that is, the receiving clock delay time is delayed backward on the basis of the set collection time point of the rising edge, and then the first data packet is collected. The receiving clock delay time is used to realize data collection when the first data packet is stable, and a second data packet is obtained, wherein the second data packet may be the same as the first data packet, or the second data packet may be different from the first data packet due to an error in the collection.

[0058] For example, the receiving delay of the PHY chip is 10ms, and the sampling time corresponding to the rising edge of the first clock is t1. Then, the PHY chip starts to collect data of the first data packet to obtain data of the second data packet after a shift of 10ms from t1, thereby improving the accuracy of receiving data in the first data packet.

[0059] It should be understood that the configuration data of the PHY chip includes the configured receive clock delay duration of the PHY chip. As an implementation method, the SOC module transmits the configuration data of each register of the PHY chip to the MAC module through the axi_lite interface. The MAC module converts the configuration data of each register of the PHY chip to MDIO (Management Data Input / Output) through the conversion interface to send the configuration data of each register of the PHY chip to the PHY chip, so that the PHY chip can be debugged.

[0060] It is important to understand that the SOC module exchanges data with the MAC through the AXI or APB interface. Since the MAC IP has built-in AXI-lite and MIIM interface conversion logic to facilitate access to the registers that configure the PHY, it is necessary to convert the AXI or APB interface to the AXI-lite interface.

[0061] Step 103: Acquire a second data packet collected by the PHY chip.

[0062] In one implementation of the embodiment of the present application, the PHY chip can be connected to a computer, and the second data packet collected by the PHY chip can be sent to the computer. The second data packet collected by the PHY chip can be captured from the computer through the packet capture tool wirkshark, and then the second data packet captured by the packet capture tool is provided to the SOC module.

[0063] In another implementation of the embodiment of the present application, the data packet of the PHY chip can be stored in its own register or in an external storage unit, so that the second data packet can be obtained from the memory in the PHY chip or from an external storage unit used to store the PHY chip.

[0064] In another implementation of the embodiment of the present application, the second data packet stored in the status register of the PHY is read by driving the serial port information to obtain the second data packet.

[0065] Step 104: Based on the comparison result of the first data packet and the second data packet, the delay time of the receiving clock of the PHY chip is detected.

[0066] In an embodiment of the present application, the first data packet and the second data packet are compared. When it is determined that the first data packet and the second data packet match, as an implementation method, the match means that the overlap of the data in the first data packet and the second data packet is greater than a set threshold value, and the set threshold value is, for example, 98%. It is determined that the received second data packet is accurate, thereby determining that the receiving clock delay time is set correctly and does not need to be reconfigured; if the received second data packet does not match the sent first data packet, it means that the receiving clock delay time is set incorrectly and needs to be reconfigured. By debugging the receiving clock delay time in the receiving mode of the PHY chip, the receiving clock delay time of the PHY chip can be detected, and a debugging method is provided. At the same time, the debugging method is simple and the debugging efficiency is high.

[0067] Step 105: In response to the data transmission mode being the sending mode, a third data packet collected by the MAC module is acquired.

[0068] Among them, the third data packet is obtained by collecting the fourth data packet sent synchronously with the second clock signal and the fourth data packet sent synchronously by the PHY chip when the MAC module receives the second clock signal and the fourth data packet sent synchronously with the second clock signal according to the second clock signal and the sending clock delay duration of the PHY chip carried by the second clock signal.

[0069] For example, after receiving the second clock signal of the PHY chip, the MAC module determines that the delay time is 10ms, and the sampling time corresponding to the rising edge of the second clock is t1. Then, MAC starts collecting data of the fourth data packet after a shift of 10ms from t1, so as to realize data collection in a stable data state, thereby improving the accuracy of data reception in the fourth data packet.

[0070] The fourth data packet may be the second data packet in the above embodiment. Alternatively, the fourth data packet is obtained by the PHY chip from the PC end, and the fourth data packet on the PC end is generated by an external packet sending tool and sent to the PC.

[0071] The second clock signal carries the delay duration of the sending clock of the PHY chip.

[0072] In the embodiment of the present application, the PHY chip is configured in the sending mode, and the fourth data packet for testing is sent by the PHY chip. As an implementation method, Figure 5As shown, the FPGA includes a MAC module. In the sending mode, the PHY chip sends the third data packet obtained by the PHY chip and the second clock signal to the MAC module synchronously. The MAC module collects the third data packet sent synchronously with the second clock signal according to the second clock signal and the delay time of the sending clock of the PHY chip carried by the second clock signal to obtain a fourth data packet. The capture module captures the third data packet received by the MAC from the MAC module and sends the third data packet to the SOC module.

[0073] As an implementation method, the capture module is used to obtain the fourth data packet currently received by the MAC module and store the fourth data packet in a setting storage unit. The setting storage unit can be in the capture module or in the FPGA chip. If the setting storage unit is a storage unit in the capture module, the SOC module obtains the fourth data packet currently received by the MAC module from the storage unit in the capture module. If the setting storage unit is a storage unit in the FPGA chip, the SOC module obtains the fourth data packet currently received by the MAC module from the storage unit in the FPGA chip.

[0074] Step 106: Acquire a fourth data packet sent by the PHY chip.

[0075] In one implementation of the embodiment of the present application, the fourth data packet sent by the PHY chip is obtained from the PC, and the fourth data packet on the PC is generated by an external packet sending tool and sent to the PC. The fourth data packet can be captured from the computer by the packet capture tool wirkshark, and then the fourth data packet captured by the packet capture tool is provided to the SOC module.

[0076] In another implementation of the embodiment of the present application, the data packet of the PHY chip can be stored in its own register or in an external storage unit, so that the fourth data packet can be obtained from the memory in the PHY chip or from an external storage unit used to store the PHY chip.

[0077] In another implementation of the embodiment of the present application, the fourth data packet stored in the status register of the PHY is read by driving the serial port information to obtain the fourth data packet.

[0078] Step 107: Based on the comparison result of the fourth data packet and the third data packet, detect the delay time of the sending clock of the PHY chip.

[0079] In one implementation of the embodiment of the present application, the fourth data packet is compared with the third data packet, and in response to the fourth data packet not matching the third data packet, it is determined that the sending clock delay time length of the PHY chip is set incorrectly; in response to the fourth data packet matching the third data packet, it is determined that the sending clock delay time length of the PHY chip is set accurately. Specifically, the method for determining whether the receiving clock delay time length of the PHY chip is set correctly in the aforementioned embodiment can be referred to, and the principle is similar, and is not limited in this embodiment.

[0080] It should be noted that step 102 to step 104 and step 105 to step 107 are in an and / or relationship. As a first implementation, step 102 to step 104 may be performed to detect the delay time of the receiving clock of the PHY chip.

[0081] As a second implementation, steps 105 to 107 may be performed to detect the delay time of the sending clock of the PHY chip;

[0082] As a third implementation, steps 102 to 104 may be performed first, and then steps 105 to 107 may be performed to detect the delay time of the receiving clock and the delay time of the sending clock of the PHY chip.

[0083] As a fourth implementation, steps 105 to 107 may be performed first, and then steps 102 to 104 may be performed to detect the delay time of the sending clock and the delay time of the receiving clock of the PHY chip.

[0084] The specific detection process can refer to the explanations in the aforementioned steps. The principles are the same and will not be repeated here.

[0085] In the debugging method of the Ethernet PHY chip of the embodiment of the present application, when it is determined that the connection state of the status register of the PHY chip to be debugged is connected, the data transmission mode of the PHY chip is configured based on the address information of the target register of the PHY chip to be debugged, and in response to the data transmission mode being the receiving mode, a set first clock signal and a first data packet are synchronously sent to the PHY chip through the MAC module, and a second data packet collected by the PHY chip is obtained. Based on the comparison result of the first data packet and the second data packet, the receiving clock delay duration of the PHY chip is detected; and / or, in response to the data transmission mode being the sending mode, a third data packet collected by the MAC module is obtained, a fourth data packet is obtained, and based on the comparison result of the third data packet and the fourth data packet, the sending clock delay duration of the PHY chip is detected. The present application sets a SOC module in the FPGA, so that for different PHY chips, the SOC can configure the data transmission mode of the PHY chip according to the address information of the target register of the PHY chip obtained, so as to test the receiving clock delay time and / or sending clock delay time of different PHY chips. Compared with the related art of testing different PHY chips, it is necessary to recompile all the codes in the FPGA, which reduces the difficulty and improves the debugging efficiency.

[0086] Based on the above embodiments, Figure 2 A flowchart of another method for debugging an Ethernet PHY chip provided in an embodiment of the present application is provided. The present application describes the detection of the delay duration of the receiving clock of the PHY chip in the PHY chip receiving scenario. Figure 2 As shown, the method comprises the following steps:

[0087] Step 201: Send a read instruction for reading the connection status to the MAC module.

[0088] As an example, Figure 3 A schematic diagram of a debugging structure of an Ethernet PHY chip provided in an embodiment of the present application, wherein the FPGA also includes a MAC module, combined with Figure 3 The method of the embodiment of the present application is described.

[0089] Among them, the read instruction is used for the MAC module to read the connection status of the status register of the PHY chip according to the read instruction, and send it to the SOC module. The SOC module determines whether the connection status of the status register of the PHY chip is a connected state or an unconnected state based on the identification information of the acquired connection status. When the connection status is connected, the receiving clock delay duration of the PHY chip is tested, and it can be determined that the data reception abnormality is caused by the incorrect setting of the receiving clock delay duration of the PHY chip. When the connection status is non-connectable or abnormal, the abnormal connection status itself will cause errors in the received data, and it is impossible to identify whether the data reception abnormality is caused by the inaccurate setting of the receiving clock delay duration of the PHY chip.

[0090] Step 202: When it is determined that the connection state of the status register of the PHY chip to be debugged is connected, configure the data transmission mode of the PHY chip based on the address information of the target register of the PHY chip to be debugged.

[0091] Step 203: In response to the data transmission mode being the receiving mode, synchronously sending a set first clock signal and a first data packet to the PHY chip through the MAC module.

[0092] In one implementation of the embodiment of the present application, in response to the data transmission mode being the receiving mode, such as Figure 3 As shown, the SOC module sends an enable signal to the packet sending module, and the packet sending module generates a first data packet under the triggering of the enable signal, and sends the first data packet to the MAC module, and then sends the first data packet and the set first clock signal to the PHY chip through the MAC module.

[0093] Step 204: Acquire a second data packet collected by the PHY chip.

[0094] Among them, step 202 to step 204 can refer to the explanation in the above-mentioned embodiment, and the principle is the same, which will not be repeated here.

[0095] Step 205: compare the first data packet and the second data packet.

[0096] Among them, the first data packet is generated by the packet assembly module in the FPGA. The packet assembly module can be built into the SOC module or independent of the SOC module. For example, the first data packet can be a UDP data packet carrying test data to be sent to the PHY chip. The second data packet is obtained by collecting the first data packet sent synchronously with the first clock signal based on the received first clock signal and the receiving clock delay time in its own configuration data when the data transmission mode of the PHY chip is the receiving mode. Therefore, the second data packet may be the same as or different from the first data packet.

[0097] Compare the data in the first data packet and the data in the second data packet. As an implementation method, if the data in the first data packet and the data in the second data packet are the same, it is considered that the first data includes and matches the data in the second data packet. If the data in the first data packet and the data in the second data packet are not the same, that is, there is a difference, it is considered that the first data includes and does not match the data in the second data packet.

[0098] As a second implementation, in order to improve the error tolerance of received data, if the same portion of data in the first data packet and data in the second data packet is greater than a set threshold, the data in the first data packet and the second data packet are considered to match; on the contrary, if the same portion of data in the first data packet and data in the second data packet is less than or equal to the set threshold, the data in the first data packet and the second data packet are considered to not match. The set threshold can be set based on the accuracy requirement and is not limited in the embodiments of the present application.

[0099] Step 206: In response to the data matching between the first data packet and the second data packet, determine that the receiving clock delay duration is set correctly.

[0100] In the embodiment of the present application, if the data of the first data packet and the second data packet match, it means that the receiving clock delay duration currently configured by the PHY chip is relatively accurate, and the data received by the data receiver and the data sent by the sender meet the receiving requirements, then it is determined that the receiving clock delay duration is set correctly, and further, there is no need to reconfigure the receiving clock delay duration of the PHY chip.

[0101] Step 207: In response to determining that the first data packet and the second data packet do not match, determining that the reception clock delay duration is incorrectly set.

[0102] In an embodiment of the present application, if the data of the first data packet and the second data packet do not match, it means that the receiving clock delay duration currently configured by the PHY chip is inaccurate. As the data received by the data receiver and the data sent by the sender are quite different, it is determined that the receiving clock delay duration is incorrectly set. Furthermore, it is necessary to reconfigure the receiving clock delay duration of the PHY chip to improve the accuracy of data reception.

[0103] When it is determined that the first data packet and the second data packet do not match, it is determined that the receiving clock delay duration is abnormally set, so that an early warning can be issued to remind that the receiving clock delay duration needs to be reset. As an implementation method, the receiving clock delay duration of the PHY chip can be modified through the SOC module according to the difference between the data of the received second data packet and the data of the first data packet. Specifically, the receiving clock delay duration of the PHY chip in the SOC module is adjusted, and the adjusted receiving clock delay duration of the PHY chip and the address information of the corresponding PHY chip to be debugged are sent to the MAC module. The MAC module sends the receiving clock delay duration corresponding to the PHY chip to the PHY chip according to the address information of the PHY chip, thereby reconfiguring the receiving clock delay duration of the PHY chip.

[0104] It should be understood that MAC is the transfer station for SOC module and PHY chip data.

[0105] In the debugging method of the Ethernet PHY chip of the embodiment of the present application, when it is determined that the connection state of the status register of the PHY chip to be debugged is connected, the data transmission mode of the PHY chip is configured through the SOC module set in the FPGA, that is, the setting of the packet sending method is realized, and then, the data in the acquired second data packet is compared with the data in the first data packet, and in response to the data matching of the first data packet and the second data packet, it is determined that the setting of the receiving clock delay duration is correct, and in response to determining that the first data packet and the second data packet do not match, it is determined that the setting of the receiving clock delay duration is incorrect, so that the receiving clock delay duration of the PHY chip can be debugged. For different PHY chips, it is only necessary to set the data transmission mode of the PHY chip through the SOC module to debug the clock-related information configured in the PHY chip, and the debugging efficiency is high.

[0106] Based on the above embodiments, in the previous embodiments, the PHY chip is configured in the receiving mode to debug the receiving clock delay duration of the PHY chip. In the implementation of the present application, the PHY chip is configured in the sending mode to debug the sending clock delay duration of the PHY chip. Figure 4 A flowchart of another method for debugging an Ethernet PHY chip provided in an embodiment of the present application is shown as follows: Figure 4 As shown, the method comprises the following steps:

[0107] Step 401: Send a read instruction for reading the connection status to the MAC module.

[0108] Step 402: When it is determined that the connection state of the status register of the PHY chip to be debugged is connected, configure the data transmission mode of the PHY chip based on the address information of the target register of the PHY chip to be debugged.

[0109] Among them, steps 401 and 402 can refer to the explanations in the aforementioned embodiments, and the principles are the same, so they will not be repeated here.

[0110] Step 403: In response to the data transmission mode being the sending mode, a third data packet collected by the MAC module is acquired.

[0111] Among them, the third data packet is obtained by collecting the fourth data packet sent synchronously with the second clock signal and the fourth data packet sent synchronously by the PHY chip when the MAC module receives the second clock signal and the fourth data packet sent synchronously with the second clock signal according to the second clock signal and the sending clock delay duration of the PHY chip carried by the second clock signal.

[0112] For example, after receiving the second clock signal of the PHY chip, the MAC module determines that the delay time is 10ms, and the sampling time corresponding to the rising edge of the second clock is t1. Then, MAC starts collecting data of the fourth data packet after a shift of 10ms from t1, so as to realize data collection in a stable data state, thereby improving the accuracy of data reception in the fourth data packet.

[0113] The fourth data packet may be the second data packet in the above embodiment. Alternatively, the fourth data packet is obtained by the PHY chip from the PC end, and the fourth data packet on the PC end is generated by an external packet sending tool and sent to the PC.

[0114] The second clock signal carries the delay duration of the sending clock of the PHY chip.

[0115] In the embodiment of the present application, the PHY chip is configured in the sending mode, and the fourth data packet for testing is sent by the PHY chip. As an implementation method, Figure 5 As shown, the FPGA includes a MAC module. In the sending mode, the PHY chip sends the third data packet obtained by the PHY chip and the second clock signal to the MAC module synchronously. The MAC module collects the third data packet sent synchronously with the second clock signal according to the second clock signal and the delay time of the sending clock of the PHY chip carried by the second clock signal to obtain a fourth data packet. The capture module captures the third data packet received by the MAC from the MAC module and sends the third data packet to the SOC module.

[0116] As an implementation method, the capture module is used to obtain the fourth data packet currently received by the MAC module and store the fourth data packet in a setting storage unit. The setting storage unit can be in the capture module or in the FPGA chip. If the setting storage unit is a storage unit in the capture module, the SOC module obtains the fourth data packet currently received by the MAC module from the storage unit in the capture module. If the setting storage unit is a storage unit in the FPGA chip, the SOC module obtains the fourth data packet currently received by the MAC module from the storage unit in the FPGA chip.

[0117] Step 404: Acquire a fourth data packet sent by the PHY chip.

[0118] In one implementation of the embodiment of the present application, the fourth data packet sent by the PHY chip is obtained from the PC, and the fourth data packet on the PC is generated by an external packet sending tool and sent to the PC. The fourth data packet can be captured from the computer by the packet capture tool wirkshark, and then the fourth data packet captured by the packet capture tool is provided to the SOC module.

[0119] In another implementation of the embodiment of the present application, the data packet of the PHY chip can be stored in its own register or in an external storage unit, so that the fourth data packet can be obtained from the memory in the PHY chip or from an external storage unit used to store the PHY chip.

[0120] In another implementation of the embodiment of the present application, the fourth data packet stored in the status register of the PHY is read by driving the serial port information to obtain the fourth data packet.

[0121] Step 405: Based on the comparison result of the fourth data packet and the third data packet, the delay time of the sending clock of the PHY chip is detected.

[0122] In one implementation of the embodiment of the present application, the fourth data packet is compared with the third data packet, and in response to the fourth data packet not matching the third data packet, it is determined that the sending clock delay time length of the PHY chip is set incorrectly; in response to the fourth data packet matching the third data packet, it is determined that the sending clock delay time length of the PHY chip is set accurately. Specifically, the method for determining whether the receiving clock delay time length of the PHY chip is set correctly in the aforementioned embodiment can be referred to, and the principle is similar, and is not limited in this embodiment.

[0123] In the debugging method of the Ethernet PHY chip of the embodiment of the present application, when it is determined that the connection state of the status register of the PHY chip to be debugged is connected, the data transmission mode of the PHY chip is configured through the SOC module set in the FPGA, that is, the setting of the packet sending method is realized, and then, the data in the acquired third data packet and the fourth data packet are compared, in response to the data matching of the third data packet and the fourth data packet, it is determined that the setting of the sending clock delay duration is correct, and in response to determining that the fourth data packet does not match the third data packet, it is determined that the setting of the sending clock delay duration is incorrect, so that the sending clock delay duration of the PHY chip can be debugged. For different PHY chips, it is only necessary to set the data transmission mode of the PHY chip through the SOC module to debug the clock-related information configured in the PHY chip, and the debugging efficiency is high.

[0124] Based on the above embodiments, the above embodiments illustrate how to debug the receiving clock delay and sending clock delay of the PHY chip separately. In the embodiments of the present application, when it is determined that the receiving clock delay is set correctly, the sending clock delay is detected, so that the receiving clock delay of the PHY chip is first detected in the receiving mode, and then the sending clock delay of the PHY chip is detected in the sending mode, which is equivalent to performing a loopback test on the reception and transmission of the PHY chip, thereby improving the reliability of the PHY chip in sending and receiving data.

[0125] Figure 6 A flowchart of another method for debugging an Ethernet PHY chip provided in an embodiment of the present application is shown as follows: Figure 6 As shown, the method comprises the following steps:

[0126] Step 601: Send a read instruction for reading the connection status to the MAC module.

[0127] Step 602: When it is determined that the connection state of the status register of the PHY chip to be debugged is connected, configure the data transmission mode of the PHY chip based on the address information of the target register of the PHY chip to be debugged.

[0128] Step 603: In response to the data transmission mode being the receiving mode, the MAC module synchronously sends a set first clock signal and a first data packet to the PHY chip.

[0129] Step 604: Acquire a second data packet collected by the PHY chip.

[0130] Step 605: Based on the comparison result of the first data packet and the second data packet, determine whether the receiving clock delay duration is set correctly.

[0131] Step 606: configure the data transmission mode of the PHY chip to the sending mode.

[0132] Step 607: Acquire the third data packet collected by the MAC module and the fourth data packet sent by the PHY.

[0133] In this scenario, the fourth data packet sent by the PHY is the second data packet collected by the PHY chip.

[0134] Step 608: Based on the comparison result of the third data packet and the fourth data packet, the delay time of the sending clock of the PHY chip is detected.

[0135] The explanations in the aforementioned embodiments are also applicable to steps 601 to 608, and the principles are the same, which will not be described again here.

[0136] In the debugging method of the Ethernet PHY chip of the embodiment of the present application, when it is determined that the receiving clock delay duration is set correctly, the sending clock delay duration is detected, thereby realizing the detection of the receiving clock delay duration of the PHY chip in the receiving mode and the sending clock delay duration in the sending mode, which is equivalent to performing a loopback test on the reception and transmission of the PHY chip, thereby improving the reliability of the PHY chip in sending and receiving data.

[0137] It should be noted that in order to improve efficiency, when the receiving clock delay time is determined to be correct and the sending clock delay time is set correctly, Figure 7 As shown, the data transmission mode of the PHY chip can also be directly set to the loopback mode, that is, after the PHY chip receives the data sent from the FPGA, it sends the received data back to the FPGA. Finally, the SOC module in the FPGA further determines whether the receiving clock delay time and the sending clock delay time of the PHY chip are set correctly by comparing the difference between the data sent to the PHY chip and the data sent back by the PHY chip, thereby improving the debugging efficiency of the PHY by setting different packet sending methods and PHY working modes. At the same time, the transmission path between the FPGA chip and the PHY chip is tested uplink and downlink, which realizes the complete test of the transmission path and improves the reliability of the PHY chip test. Among them, the relevant explanations in the aforementioned embodiments are also applicable to this embodiment, and the principles are the same, which will not be repeated here.

[0138] It should be understood that the sending clock delay duration of the PHY chip is first detected in the sending mode, and then the receiving clock delay duration of the PHY chip is detected in the receiving mode, so as to perform a loopback test on the sending and receiving of the PHY chip. The above-mentioned loopback measurement method can be referred to, and the principle is the same, which will not be repeated here.

[0139] As an implementation method, the parameter M of the data transmission mode can be maintained in the SOC module, and the value of the parameter M can be set to different values ​​to indicate that the PHY chip is in different data transmission modes. For example, when the M value is 00, the data transmission mode of the PHY chip is the sending mode; when the M value is 01, the data transmission mode of the PHY chip is the receiving mode; when the M value is 10, the data transmission mode of the PHY chip is the sending and receiving mode, or the loopback mode. The loopback mode is set in the PHY chip so that after receiving the data packet sent by the MAC module, the PHY chip will forward the data packet back, thereby realizing the transmission loopback of the data in the PHY chip. In the related art, the loopback mode is set in the FPGA chip, which requires two MAC modules to be set in the FPGA chip, and a first-in-first-out memory is also required to cooperate with the MAC module to realize the loopback. The loopback method is complicated and increases the hardware cost. In the embodiment of the present application, the mode of the PHY chip is set to the loopback mode, which does not increase the hardware cost and is simple to implement. Through the loopback test, a complete test of the transmission path is realized, and the reliability of the PHY chip test is also improved.

[0140] Based on the above embodiment, in one implementation of the embodiment of the present application:

[0141] The SOC module is also used to issue an abnormal warning when it is determined that the connection state is not connected, prompting the need to check the hardware circuit. When it is determined that the hardware circuit is normal, the configuration data of the status register of the PHY chip is re-acquired, and the configuration data of the status register of the PHY chip is sent to the MAC module through the setting interface. The MAC module is also used to send the received configuration information of the status register of the PHY chip to the PHY chip, so that the PHY chip writes it into the status register to achieve reconfiguration of the status register of the PHY chip, so that after the FPGA chip and the PHY chip are connected, the connection state of the PHY chip is the connection LINK state, which is convenient for subsequent transmission path testing.

[0142] Based on the above embodiments, Figure 7 A flowchart of a debugging method for an Ethernet PHY chip provided in an embodiment of the present application is provided, which is applied to an Ethernet PHY chip, such as Figure 7 As shown, the method includes:

[0143] Step 701, determining that the connection state of the status register of the PHY chip to be debugged is connected, and determining the data transmission mode of the PHY chip.

[0144] The data transmission mode is obtained by configuring the PHY chip based on the address information of the target register of the PHY chip to be debugged obtained by the SOC. Please refer to the explanation in the above embodiment for details. The principle is the same and will not be repeated here.

[0145] As an implementation manner, the status register of the PHY chip has a different value of a status flag in a connected state. For example, in a connected state, the value of the status flag is 1, and in a disconnected state, the value of the status flag is 0.

[0146] Step 702, in response to the data transmission mode of the PHY chip to be debugged being configured as a receiving mode, the first data packet sent synchronously with the first clock signal is collected to obtain a second data packet using the set first clock signal sent by the received SOC module through the MAC module and the receiving clock delay duration in the configuration data of the PHY chip.

[0147] The second data packet is used by the SOC module to detect the delay duration of the receiving clock of the PHY chip based on the comparison result of the first data packet and the second data packet.

[0148] The explanations and beneficial effects in the above embodiments are also applicable to the method of this embodiment, and the principles are the same, so they will not be repeated here.

[0149] Step 703: In response to the data transmission mode being configured as the sending mode, synchronously sending a fourth data packet and a second clock signal of the PHY chip to the MAC module.

[0150] Among them, the second clock signal is used by the MAC module to collect the fourth data packet sent synchronously with the second clock signal to obtain a third data packet according to the sending clock delay duration of the PHY chip carried by the second clock signal and the second clock signal; wherein the third data packet is used by the SOC module to detect the sending clock delay duration of the PHY chip based on the comparison result of the third data packet and the fourth data packet.

[0151] The explanations and beneficial effects in the above embodiments are also applicable to the method of this embodiment, and the principles are the same, so they will not be repeated here.

[0152] In order to implement the above embodiments, the present application also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method described in the above method embodiments is implemented.

[0153] In order to implement the above embodiments, the present application also proposes a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the method described in the above method embodiments is implemented.

[0154] In order to implement the above embodiments, the present application also proposes a computer program product on which a computer program is stored. When the computer program is executed by a processor, the method described in the above method embodiments is implemented.

[0155] Based on the above embodiments, the embodiments of the present application also provide a debugging device for an Ethernet PHY chip.

[0156] Fig. 9 A schematic diagram of the structure of a debugging device for an Ethernet PHY chip provided in an embodiment of the present application is shown in FIG. Fig. 9 As shown, the device comprises:

[0157] The configuration module 91 is used to configure the data transmission mode of the PHY chip to be debugged based on the address information of the target register of the PHY chip to be debugged when determining that the connection state of the status register of the PHY chip to be debugged is connected.

[0158] The sending module 92 is used to synchronously send a set first clock signal and a first data packet to the PHY chip through the MAC module in response to the data transmission mode being the receiving mode; wherein the first clock signal is used for the PHY chip in the receiving mode to collect the first data packet sent synchronously with the first clock signal to obtain a second data packet according to the first clock signal and the receiving clock delay duration in the configuration data of the PHY chip.

[0159] The first acquisition module 93 is used to acquire the second data packet collected by the PHY chip.

[0160] A first detection module 94, configured to detect a delay duration of a receiving clock of the PHY chip based on a comparison result of the first data packet and the second data packet;

[0161] And / or, a second acquisition module 95, configured to acquire a third data packet collected by the MAC module in response to the data transmission mode being the sending mode; wherein the third data packet is obtained by the MAC module receiving the second clock signal and the fourth data packet synchronously sent by the PHY chip, and collecting the fourth data packet sent synchronously with the second clock signal according to the second clock signal and the sending clock delay time of the PHY chip carried by the second clock signal;

[0162] A third acquisition module 96, configured to acquire a fourth data packet sent by the PHY chip;

[0163] The second detection module 97 is used to detect the delay duration of the sending clock of the PHY chip based on the comparison result of the third data packet and the fourth data packet.

[0164] Further, in an implementation of the embodiment of the present application, the first detection module 94 is specifically configured to:

[0165] comparing the first data packet and the second data packet;

[0166] In response to data matching between the first data packet and the second data packet, determining that the reception clock delay duration is set correctly;

[0167] In response to determining that the first data packet and the second data packet do not match, it is determined that the reception clock delay duration is set incorrectly.

[0168] In one implementation of the embodiment of the present application, the device further includes:

[0169] The setting module is used to configure the data transmission mode of the PHY chip to the sending mode in response to determining that the receiving clock delay duration is set correctly.

[0170] In one implementation of the embodiment of the present application, the second detection module 97 is further configured to:

[0171] comparing the fourth data packet with the third data packet;

[0172] In response to the fourth data packet not matching the third data packet, determining that a transmission clock delay duration of the PHY chip is set incorrectly;

[0173] In response to the fourth data packet matching the third data packet, it is determined that the sending clock delay duration of the PHY chip is set accurately.

[0174] In one implementation of the embodiment of the present application, the sending module 92 is further configured to:

[0175] A read instruction for reading the connection status is sent to the MAC module; wherein the read instruction is used by the MAC module to read the connection status of the status register of the PHY chip according to the read instruction.

[0176] The explanations in the aforementioned embodiments are also applicable to the device of this embodiment, and the principles are the same, which will not be described again here.

[0177] In the debugging device of the Ethernet PHY chip in the embodiment of the present application, when it is determined that the connection state of the status register of the PHY chip to be debugged is connected, the data transmission mode of the PHY chip is configured based on the address information of the target register of the PHY chip to be debugged, and in response to the data transmission mode being the receiving mode, a set first clock signal and a first data packet are synchronously sent to the PHY chip through the MAC module, and a second data packet collected by the PHY chip is obtained. Based on the comparison result of the first data packet and the second data packet, the receiving clock delay duration of the PHY chip is detected; and / or, in response to the data transmission mode being the sending mode, a third data packet collected by the MAC module is obtained, a fourth data packet is obtained, and based on the comparison result of the third data packet and the fourth data packet, the sending clock delay duration of the PHY chip is detected. The present application sets a SOC module in the FPGA, so that for different PHY chips, the SOC can configure the data transmission mode of the PHY chip according to the address information of the target register of the PHY chip obtained, so as to test the receiving clock delay time and / or sending clock delay time of different PHY chips. Compared with the related art of testing different PHY chips, it is necessary to recompile all the codes in the FPGA, which reduces the difficulty and improves the debugging efficiency.

[0178] Based on the above embodiments, the embodiments of the present application also provide a debugging device for an Ethernet PHY chip.

[0179] Fig.10 A schematic diagram of the structure of a debugging device for an Ethernet PHY chip provided in an embodiment of the present application is shown in FIG. Fig.10 As shown, the device comprises:

[0180] The determination module 110 is used to determine that the connection status of the status register of the PHY chip to be debugged is connected.

[0181] The processing module 112 is used for collecting a first data packet sent synchronously with the first clock signal in response to the data transmission mode of the PHY chip to be debugged being configured as a receiving mode, using the set first clock signal sent by the received SOC module through the MAC module and the receiving clock delay duration in the configuration data of the PHY chip, to obtain a second data packet; wherein the second data packet is used by the SOC module to detect the receiving clock delay duration of the PHY chip based on the comparison result of the first data packet and the second data packet.

[0182] And / or, the processing module 112 is also used to synchronously send a fourth data packet and the second clock signal of the PHY chip to the MAC module in response to the data transmission mode being configured as a sending mode; wherein the second clock signal is used by the MAC module to collect the fourth data packet sent synchronously with the second clock signal according to the second clock signal and the sending clock delay duration of the PHY chip carried by the second clock signal, to obtain a third data packet; wherein the third data packet is used by the SOC module to detect the sending clock delay duration of the PHY chip based on the comparison result of the third data packet and the fourth data packet.

[0183] The explanations and beneficial effects in the aforementioned embodiments are also applicable to the device of this embodiment, and the principles are the same, so they will not be repeated here.

[0184] In the debugging device of the Ethernet PHY chip in the embodiment of the present application, a SOC module is set in the FPGA, so that for different PHY chips, the SOC can configure the data transmission mode of the PHY chip according to the address information of the target register of the PHY chip obtained, so as to test the receiving clock delay time and / or the sending clock delay time of different PHY chips. Compared with the related art of testing different PHY chips, it is necessary to recompile all the codes in the FPGA, which reduces the difficulty and improves the debugging efficiency.

[0185] Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Fig.11 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application. The electronic device can be a terminal device or a server.

[0186] like Fig.11 As shown, the electronic device 10 includes a processor 11, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 12 or a program loaded from a memory 16 to a random access memory (RAM) 13. Various programs and data required for the operation of the electronic device 10 are also stored in the RAM 13. The processor 11, the ROM 12, and the RAM 13 are connected to each other via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0187] The following components are connected to the I / O interface 15: a memory 16 including a hard disk, etc.; and a communication part 17 including a network interface card such as a LAN (Local Area Network) card, a modem, etc., and the communication part 17 performs communication processing via a network such as the Internet; a drive 18 is also connected to the I / O interface 15 as needed.

[0188] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part 17. When the computer program is executed by the processor 11, the above-mentioned functions defined in the method of the present application are executed.

[0189] In an exemplary embodiment, a storage medium including instructions is also provided, such as a memory 16 including instructions, and the instructions can be executed by the processor 11 of the electronic device 10 to complete the above method. Optionally, the storage medium can be a non-transitory computer-readable storage medium, for example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0190] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

Claims

1. A debugging method for an Ethernet PHY chip, characterized in that: The method comprises: When it is determined that the connection state of the status register of the PHY chip to be debugged is connected, configuring the data transmission mode of the PHY chip based on the acquired address information of the target register of the PHY chip to be debugged; In response to the data transmission mode being a receiving mode, synchronously sending a set first clock signal and a first data packet to the PHY chip through the MAC module; wherein the first clock signal is used by the PHY chip in the receiving mode to collect the first data packet sent synchronously with the first clock signal according to the first clock signal and the receiving clock delay time in the configuration data of the PHY chip to obtain a second data packet; Acquire a second data packet collected by the PHY chip; Based on the comparison result of the first data packet and the second data packet, detecting the delay duration of the receiving clock of the PHY chip; and / or, in response to the data transmission mode being a sending mode, acquiring a third data packet collected by the MAC module; wherein the third data packet is obtained by the MAC module receiving the second clock signal and the fourth data packet synchronously sent by the PHY chip, and collecting the fourth data packet sent synchronously with the second clock signal according to the second clock signal and the sending clock delay time of the PHY chip carried by the second clock signal; Acquire a fourth data packet sent by the PHY chip; Based on the comparison result of the third data packet and the fourth data packet, the delay duration of the sending clock of the PHY chip is detected.

2. The method according to claim 1, characterized in that The detecting the receiving clock delay duration of the PHY chip based on the comparison result of the first data packet and the second data packet includes: comparing the first data packet and the second data packet; In response to data matching between the first data packet and the second data packet, determining that the reception clock delay duration is set correctly; In response to determining that the first data packet and the second data packet do not match, it is determined that the reception clock delay duration is set incorrectly.

3. The method according to claim 1, characterized in that The detecting the delay time of the sending clock of the PHY chip based on the comparison result of the third data packet and the fourth data packet includes: comparing the fourth data packet with the third data packet; In response to the fourth data packet not matching the third data packet, determining that a transmission clock delay duration of the PHY chip is set incorrectly; In response to the fourth data packet matching the third data packet, it is determined that the sending clock delay duration of the PHY chip is set accurately.

4. The method according to any one of claims 1 to 3, characterized in that: Before configuring the data transmission mode of the PHY chip based on the address information of the target register of the PHY chip to be debugged, when it is determined that the connection state of the status register of the PHY chip to be debugged is connected, the method further includes: A read instruction for reading the connection status is sent to the MAC module; wherein the read instruction is used by the MAC module to read the connection status of the status register of the PHY chip according to the read instruction.

5. A debugging method for an Ethernet PHY chip, characterized in that: include: Determine that the connection state of the status register of the PHY chip to be debugged is connected, and determine the data transmission mode of the PHY chip; wherein the data transmission mode is obtained by configuring the PHY chip by the SOC based on the address information of the target register of the PHY chip to be debugged obtained; In response to the data transmission mode being configured as a receiving mode, the first data packet sent synchronously with the first clock signal is collected by using the set first clock signal sent by the received SOC module through the MAC module and the receiving clock delay duration in the configuration data of the PHY chip to obtain a second data packet; wherein the second data packet is used by the SOC module to detect the receiving clock delay duration of the PHY chip based on the comparison result of the first data packet and the second data packet; And / or, in response to the data transmission mode being configured as the sending mode, a fourth data packet and the second clock signal of the PHY chip are synchronously sent to the MAC module; wherein the second clock signal is used by the MAC module to collect the fourth data packet sent synchronously with the second clock signal according to the second clock signal and the sending clock delay duration of the PHY chip carried by the second clock signal, to obtain a third data packet; wherein the third data packet is used by the SOC module to detect the sending clock delay duration of the PHY chip based on the comparison result of the third data packet and the fourth data packet.

6. A debugging device for an Ethernet PHY chip, characterized in that: include: a configuration module, configured to configure a data transmission mode of the PHY chip based on the acquired address information of the target register of the PHY chip to be debugged when determining that the connection state of the status register of the PHY chip to be debugged is connected; a sending module, configured to synchronously send a set first clock signal and a first data packet to the PHY chip through a MAC module in response to the data transmission mode being a receiving mode; wherein the first clock signal is used by the PHY chip in the receiving mode to collect the first data packet sent synchronously with the first clock signal according to the first clock signal and the receiving clock delay time in the configuration data of the PHY chip to obtain a second data packet; A first acquisition module, used to acquire a second data packet collected by the PHY chip; A first detection module, configured to detect a delay duration of a receiving clock of the PHY chip based on a comparison result of the first data packet and the second data packet; And / or, a second acquisition module, configured to acquire a third data packet collected by the MAC module in response to the data transmission mode being a sending mode; wherein the third data packet is obtained by the MAC module receiving the second clock signal and the fourth data packet synchronously sent by the PHY chip, and collecting the fourth data packet sent synchronously with the second clock signal according to the second clock signal and the sending clock delay time of the PHY chip carried by the second clock signal; A third acquisition module, used to acquire a fourth data packet sent by the PHY chip; The second detection module is used to detect the delay duration of the sending clock of the PHY chip based on the comparison result of the third data packet and the fourth data packet.

7. The device according to claim 6, characterized in that The first detection module is specifically used to: comparing the first data packet and the second data packet; In response to data matching between the first data packet and the second data packet, determining that the reception clock delay duration is set correctly; In response to determining that the first data packet and the second data packet do not match, it is determined that the reception clock delay duration is set incorrectly.

8. A debugging device for an Ethernet PHY chip, characterized in that: include: A determination module, used to determine that the connection state of the status register of the PHY chip to be debugged is connected, and to determine the data transmission mode of the PHY chip; wherein the data transmission mode is obtained by configuring the PHY chip by the SOC based on the address information of the target register of the PHY chip to be debugged obtained; A processing module, configured to, in response to the data transmission mode of the PHY chip to be debugged being configured as a receiving mode, collect a first data packet sent synchronously with the first clock signal using a set first clock signal sent by the received SOC module through the MAC module and a receiving clock delay duration in the configuration data of the PHY chip to obtain a second data packet; wherein the second data packet is used by the SOC module to detect the receiving clock delay duration of the PHY chip based on a comparison result of the first data packet and the second data packet; And / or, the processing module is also used to synchronously send a fourth data packet and the second clock signal of the PHY chip to the MAC module in response to the data transmission mode being configured as a sending mode; wherein the second clock signal is used by the MAC module to collect the fourth data packet sent synchronously with the second clock signal according to the second clock signal and the sending clock delay duration of the PHY chip carried by the second clock signal, to obtain a third data packet; wherein the third data packet is used by the SOC module to detect the sending clock delay duration of the PHY chip based on the comparison result of the third data packet and the fourth data packet.

9. An electronic device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method according to any one of claims 1 to 4 is implemented, or the method according to claim 5 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented, or the method according to claim 5 is implemented.

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