A multi-segment impedance routing structure and its preparation method, device, equipment, medium and product

Abstract

The present application discloses a multi-segment impedance routing structure and its preparation method, device, equipment, medium and product, relating to the field of communication technology. The structure includes a first connecting line and a second connecting line; the first connecting line is located in a narrow area of ​​the circuit board; the second connecting line is located in a loose area of ​​the circuit board, forming a multi-segment impedance routing structure; the width of the first connecting line is smaller than the width of the second connecting line, and the average impedance of each segment of the line in the multi-segment impedance routing structure is equal to the standard impedance; each segment of the line includes the first connecting line and the second connecting line. The present application can maintain the continuity of the routing impedance and ensure signal integrity.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a multi-segment impedance routing structure and a preparation method, device, equipment, medium and product thereof. Background Art

[0002] Nowadays, the density of chip packaging is getting higher and higher, and the pad spacing is getting smaller and smaller, which makes it more difficult for the traces on the circuit board to pass through the pad range. Narrowing the width of the trace to pass through the pad is the current treatment method, such as Figure 1 As shown, the change in line width will cause the trace impedance value to change. Since the trace impedance value is related to the signal reflection coefficient, and whether the transmitted signal is complete is determined by the signal reflection coefficient, the change in impedance value will cause the reflection coefficient to change. This practice will lead to discontinuity in the trace impedance, resulting in signal reflection, which in turn affects the signal integrity. Summary of the Invention

[0003] The purpose of this application is to provide a multi-segment impedance routing structure and its preparation method, device, equipment, medium and product to solve the problem of routing impedance discontinuity affecting signal integrity.

[0004] To achieve the above objectives, this application provides the following solutions.

[0005] In a first aspect, the present application provides a multi-segment impedance routing structure, which is applied to a circuit board. The multi-segment impedance routing structure includes: a first connecting line and a second connecting line.

[0006] The first connecting line is located in a narrow area of ​​the circuit board; the second connecting line is located in a loose area of ​​the circuit board, forming a multi-segment impedance routing structure; the width of the first connecting line is smaller than the width of the second connecting line, and the average impedance of each segment of the line in the multi-segment impedance routing structure is equal to the standard impedance; each segment of the line includes the first connecting line and the second connecting line.

[0007] In a second aspect, the present application provides a method for preparing a multi-segment impedance routing structure, comprising the following steps.

[0008] Based on the spatial position of the circuit board, the circuit board is divided into areas to determine narrow areas and loose areas.

[0009] Based on the pad positions on the circuit board, the first connecting line is set in the narrow area and the second connecting line is set in the loose area to determine the routing paths of the multiple-segment lines; the width of the first connecting line is smaller than the width of the second connecting line, and the average impedance of each segment of the line in the multi-segment impedance routing structure is equal to the standard impedance; each segment of the line includes the first connecting line and the second connecting line.

[0010] A final routing path is determined based on the routing path of each circuit segment and the spatial position of the circuit board, and a multi-segment impedance routing structure is prepared based on the final routing path.

[0011] In a third aspect, the present application provides a device for preparing a multi-segment impedance routing structure, including the following modules.

[0012] The area division module is used to divide the circuit board into areas based on the spatial position of the circuit board and determine the narrow area and the loose area.

[0013] A routing path determination module is configured to determine a routing path for multiple segments of wiring based on pad positions on the circuit board, by placing a first connecting line in the narrow area and a second connecting line in the loose area; the width of the first connecting line is smaller than the width of the second connecting line, and the average impedance of each segment of wiring in the multi-segment impedance routing structure is equal to a standard impedance; and each segment of wiring includes the first connecting line and the second connecting line.

[0014] The final routing route determination module is used to determine the final routing route according to the routing path of each line segment and the spatial position of the circuit board.

[0015] A multi-segment impedance routing structure preparation module is used to prepare a multi-segment impedance routing structure according to the final routing path.

[0016] In a fourth aspect, the present application provides a computer device comprising: a memory, a processor, and a computer program stored in the memory and runnable on the processor, wherein the processor executes the computer program to implement the method for preparing a multi-segment impedance routing structure described above.

[0017] In a fifth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method for preparing the multi-segment impedance routing structure described in any one of the above.

[0018] In a sixth aspect, the present application provides a computer program product, comprising a computer program, which, when executed by a processor, implements the method for preparing the multi-segment impedance routing structure described in any one of the above.

[0019] According to the specific embodiments provided in this application, this application discloses the following technical effects.

[0020] The present application provides a multi-segment impedance routing structure and its preparation method, device, equipment, medium and product. Based on the spatial position of the circuit board, narrow areas and loose areas are divided to set connecting lines of different widths, namely first connecting lines and second connecting lines, to form a multi-segment impedance routing structure; wherein the multi-segment impedance routing structure includes multiple segments of lines. When setting the first connecting line and the second connecting line, the present application requires that the average impedance of each segment of the line is equal to the standard impedance. Wherein, Γ is the signal reflection coefficient, ZL is the load impedance, which is the average impedance of each line segment here, and Zo is the standard impedance. It can be seen that the signal reflection coefficient of the multi-segment impedance routing structure prepared in the present application is 0, thereby maintaining the continuity of the routing impedance of the multi-segment impedance routing structure of the present application, thereby avoiding signal reflection and ensuring signal integrity. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 Schematic diagram of the existing method for narrowing the routing.

[0023] Figure 2 A schematic diagram of a multi-segment impedance routing structure provided in one embodiment of the present application.

[0024] Figure 3 This is a schematic diagram of another multi-segment impedance routing structure provided in an embodiment of the present application.

[0025] Figure 4 A schematic flow chart of a method for preparing a multi-segment impedance routing structure provided in one embodiment of the present application.

[0026] Figure 5 A schematic diagram of a computer device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0028] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0029] In the Ball Grid Array (BGA) packaging process, such as Figure 1 The method shown is to narrow the width of the trace to cross the pad range. Since the reflection coefficient is as high as 20%, the signal integrity is seriously affected.

[0030] Based on this, the present application provides a multi-segment impedance routing structure, which is applied to a circuit board. The multi-segment impedance routing structure includes: a first connecting line and a second connecting line; the first connecting line is located in a narrow area of ​​the circuit board; the second connecting line is located in a loose area of ​​the circuit board, forming a multi-segment impedance routing structure, such as Figure 2-Figure 3 As shown; the width of the first connecting line is smaller than the width of the second connecting line, and the average impedance of each segment of the line in the multi-segment impedance routing structure is equal to the standard impedance; each segment of the line includes the first connecting line and the second connecting line.

[0031] In an exemplary embodiment, the routing path length of each line segment is less than a critical length; the critical length is determined based on a signal rise time when a radar detection instrument measures the impedance value of each line segment.

[0032] In an exemplary embodiment, the critical length L Critical For: L Critical =T rise / 2; where T rise is the signal rise time.

[0033] In an exemplary embodiment, the critical length is equal to an averaging window of a radar detection instrument.

[0034] In practical applications, a radar detection instrument with time domain reflectometry (TDR) technology is used to measure the impedance value of a transmission line using an averaging window. The transmission line is the line of the multi-segment impedance trace structure.

[0035] Within the averaging window, if the average impedance is equal to the characteristic impedance of the transmission line, the continuity of the transmission line can be maintained and the signal integrity can be maintained.

[0036] In an exemplary embodiment, the average impedance Z of each line segment is avg (t) is: Where a is the starting point of each line segment, b is the end point of each line segment, t is the routing path length of each line segment, and Z(t) is the impedance of the routing path length.

[0037] In practical applications, the multi-segment impedance routing structure is not limited to use in narrow pad spacing, but can also be used between vias, etc.

[0038] exist Figure 2 In, t a for Figure 2 The starting time of the multi-segment impedance trace structure shown, t b for Figure 2 The endpoint time of the multi-segment impedance routing structure shown in the figure, a section of the line shown in the multi-segment impedance routing structure includes a first connecting line and a second connecting line connected to each other; the impedance Z1 of the first connecting line is 50Ω, and the impedance of the second connecting line is 30Ω; the standard impedance is 40Ω, therefore, Because Z avg (t) = ZL, therefore, There is no signal reflection and the integrity of the serial number will not be affected during transmission.

[0039] exist Figure 3 In, t a’ for Figure 3 The starting time of the multi-segment impedance trace structure shown, t b’ for Figure 3 The endpoint time of the multi-segment impedance routing structure shown in the figure, a section of the line shown in the multi-segment impedance routing structure includes a first connecting line and a second connecting line connected to each other; the impedance Z1 of the first connecting line is 50Ω, and the impedance of the second connecting line is 30Ω; the standard impedance is 40Ω, so, Because Z' avg (t)=ZL,a'is Figure 3 The starting point of each line shown, b' is Figure 3 The end point of each line segment shown, therefore, There is no signal reflection and the integrity of the serial number will not be affected during transmission.

[0040] The present application uses a multi-segment impedance routing structure in a narrow pad spacing and uses the multi-segment impedance routing structure within a critical length to reduce impedance discontinuity.

[0041] The embodiment of the present application provides a method for preparing a multi-segment impedance routing structure, which is executed by a computer device, specifically a computer device such as a terminal or a server, or a terminal and a server. In the embodiment of the present application, Figure 4 As shown, the method includes the following steps.

[0042] S1: Based on the spatial location of the circuit board, the circuit board is divided into areas to determine narrow areas and loose areas.

[0043] S2: Based on the pad positions on the circuit board, the first connecting line is set in the narrow area and the second connecting line is set in the loose area to determine the routing path of the multi-segment circuit; the width of the first connecting line is smaller than the width of the second connecting line, and the average impedance of each segment of the circuit in the multi-segment impedance routing structure is equal to the standard impedance; each segment of the circuit includes the first connecting line and the second connecting line. Figure 2-Figure 3 BGA pads shown.

[0044] S3: Determine a final routing path according to the routing path of each line segment and the spatial position of the circuit board.

[0045] S4: preparing a multi-segment impedance routing structure according to the final routing path.

[0046] In practical applications, the first step is to determine the standard impedance Zo of the connecting line according to production requirements.

[0047] Step 2: Design the routing paths for multiple lines based on the pad positions on the circuit board.

[0048] Step 3: Design the final routing path based on the routing paths of multiple lines and the spatial position of the circuit board. The final routing path consists of one or more lines, and the routing path length of each line does not exceed the critical length, ensuring the average impedance Z of the routing path length of each line avg Equal to the standard impedance Zo.

[0049] Therefore, the impedance design method for each line segment is as follows: according to the spatial position of the circuit board, the width of the connection line is reduced in the narrow part, such as the boundary or between the pad array; in the loose part, the width of the connection line is increased to ensure the average impedance Z of each line segment. avg Equal to the standard impedance Zo.

[0050] Step 4: Complete the line connection according to the final routing path and the impedance design of each line segment, and prepare a multi-segment impedance routing structure.

[0051] Based on the same inventive concept, embodiments of the present application also provide a device for fabricating a multi-segment impedance trace structure for implementing the aforementioned method for fabricating a multi-segment impedance trace structure. The solution provided by this device is similar to the solution described in the aforementioned method. Therefore, the specific limitations of one or more embodiments of the device for fabricating a multi-segment impedance trace structure provided below can be found in the aforementioned method for fabricating a multi-segment impedance trace structure, and will not be further elaborated here.

[0052] In an exemplary embodiment, a device for preparing a multi-segment impedance routing structure is provided, including the following modules.

[0053] The area division module is used to divide the circuit board into areas based on the spatial position of the circuit board and determine the narrow area and the loose area.

[0054] A routing path determination module is configured to determine a routing path for multiple segments of wiring based on pad positions on the circuit board, by placing a first connecting line in the narrow area and a second connecting line in the loose area; the width of the first connecting line is smaller than the width of the second connecting line, and the average impedance of each segment of wiring in the multi-segment impedance routing structure is equal to a standard impedance; and each segment of wiring includes the first connecting line and the second connecting line.

[0055] The final routing route determination module is used to determine the final routing route according to the routing path of each line segment and the spatial position of the circuit board.

[0056] A multi-segment impedance routing structure preparation module is used to prepare a multi-segment impedance routing structure according to the final routing path.

[0057] In an exemplary embodiment, a computer device is provided, such as Figure 5As shown, the computer device can be a server or a terminal. The computer device includes a processor, a memory, an input / output interface (I / O) and a communication interface. The processor, the memory and the input / output interface are connected via a system bus, and the communication interface is connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store preparation data of a multi-segment impedance routing structure. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a method for preparing a multi-segment impedance routing structure is implemented.

[0058] In an exemplary embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor implements the above method when executing the computer program.

[0059] In an exemplary embodiment, a computer-readable storage medium is provided, storing a computer program, which implements the above method when executed by a processor.

[0060] In an exemplary embodiment, a computer program product is provided, including a computer program, which implements the above method when executed by a processor.

[0061] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM may be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0062] In this application, all actions to obtain signals, information or data are carried out in compliance with the relevant data protection laws and policies of the country where they are located and with the authorization given by the owner of the corresponding device.

[0063] The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processors involved in the various embodiments provided herein may include, but are not limited to, general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic units, data processing logic units based on quantum computing, and the like.

[0064] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0065] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above examples is only intended to help understand the method and core concept of this application. At the same time, for those skilled in the art, based on the concept of this application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A multi-segment impedance routing structure, characterized in that: The multi-segment impedance routing structure is applied to a circuit board, and the multi-segment impedance routing structure includes: a first connecting line and a second connecting line; The first connecting line is located in a narrow area of ​​the circuit board; the second connecting line is located in a loose area of ​​the circuit board, forming a multi-segment impedance routing structure; the width of the first connecting line is smaller than the width of the second connecting line, and the average impedance of each segment of the multi-segment impedance routing structure is equal to the standard impedance; each segment includes the first connecting line and the second connecting line; the average impedance Z of each segment is avg (t) is: Where a is the starting point of each line segment, b is the end point of each line segment, t is the routing path length of each line segment, and Z(t) is the impedance of the routing path length.

2. The multi-segment impedance routing structure according to claim 1, wherein: The routing path length of each section of the line is less than a critical length; the critical length is determined based on a signal rise time when a radar detection instrument measures the impedance value of each section of the line.

3. A method for preparing a multi-segment impedance routing structure, characterized in that: The method for preparing the multi-segment impedance routing structure is applied to the multi-segment impedance routing structure according to any one of claims 1 to 2, and the method for preparing the multi-segment impedance routing structure comprises: Based on the spatial location of the circuit board, the circuit board is divided into areas to determine the narrow area and the loose area; Based on the pad positions on the circuit board, the first connecting line is set in the narrow area and the second connecting line is set in the loose area to determine the routing path of the multi-segment circuit; the width of the first connecting line is smaller than the width of the second connecting line, and the average impedance of each segment of the circuit in the multi-segment impedance routing structure is equal to the standard impedance; each segment of the circuit includes the first connecting line and the second connecting line; the average impedance Z of each segment of the circuit is equal to the standard impedance. avg (t) is: Where a is the starting point of each line segment, b is the end point of each line segment; t is the routing path length of each line segment; Z(t) is the impedance of the routing path length; Determining a final routing path based on the routing path of each line segment and the spatial position of the circuit board; A multi-segment impedance routing structure is prepared according to the final routing path.

4. A device for preparing a multi-segment impedance routing structure, characterized in that: The manufacturing device of the multi-segment impedance routing structure includes: The area division module is used to divide the circuit board into areas based on the spatial location of the circuit board and determine the narrow area and loose area; A routing path determination module is configured to determine the routing paths of multiple segments of lines by placing a first connecting line in the narrow area and a second connecting line in the loose area based on the pad positions on the circuit board; the width of the first connecting line is smaller than the width of the second connecting line, and the average impedance of each segment of the line in the multi-segment impedance routing structure is equal to the standard impedance; each segment of the line includes the first connecting line and the second connecting line; the average impedance Z of each segment of the line is equal to the standard impedance; avg (t) is: Where a is the starting point of each line segment, b is the end point of each line segment; t is the routing path length of each line segment; Z(t) is the impedance of the routing path length; A final routing route determination module is used to determine the final routing route based on the routing path of each line segment and the spatial position of the circuit board; A multi-segment impedance routing structure preparation module is used to prepare a multi-segment impedance routing structure according to the final routing path.

5. A computer device comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method for preparing the multi-segment impedance routing structure according to claim 3.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for preparing the multi-segment impedance routing structure according to claim 3 is implemented.

7. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method for preparing the multi-segment impedance routing structure according to claim 3 is implemented.

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