Integrated assemblies including metal-containing interconnects to active region struts and methods of forming integrated assemblies

Abstract

The invention relates to an integrated assembly including metal-containing interconnects to active region struts and a method of forming an integrated assembly. Some embodiments include an integrated assembly with active region struts. Each of the active region pillars has a contact region. The contact regions include a pair of memory element contact regions and a digital line contact region between the memory element contact regions. The active region pillar includes silicon. Word lines extend along the active region pillars and along a first direction. Cobalt silicide directly abuts the silicon of one or more of the contact regions. A metal-containing material directly abuts the cobalt silicide. A digital line is electrically coupled with the digital line contact region and extends along a second direction crossing the first direction. A memory element is electrically coupled with the memory element contact region. Some embodiments include methods of forming an integrated assembly.

Description

[0001] Divisional Application Information

[0002] This application is a divisional application of an invention patent application with an application date of August 28, 2019, application number "201980068846.X", and invention name "Integrated assembly containing metal interconnects to active area pillars and method for forming an integrated assembly". Technical Field

[0003] An integrated assembly including metal-containing interconnects to active area pillars and methods of forming the integrated assembly. Background Art

[0004] Memory is a type of integrated circuit and is used in computer systems to store data. An example memory is DRAM (Dynamic Random Access Memory). DRAM cells may each include a transistor and capacitor combination. DRAM cells may be arranged in an array; where word lines extend along the rows of the array and digit lines extend along the columns of the array. The word lines may be coupled to the transistors of the memory cells. Each memory cell may be uniquely addressable via a combination of one of the word lines and one of the digit lines.

[0005] New methods need to be developed for manufacturing highly integrated DRAMs, and new architectures need to be developed for manufacturing with these methods. Summary of the invention

[0006] In one aspect, the present disclosure relates to an integrated assembly comprising: active area pillars; each of the active area pillars having a contact area associated therewith; the contact area being associated with each of the active area pillars, each of the active area pillars including a pair of storage element contact areas, and including a digit line contact area between the storage element contact areas of the pair; the active area pillars comprising silicon; a word line extending along the active area pillars and along a first direction; cobalt silicide directly abutting the silicon of one or more of the contact areas; a metal-containing material directly abutting the cobalt silicide; a digit line electrically coupled to the digit line contact area and extending along a second direction intersecting the first direction; and a storage element electrically coupled to the storage element contact areas of the pair BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1-1C is a diagrammatic view of a region of an example construction at an example initial processing stage of an example method of forming an example integrated assembly. Figure 1 It is a diagrammatic top view; Figure 1C is a diagrammatic cross-sectional top view; and Figure 1A and 1B is a diagrammatic cross-sectional side view. Figure 1A The view is along the Figure 1 , 1B and line AA of 1C. Figure 1B The view is along the Figure 1 , 1A and 1C for line BB. Figure 1C The view is along the Figure 1A and 1B Line CC.

[0008] Figure 2-2B is Figure 1-1C The instance processing phase after the processing phase Figure 1-1C A diagrammatic view of a zone constructed for an example of . Figure 2 It is a diagrammatic top view; Figure 2A It is along Figure 2 and 2B A diagrammatic cross-sectional side view of line AA of FIG. 1 ; and Figure 2B It is along Figure 2 and 2A Diagrammatic cross-sectional side view of line BB.

[0009] Figure 3-3B is Figure 2-2B The instance processing phase after the processing phase Figure 1-1C A diagrammatic view of a zone constructed for an example of . Figure 3 It is a diagrammatic top view; Figure 3A It is along Figure 3 and 3B A diagrammatic cross-sectional side view of line AA of FIG. 1 ; and Figure 3B It is along Figure 3 and 3A Diagrammatic cross-sectional side view of line BB.

[0010] Figure 4-4B is Figure 3-3B The instance processing phase after the processing phase Figure 1-1C A diagrammatic view of a zone constructed for an example of . Figure 4 It is a diagrammatic top view; Figure 4A It is along Figure 4 and 4B A diagrammatic cross-sectional side view of line AA of FIG. 1 ; and Figure 4B It is along Figure 4 and 4A Diagrammatic cross-sectional side view of line BB.

[0011] Figure 5-5B is Figure 4-4B The instance processing phase after the processing phase Figure 1-1C A diagrammatic view of a zone constructed for an example of . Figure 5 It is a diagrammatic top view; Figure 5A It is along Figure 5 and 5BA diagrammatic cross-sectional side view of line AA of FIG. 1 ; and Figure 5B It is along Figure 5 and 5A Diagrammatic cross-sectional side view of line BB.

[0012] Figure 6-6B is Figure 5-5B The instance processing phase after the processing phase Figure 1-1C A diagrammatic view of a zone constructed for an example of . Figure 6 It is a diagrammatic top view; Fig. 6A It is along Figure 6 and 6B A diagrammatic cross-sectional side view of line AA of FIG. 1 ; and Figure 6B It is along Figure 6 and 6A Diagrammatic cross-sectional side view of line BB.

[0013] Figure 7-7B is Figure 6-6B The instance processing phase after the processing phase Figure 1-1C A diagrammatic view of a zone constructed for an example of . Figure 7 It is a diagrammatic top view; Fig. 7A It is along Figure 7 and 7B A diagrammatic cross-sectional side view of line AA of FIG. 1 ; and Figure 7B It is along Figure 7 and 7A Diagrammatic cross-sectional side view of line BB.

[0014] Figure 8-8B is Figure 7-7B The instance processing phase after the processing phase Figure 1-1C A diagrammatic view of a zone constructed for an example of . Figure 8 It is a diagrammatic top view; Fig. 8A It is along Figure 8 and 8B A diagrammatic cross-sectional side view of line AA of FIG. 1 ; and Figure 8B It is along Figure 8 and 8A Diagrammatic cross-sectional side view of line BB.

[0015] Figure 9-9B is Figure 8-8B The instance processing phase after the processing phase Figure 1-1C A diagrammatic view of a zone constructed for an example of . Fig. 9 It is a diagrammatic top view; Fig.9A It is along Fig. 9 and 9B A diagrammatic cross-sectional side view of line AA of FIG. 1 ; and Fig. 9B It is along Fig. 9 and 9ADiagrammatic cross-sectional side view of line BB.

[0016] Figure 10-10B is Figure 9-9B The instance processing phase after the processing phase Figure 1-1C A diagrammatic view of a zone constructed for an example of . Fig.10 It is a diagrammatic top view; Fig. 10A It is along Fig.10 and 10B A diagrammatic cross-sectional side view of line AA of FIG. 1 ; and Fig. 10B It is along Fig.10 and 10A Diagrammatic cross-sectional side view of line BB.

[0017] Figure 11-11B is Figure 10-10B The instance processing phase after the processing phase Figure 1-1C A diagrammatic view of a zone constructed for an example of . Fig.11 It is a diagrammatic top view; Fig.11A It is along Fig.11 and 11B A diagrammatic cross-sectional side view of line AA of FIG. 1 ; and Fig. 11B It is along Fig.11 and 11A Diagrammatic cross-sectional side view of line BB.

[0018] Figure 12-12B is Figure 11-11B The instance processing phase after the processing phase Figure 1-1C A diagrammatic view of a zone constructed for an example of . Fig.12 It is a diagrammatic top view; Fig. 12A It is along Fig.12 and 12B A diagrammatic cross-sectional side view of line AA of FIG. 1 ; and Fig. 12B It is along Fig.12 and 12A Diagrammatic cross-sectional side view of line BB.

[0019] Figure 13-13B is Figure 12-12B The instance processing phase after the processing phase Figure 1-1C A diagrammatic view of a zone constructed for an example of . Fig.13 It is a diagrammatic top view; Fig.13A It is along Fig.13 and 13B A diagrammatic cross-sectional side view of line AA of FIG. 1 ; and Fig. 13B It is along Fig.13 and 13A Diagrammatic cross-sectional side view of line BB.

[0020] Figure 14-14B is Figure 13-13BThe instance processing phase after the processing phase Figure 1-1C A diagrammatic view of a zone constructed for an example of . Fig.14 It is a diagrammatic top view; Fig.14A It is along Fig.14 and 14B A diagrammatic cross-sectional side view of line AA of FIG. 1 ; and Fig. 14B It is along Fig.14 and 14A Diagrammatic cross-sectional side view of line BB.

[0021] Fig.15 is a diagrammatic representation of a region of an example memory array.

[0022] Figure 16-19 It is available to follow Fig. 12A The instance processing phase of the instance method of the processing phase is along the same Fig. 12A Diagrammatic cross-sectional side view of the same cross section. DETAILED DESCRIPTION

[0023] Some embodiments include methods of forming connections to digit line contact regions and / or methods of forming connections to storage element contact regions. The connections may include interconnects having metal on metal silicide; and in some embodiments, the interconnects may include ruthenium on cobalt silicide. The interconnects may directly contact single crystal silicon of digit line contact regions and / or storage element contact regions. Some embodiments include an integrated assembly having a conductive interconnect comprising a metal-containing material (e.g., one or more of copper, molybdenum, palladium, platinum, ruthenium, tungsten, titanium, etc.) on cobalt silicide. Reference is made below to Figure 1-19 Example embodiments are described.

[0024] See also Figure 1-1C , showing a portion of an example integrated assembly 10. Such assemblies may be formed using any suitable method. Assembly 10 includes a plurality of active regions 12 (also referred to herein as active region pillars) extending upwardly from a semiconductor substrate 14. Some of active regions 12 are labeled 12a-f so that they can be distinguished from each other and from other active regions. All active regions 12 may be substantially identical to each other; wherein the term "substantially identical" means identical within reasonable manufacturing and measurement tolerances. Active regions 12 are located at Figure 1 The components are shown in dashed lines (phantom) to indicate that they are beneath other materials.

[0025] Active region 12 and semiconductor substrate 14 include semiconductor material 16. This semiconductor material may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, and the like; wherein the term III / V semiconductor material refers to semiconductor materials including elements selected from Groups III and V of the periodic table (wherein Groups III and V are legacy nomenclature and are now referred to as Groups 13 and 15). In some embodiments, semiconductor material 16 may include, consist essentially of, or consist of appropriately doped silicon. Silicon may be in any suitable form; and in some embodiments may be single crystal silicon. In some embodiments, semiconductor material 16 of the active region may be referred to as active region material.

[0026] Base 14 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any structure including semiconductor material, including but not limited to bulk semiconductor material, such as semiconductor wafers (alone or in an assembly including other materials), and layers of semiconductor material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrates described above.

[0027] Active regions 12 are separated from one another by intervening regions that include insulating materials 18 and 28. Insulating material 18 may include any suitable composition or combination of compositions; and in some embodiments, may include, consist essentially of, or consist of silicon dioxide. Insulating material 28 may include any suitable composition; and in some embodiments, may include, consist essentially of, or consist of silicon dioxide and / or silicon nitride. Insulating material 28 may be the same composition as insulating material 18, or may be a different composition than insulating material 18.

[0028] The word line (ie, access line) 20 is arranged along a first direction (from Figure 1 and 1C The first direction may correspond to the row direction of the memory array. The word line 20 is Figure 1 1 and 2. The word lines 12 are shown in dashed lines (phantom) in order to indicate that they are underneath other materials. Digital lines (i.e., sense lines, bit lines) will be formed with the processes described herein, and such digital lines will extend along a second direction (represented by the y-axis) which may correspond to the column direction of the memory array. The word lines are adjacent to the active area pillars 12. The second direction (i.e., the column direction) may be orthogonal to the first direction (i.e., the row direction), or may simply cross the first direction.

[0029] The word line 20 includes a conductive material 24. The conductive material 24 may include any suitable conductive composition, such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.).

[0030] Insulating material 28 is over word line 20 .

[0031] Gate dielectric material 30 extends around the lower region of word line 20 and between the word line and active region 12. Gate dielectric material 30 may include any suitable composition and in some embodiments may include, consist essentially of, or consist of silicon dioxide.

[0032] The word lines 20 include transistor gates along the active regions 12. Each of the active regions (ie, active region pillars) 12 can be viewed as including a digit line contact region 32 (eg, a digit line contact region 32) between a pair of storage element contact regions 34. Figure 1A and 1C ). In some embodiments, regions 32 and 34 may be generally referred to as contact regions.

[0033] The word line 20 includes a transistor gate that couples the storage element contact region 34 with the digit line contact region 32 in a gating manner. The digit line contact region 32 and the storage element contact region 34 are connected at Figure 1C The indication is to assist the reader in understanding the relative position of the word line 20 relative to the digit line contact region 32 and the storage element contact region 34. However, it should be understood that the digit line contact region 32 and the storage element contact region 34 are actually compared to Figure 1C The cross section is located higher above the active area, such as Figure 1A and 1B Instructions.

[0034] Digit line contact region 32 is ultimately coupled to a digit line, and storage element contact region 34 is ultimately coupled to a storage element (eg, a capacitor), as described in greater detail below.

[0035] In some embodiments, materials 16, 18, 24, 28, and 30 may be considered to form construction 22. A large sheet of first material 26 is formed to extend across construction 22. In some embodiments, first material 26 may include, consist essentially of, or consist of silicon nitride.

[0036] In the embodiment shown, the first material is over insulating material 36, which in turn is over construction 22. Insulating material 36 may include any suitable composition; including, for example, one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, and the like.

[0037] See also Figure 2-2B , forming opening 38 to extend into material 26. Opening 38 may be patterned using a mask (not shown) and any suitable etch. For example, if material 26 includes silicon nitride, the etch may utilize phosphoric acid.

[0038] The patterned material 26 may be referred to as a patterning mold 40; wherein the patterning mold has an opening 38 extending therethrough.

[0039] Although opening 38 is shown as circular in top view, it should be understood that the opening may have other shapes in other embodiments. For example, in some example embodiments, in top view, the opening may be oval, square, rectangular, polygonal, etc. Opening 38 may have any suitable size, and in some embodiments may have a width W (e.g., the diameter of the circular opening shown) in a range of at least about 2 nanometers (nm) to less than or equal to about 15 nm; and in some embodiments, this width may be less than or equal to about 10 nm.

[0040] See also Figure 3-3B , opening 38 extends through material 36 and into formation 22. Opening 38 is aligned with digit line contact region 32 and, in the embodiment shown, extends into semiconductor material 16 of digit line contact region 32. Opening 38 may extend into semiconductor material 16 using any suitable etch. For example, in some embodiments, semiconductor material 16 may include silicon (e.g., single crystal silicon), and the opening may extend into the semiconductor material using an etch using one or more of nitric acid, potassium hydroxide, and tetramethylammonium hydroxide.

[0041] See also Figure 4-4B , after openings 38 extend into active region 12, sacrificial material 42 is formed within such openings. Sacrificial material 42 may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of one or more carbon-containing polymers. Such polymers may include carbon and hydrogen; and may also include one or more heteroatoms (e.g., nitrogen, oxygen, etc.). Example polymers may be compositions conventionally used as bottom antireflective compositions (BARCs), compositions used as underlayers (ULs), and the like.

[0042] In some embodiments, sacrificial material 42 may initially be spread across the surface of assembly 10 to fill opening 38, and then the polymer may be cured using a suitable bake. Excess polymer may then be removed using any suitable process. In the embodiment shown, assembly 10 has a planarized upper surface 43 extending across sacrificial material 42 and material 26. This planarized surface may be formed by removing excess sacrificial material 42 using chemical mechanical polishing (CMP).

[0043] See also Figure 5-5B , grooves 44-47 are formed in patterned mold 40. The grooves extend along a second direction represented by the y-axis. Grooves 44-47 have a width W1 that is equal to the width W of opening 38 (see above). Figure 2-2B described).

[0044] Trenches 44-47 may be formed using any suitable process; and in some embodiments may be formed using a selective etch of material 26 relative to material 36 (e.g., a selective etch of silicon nitride relative to silicon dioxide). For purposes of understanding the present disclosure and the appended claims, a material should be understood to be "selectively removed" relative to another material if the material is removed faster than the other material; this may include (but is not limited to) a condition where one material is 100% selective relative to the other material.

[0045] Phosphoric acid may be used in the example etch used to form trenches 44-47. In the illustrated embodiment, sacrificial material 42 ( Figure 4-4B ) to reopen opening 38; wherein the reopened opening is located at the bottom of trenches 44-47. In some embodiments, trenches 44-47 are formed using an etch (e.g., an etch using phosphoric acid) followed by a clean to remove organic residues, and sacrificial material 42 includes a carbon-containing polymer that is removed during this clean. An example clean may utilize ammonia and hydrogen peroxide.

[0046] The digit line contact region 32 has an exposed surface 49 along the bottom of the reopened opening 38 .

[0047] See also Figure 6-6B, silicon (or other suitable semiconductor material) 50 is epitaxially grown from the exposed surface 49 of the semiconductor material 16. The epitaxially grown silicon can be formed to any suitable thickness. In the embodiment shown, the silicon 50 grows to a certain thickness so that it remains below the material 26 of the patterned mold 40. In other embodiments, the silicon 50 can be grown to be thick enough to extend into the patterned mold 40. In some embodiments, the epitaxially grown silicon 50 can be omitted. In some embodiments, the epitaxially grown silicon 50 can be replaced with polycrystalline silicon deposited above the surface 49. However, in some applications, it may be advantageous to use epitaxially grown silicon 50 instead of polycrystalline silicon because epitaxially grown silicon can provide lower resistance and better uniformity than polycrystalline silicon can achieve, especially within the strict boundaries of highly integrated circuits. The epitaxially grown silicon 50 can be conductively doped with one or more suitable dopants (e.g., phosphorus, boron, etc.).

[0048] Conductive metal-containing material 52 is formed on and directly against epitaxially grown silicon 50. In some embodiments, metal-containing material 52 may include a metal silicide. For example, in some example embodiments, metal-containing material 52 may include, consist essentially of, or consist of cobalt silicide. In some embodiments, metal-containing material 52 may be considered to be directly against the silicon of digit line contact region 32; regardless of whether metal-containing material 52 is directly against epitaxially grown material 50 or directly against semiconductor material 16.

[0049] Spacers 54 are optionally formed adjacent to the sidewalls of trenches 44-47. Spacers include insulating material 56, which may be referred to as insulating spacer material. Material 56 may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of one or more of silicon dioxide, carbon-doped silicon dioxide (SiOC, where the formula indicates the main component but not a specific stoichiometry), silicon oxynitride (SiON, where the formula indicates the main component but not a specific stoichiometry), and the like. In some applications, material 56 may be low-k (i.e., may have a dielectric constant less than that of silicon dioxide). An advantage of low-k materials may be that they may provide high selectivity during subsequent etching and cleaning (e.g., during wet cleaning), especially in situations where dry etching plasma damage may be avoided. In some embodiments, material 26 of patterned mold 40 may be referred to as a first material having a first composition, and material 56 of spacer 54 may be referred to as a second material having a second composition different from the first composition.

[0050] Spacer 54 may be formed after silicon 50 and metal-containing material 52 (as shown); or may be formed before silicon 50 and metal-containing material 52, in which case spacer 54 may extend into opening 38 (opening 38 is formed between the silicon 50 and the metal-containing material 52). Figure 5-5B) and extends along the sides of material 50 and metal-containing material 52.

[0051] The trenches 44-47 are narrowed by the spacers 54; and in some embodiments, Figure 6-6B The processing stage may have a width less than or equal to about 10 nm.

[0052] See also Figure 7-7B , an optional barrier material 58 is disposed within the trenches 45-47 to line the trenches. In the embodiment shown, the barrier material 58 extends along the bottom of the trenches and the sides of the trenches and directly abuts against the upper surface of the metal-containing material 52. The barrier material 58 may include any suitable composition; and in some embodiments may include one or more of ruthenium, tantalum, and titanium.

[0053] Digit line material 60 is disposed within trenches 44-47 and adjacent to optional barrier material 58. Digit line material 60 may include any suitable composition; and in some embodiments may include a metal. For example, in some embodiments, digit line material 60 may include, consist essentially of, or consist of copper, molybdenum, palladium, platinum, ruthenium, tungsten, titanium, and mixtures thereof. Barrier material 58 may be particularly useful in applications where the digit line material includes copper in order to prevent copper migration. In other embodiments, barrier material 58 may be omitted, and the metal of digit line material 60 may directly contact metal-containing material 52. For example, in some applications, digit line material 60 may include, consist essentially of, or consist of ruthenium; and such ruthenium may directly contact an upper surface of metal-containing material 52 (e.g., may directly contact an upper surface of metal-containing material 52).

[0054] See also Figure 8-8B, materials 56, 58, and 60 are recessed within trenches 44-47, and then additional insulating material 56 is formed over recessed materials 56, 58, and 60 and is used to fill trenches 44-47. In the illustrated embodiment, trenches 44-47 are filled with the same insulating material 56 as is used in spacers 54. This may be advantageous because it may enable easy identification of an etch that will selectively remove material 26 of mold 40 relative to material 56 surrounding digit line material 60. In other embodiments, the insulating material used to fill trenches 44-47 may be different from the material used for spacers 54. In some embodiments, materials 26 and 56 may be referred to as first and second materials, respectively; wherein the first material comprises silicon nitride and the second material comprises silicon dioxide. It should be noted that different structures including material 56 will merge with each other to form a single structure including material 56. However, the structures are shown separated from one another so that the structures are clearly demarcated in the assembly described herein; in part to assist the reader in identifying the structures recited in the appended claims, and in part because the application also includes embodiments in which the structures do not all include the same material 56.

[0055] Figure 8-8B The recessed digit line material 60 can be regarded as a digit line 62 configured to extend along the second direction y-axis. Such digit lines are electrically coupled to the digit line contact region 32 .

[0056] See also Figure 9-9B , selectively removing the first material 26 relative to the second material 56 ( Figure 8-8B ). The selective removal of material 26 may utilize any suitable conditions; and in some embodiments may utilize phosphoric acid to selectively remove silicon nitride relative to silicon dioxide.

[0057] Removal of material 26 ( Figure 8-8B ) forms grooves 63-67 extending along the second direction y-axis. In some embodiments, grooves 63-67 may be referred to as second grooves to distinguish them from the above reference grooves. Figure 5-5B The first trenches 44-47 are described as distinguishing the digital line 62 between the second trenches 63-67. Fig.9A shown.

[0058] See also Figure 10-10B , spacers 68 are formed along the sidewalls of the second trenches 63-67. In the illustrated embodiment, the spacers 68 include the second material 56 (eg, silicon dioxide). Subsequently, the trenches 63-67 are filled with the first material 26 (eg, silicon nitride).

[0059] See also Figure 11-11B , the first material 26 is patterned into first material pillars 70 aligned with the storage element contact regions 34. Fig.11Only some of the pillars 70 are labeled with the number 70 in the top view of FIG. However, all pillars 70 are labeled with an "N" to identify such pillars; wherein the label "N" indicates that in some embodiments the pillars may include silicon nitride. The second material 56 is formed in the trenches 63-67 ( Fig.10 ) and in the region between the pillars 70. Fig.11 Such regions are marked with “O” in the top view of FIG. 5 to identify such regions; wherein the mark “O” indicates that in some embodiments the region may include silicon dioxide.

[0060] Material 26 may be patterned into pillars 70 using any suitable process. For example, in some embodiments, one or more masks may extend along the x-axis direction and be used to pattern material 26 into pillars 70 in conjunction with one or more suitable etches.

[0061] See also Figure 12-12B , selectively removing the first material 26 relative to the second material 56 ( Figure 11-11B ) to form openings 72 aligned with portions of storage element contact regions 34. It should be noted that in some embodiments, material 36 may include the same composition as second material 56 (e.g., silicon dioxide), and accordingly regions of material 36 may be considered to correspond to additional regions of the second material. Fig.12 The top view uses the mark "O" to help readers understand Fig.11 The regions marked “N” are selectively removed relative to the regions marked “O”.

[0062] See also Figure 13-13B , opening 72 extends through material 36 and into semiconductor material 16 of storage element contact region 34. Opening 72 may be constructed using a method similar to that described above with reference to Figure 3-3B The process described with respect to the extension of the opening 38 extends.

[0063] The storage element contact region 34 has an exposed surface 73 along the bottom of the extended opening 72 .

[0064] See also Figure 14-14B , silicon (or other suitable semiconductor material) 74 is epitaxially grown from the exposed surface 73 of the semiconductor material 16. The epitaxially grown silicon can be formed to any suitable thickness. In some embodiments, the epitaxially grown silicon 74 can be omitted. In some embodiments, the epitaxially grown silicon 74 can be replaced with polycrystalline silicon deposited above the surface 73. However, in some applications, it may be advantageous to utilize epitaxially grown silicon 74 instead of polycrystalline silicon because epitaxially grown silicon can provide lower resistance and better uniformity than that achievable with polycrystalline silicon, especially within the strict limits of highly integrated circuits. The epitaxially grown silicon 74 can be conductively doped with one or more suitable dopants (e.g., phosphorus, boron, etc.).

[0065] Conductive metal-containing material 76 is formed on and directly against epitaxially grown silicon 74. In some embodiments, metal-containing material 76 may include a metal silicide. For example, in some example embodiments, metal-containing material 76 may include, consist essentially of, or consist of cobalt silicide. In some embodiments, metal-containing material 76 may be considered to be directly against the silicon of storage element contact region 34; regardless of whether metal-containing material 76 is directly against epitaxially grown material 74 or directly against semiconductor material 16.

[0066] Conductive material 78 is disposed above metal silicide 76 and in direct contact with metal-containing material 76. Conductive material 78 may include any suitable composition; and in some embodiments may include a metal. For example, in some embodiments, conductive material 78 may include, consist essentially of, or consist of copper, molybdenum, palladium, platinum, ruthenium, tungsten, titanium, and mixtures thereof. In some applications, conductive material 78 may include, consist essentially of, or consist of ruthenium; and such ruthenium may directly contact the upper surface of metal-containing material 76 (e.g., may directly contact the upper surface of metal-containing material 76). In some embodiments, an optional barrier material (similar to that described above with reference to Figure 7-7B The depicted optional barrier material 58 ) may be disposed between the conductive material 78 and the metal-containing material 76 .

[0067] Material 74, metal-containing material 76, and material 78 together form a conductive interconnect 80 coupled to storage element contact region 34. Storage element 82 is formed to be electrically coupled to conductive interconnect 80. The example storage element 82 shown is configured as a capacitor. Each of the storage elements 82 has a node connected to a reference voltage 84. The reference voltage can be ground or any other suitable voltage.

[0068] In some embodiments, other memory elements may be utilized in place of memory element 82. Any suitable device having two or more detectable states may be used as a memory element; including, for example, devices comprising phase change materials, conductive bridging materials, and the like.

[0069] Figure 14-14B The configuration of can be considered to correspond to a region of a memory array 86 (e.g., a DRAM array). The memory array includes a memory cell 88, which includes an access transistor (e.g., a transistor including a gate along one of the word lines 20) coupled to a storage element 82 (e.g., a capacitor). Fig.15 An example memory array 86 is described. The memory array includes digit lines (DL1-DL4) corresponding to digit lines 62, and includes word lines (WL1-WL4) corresponding to word lines 20. Memory cells 88 include transistors coupled to storage elements 82. Each of the memory cells 88 is uniquely addressed via a combination of a word line and a digit line.

[0070] Fig.15 The memory array 86 of is a DRAM array in which each of the memory cells 88 includes a transistor and a capacitor. In other embodiments, configurations similar to those described herein may be utilized in other memory arrays.

[0071] In some embodiments, it may be desirable to form a void (air gap) adjacent to the sidewall of the conductive interconnect 80 ( Fig.14A ). This can improve performance across the memory array by, for example, reducing parasitic capacitance between adjacent devices. Example methods of forming a void adjacent to the sidewalls of a conductive interconnect are described in detail in Figure 16-19 describe.

[0072] See also Fig.16 , showing you can follow Fig. 12A The assembly 10 is at a processing stage of the ...

[0073] See also Fig.17 , material 74, metal-containing material 76, and material 78 are formed within the extended opening 72 ( Fig.16 ) to form a conductive interconnect 80 electrically coupled to the storage element contact region 34.

[0074] See also Fig.18 , remove the sacrificial spacer 98 ( Fig.17 ) to leave voids (air gaps) 92 along the sidewalls of conductive interconnect 80. In the embodiment shown, the voids are along the sidewalls of metal-containing material 78 and metal-containing material 76. In some embodiments, the voids may or may not extend to also be along the sidewalls of epitaxially grown semiconductor material 74. In some embodiments, the voids may extend along metal-containing material 78 without extending along metal-containing material 76.

[0075] See also Fig.19 , a sealing material 94 may be disposed across the assembly 10 to seal the void (air gap) 92. The sealing material is an electrically insulating material and may include any suitable composition. In some example embodiments, the sealing material 94 may include one or more of silicon dioxide, silicon nitride, carbon-doped silicon dioxide, silicon oxynitride, etc. In some embodiments, the sealing material 94 may be a low-k material.

[0076] Fig.19 The interconnect 80 may then be utilized using any suitable processing and storage elements (e.g., Fig.14A The storage element 82 is coupled.

[0077] The assemblies and structures discussed above may be utilized within integrated circuits (the term "integrated circuit" refers to an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multi-layer, multi-chip modules. The electronic system may be any of a wide range of systems such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and the like. The assemblies described herein may be arranged along levels of multi-level (e.g., multi-level, multi-faceted) assemblies. Some levels may include memory, and some levels may include control circuits (e.g., drivers, sense amplifiers, etc.). In some embodiments, the memory may be above the CMOS, where the CMOS is incorporated into the control circuits. The levels may be within separate dies (wafers) of a package, or may be part of the same die (wafer).

[0078] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0079] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. The terms are considered synonymous in the present invention. The use of the term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may provide language changes within the present disclosure to simplify the premise basis within the appended claims, and is not intended to indicate any significant chemical or electrical differences.

[0080] The specific orientations of the various embodiments in the figures are for illustration purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The descriptions and appended claims provided herein relate to any structure having the described relationships between the various features, regardless of whether the structure is in a specific orientation of the drawings or rotated relative to such orientation.

[0081] Unless otherwise specified, the cross-sectional views of the accompanying drawings only show features within the plane of the cross-section, and do not show material behind the plane of the cross-section, in order to simplify the drawing.

[0082] When a structure is referred to as being "on another structure," "adjacent to another structure," or "against another structure," the structure may be directly on the other structure or there may also be intervening structures. Conversely, when a structure is referred to as being "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there are no intervening structures. The terms "directly below," "directly above," and the like do not indicate direct physical contact (unless expressly stated otherwise), but rather indicate upright alignment.

[0083] A structure (eg, layer, material, etc.) may be referred to as "vertically extending" to indicate that the structure extends generally upward from an underlying base (eg, substrate). A vertically extending structure may or may not extend generally orthogonally relative to an upper surface of the base.

[0084] Some embodiments include a method of forming an integrated assembly. A structure is provided, which has an active area pillar. Each active area pillar has a pair of storage element contact areas, and a digit line contact area between the pair of storage element contact areas. The active area pillar includes a semiconductor material. The structure includes a word line extending along the active area pillar and along a first direction. A patterned mold is formed above the structure. The patterned mold has an opening extending through it. The opening is aligned with the digit line contact area. The opening extends into the semiconductor material of the digit line contact area. A carbon-containing polymer is formed in the extended opening. A groove is formed in the patterned mold. The groove extends along a second direction and crosses the digit line contact area. The second direction intersects the first direction. The carbon-containing polymer is removed from above the digit line contact area to reopen the opening. The reopened opening is located at the bottom of the groove and extends into the semiconductor material of the digit line contact area. The surface of the digit line contact area is exposed in the reopened opening. The digit line material is formed in the groove and electrically coupled to the digit line contact area. The digit line material is configured as a digit line extending along the second direction. The storage element is electrically coupled to the storage element contact region.

[0085] Some embodiments include a method of forming an integrated assembly. A structure is provided having active area pillars. Each active area pillar has a pair of storage element contact areas and a digit line contact area between the pair of storage element contact areas. The active area pillars include single crystal semiconductor material. The structure includes a word line extending along the active area pillars and along a first direction. A patterned mold is formed above the structure. The patterned mold has an opening extending therethrough. The opening is aligned with the digit line contact area. The opening extends into the single crystal semiconductor material of the digit line contact area. Sacrificial material is formed in the extended opening. A trench is formed in the patterned mold. The trench extends along a second direction and across the digit line contact area. The second direction intersects the first direction. The sacrificial material is removed from above the digit line contact area to reopen the opening. The reopened opening is located at the bottom of the trench and extends into the semiconductor material of the digit line contact area. The surface of the digit line contact area is exposed in the reopened opening. Silicon is epitaxially grown from the exposed surface of the digit line contact area. The digit line material is formed in the trench and electrically coupled to the epitaxially grown silicon. The digit line material is configured as a digit line extending along a second direction. The storage element is electrically coupled to the storage element contact region.

[0086] Some embodiments include an integrated assembly having active area pillars. Each of the active area pillars has a contact region. The contact region includes a pair of storage element contact regions and includes a digit line contact region between the pair of storage element contact regions. The active area pillars include silicon. A word line extends along the active area pillars and along a first direction. Cobalt silicide is directly against the silicon of one or more of the contact regions. A metal-containing material is directly against the cobalt silicide. The digit line is electrically coupled to the digit line contact region and extends along a second direction that intersects the first direction. The storage element is electrically coupled to the storage element contact region.

Claims

1. An integrated assembly comprising: Active area pillars; Each of said active area pillars has a contact region associated therewith; The contact region is associated with each of the active area pillars, each of the active area pillars including a pair of storage element contact regions and a digit line contact region between the storage element contact regions of the pair; the active area pillars comprising silicon; A word line extending along the active area pillar and along a first direction; cobalt silicide directly against the silicon in one or more of the contact regions; a metal-containing material directly against the cobalt silicide; a digit line electrically coupled to the digit line contact region and extending along a second direction intersecting the first direction; as well as A storage element is electrically coupled to the storage element contact regions of the pair.

2. The integrated assembly of claim 1, wherein the metal-containing material comprises one or more of copper, molybdenum, palladium, platinum, ruthenium, tungsten, and titanium.

3. The integrated assembly of claim 1, wherein the metal-containing material comprises ruthenium.

4. The integrated assembly of claim 1 wherein the cobalt silicide is directly against the silicon of the digit line contact region.

5. The integrated assembly of claim 1 wherein the cobalt silicide is directly against the silicon of the storage element contact region.

6. The integrated assembly of claim 1 wherein the cobalt silicide is directly against the silicon of the digit line contact area and directly against the silicon of the storage element contact area.

7. The integrated assembly of claim 1 wherein the silicon is single crystal silicon.

8. The integrated assembly of claim 1, wherein the storage element is a capacitor.

9. The integrated assembly of claim 1, wherein the metal-containing material consists of an interconnect that electrically couples the storage element to the storage element contact region; and wherein a void is directly adjacent to the metal-containing material.

10. The integrated assembly of claim 1 wherein the active area pillars consist of access transistors; wherein the access transistors and storage elements are incorporated into memory cells; and wherein each of the memory cells is uniquely addressed via a combination of one of the word lines and one of the digit lines.

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