OTP memory structure
By designing the gate oxide layer in the OTP memory structure, the problem of low programming efficiency of OTP memory is solved, and more efficient programming and a more controllable fuse structure are achieved.
Patent Information
- Application Number
- CN202510039588.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-09
- Publication Date
- 2025-05-06
AI Technical Summary
When programming existing OTP memory devices, the breakdown points of the gate oxide layer are randomly distributed, resulting in low programming efficiency.
An OTP memory structure is designed in which the gate oxide layer is thin at the recessed region and the first gate structure is isolated from the shallow trench across the active region, which is used to improve programming efficiency.
Through the thinner design of the gate oxide layer in the recessed area, the programming efficiency of the OTP memory is improved, and the physical position of the fuse is concentrated in the recessed area, making the fuse structure more convergent and controllable.
Smart Images
Figure CN119947095A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of semiconductor manufacturing, and in particular to an OTP memory structure. Background Art
[0002] OTP memory devices (one-time programmable memory devices) are non-volatile memories and are a special type of read-only memory. Because they only allow data to be written once, they have the advantages of low power consumption, small area, and high security. They are widely used in fields that require reliable and repeated reading of data, such as verification code storage and secure identity card (ID) storage.
[0003] In the related art, an OTP memory device generally includes a substrate and a MOS transistor disposed on the substrate, wherein the MOS transistor includes a gate, a gate oxide layer, and a source and a drain located below and on both sides of the gate oxide layer. During programming, a short voltage is applied between the gate and the source or between the gate and the drain. When the voltage exceeds the breakdown voltage of the gate oxide layer, the gate oxide layer is broken down and programming is completed. At present, the logic architecture NVM (non-volatile memory) design based on anti-fuse mostly uses oxide layer and HK material breakdown to realize anti-fuse, wherein the anti-fuse is composed of two transistors, one is a programming transistor and the other is a read / select transistor.
[0004] However, during the use of the OTP memory device, the breakdown points generated when the gate oxide layer is broken down are randomly distributed in any area of the gate oxide layer, resulting in low programming efficiency. Summary of the invention
[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an OTP memory structure for solving the problem of low programming efficiency of the existing OTP memory.
[0006] To achieve the above-mentioned object and other related objects, the present invention provides an OTP memory structure, the structure comprising: a substrate, a first gate structure formed on the substrate, a second gate structure and active regions located on both sides of the second gate structure,
[0007] A shallow trench isolation structure is formed in the substrate, the shallow trench isolation structure isolates the active area, and a concave area is provided at the junction between the shallow trench isolation structure and the active area;
[0008] One side of the first gate structure crosses the recessed area and extends to the surface of the shallow trench isolation structure adjacent thereto, and the other side of the first gate structure is spaced apart from the second gate structure;
[0009] The first gate structure is coupled to the programming line and includes at least a gate oxide layer, and the thickness of the gate oxide layer formed in the recessed area is less than the thickness of the gate oxide layer formed in the non-recessed area.
[0010] Optionally, the first gate structure further includes a high-K dielectric layer, and the high-K dielectric layer is formed on a surface of the gate oxide layer.
[0011] Optionally, the first gate structure further includes a polysilicon layer, which is formed on the surface of the gate oxide layer when the first gate structure only includes the gate oxide layer, and is formed on the surface of the high-K dielectric layer when the first gate structure further includes the high-K dielectric layer.
[0012] Optionally, the number of the first gate structures is at least 2 and they are arranged at intervals.
[0013] Optionally, the second gate structure includes a gate oxide layer and a polysilicon layer formed on a surface of the gate oxide layer, and the second gate structure is coupled to a word line.
[0014] Optionally, the second gate structure further includes the high-K dielectric layer. In this case, the high-K dielectric layer is formed on a surface of the gate oxide layer, and the polysilicon layer is formed on a surface of the high-K dielectric layer.
[0015] Optionally, the second gate structure is coupled to the word line through a contact hole.
[0016] Optionally, the number of the second gate structures is at least 2, and the second gate structures are arranged at intervals, and each of the second gate structures is located in a region between the first gate structures.
[0017] Optionally, a source and a drain are formed in the active region between the two second gate structures, and the source or the drain is coupled to a bit line.
[0018] Optionally, the source or the drain is coupled to the bit line through the contact hole.
[0019] Optionally, the gate oxide layer is made of silicon oxide.
[0020] Optionally, applicable technology nodes include 55nm, 40nm, and less than or equal to 28nm.
[0021] As described above, the OTP memory structure of the present invention utilizes the characteristic that the gate oxide layer is relatively thin in the divot, and the first gate structure (that is, the gate coupled to the programming line) spans the active area and the shallow trench isolation structure, so that the formed memory can improve the programming efficiency. Moreover, the physical position of the fuse will be concentrated in the divot area, so the fuse structure is more convergent and controllable. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 Shown is a schematic layout diagram of the OTP memory structure of the present invention.
[0023] Figure 2 Shown is a schematic diagram of the recessed area of the present invention. DETAILED DESCRIPTION
[0024] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0025] See also Figure 1 to Figure 2 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.
[0026] like Figure 1 and Figure 2 As shown, this embodiment provides an OTP memory structure, the structure comprising: a substrate, a first gate structure formed on the substrate, a second gate structure and active regions located on both sides of the second gate structure,
[0027] A shallow trench isolation structure is formed in the substrate, the shallow trench isolation structure isolates the active area, and a concave area is provided at the junction between the shallow trench isolation structure and the active area;
[0028] One side of the first gate structure crosses the recessed area and extends to the surface of the shallow trench isolation structure adjacent thereto, and the other side of the first gate structure is spaced apart from the second gate structure;
[0029] The first gate structure is coupled to the programming line and includes at least a gate oxide layer, and the thickness of the gate oxide layer formed in the recessed area is less than the thickness of the gate oxide layer formed in the non-recessed area.
[0030] In this embodiment, the material of the semiconductor substrate includes Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or III / V compound semiconductors, and also includes multilayer structures formed by these semiconductor structures, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI). Moreover, it should be noted that in Figure 2 The area indicated by the black dot below the first gate structure is the area where the recessed area is located.
[0031] Specifically, the first gate structure further includes a high-K dielectric layer, and the high-K dielectric layer is formed on the surface of the gate oxide layer. In this embodiment, the high-K dielectric layer includes hafnium dioxide.
[0032] Specifically, the first gate structure also includes a polysilicon layer, which is formed on the surface of the gate oxide layer when the first gate structure only includes the gate oxide layer, and is formed on the surface of the high-K dielectric layer when the first gate structure also includes the high-K dielectric layer.
[0033] Specifically, the number of the first gate structures is at least 2 and they are arranged at intervals.
[0034] Specifically, the second gate structure includes a gate oxide layer and a polysilicon layer formed on a surface of the gate oxide layer, and the second gate structure is coupled to a word line.
[0035] Specifically, the second gate structure further includes the high-K dielectric layer. In this case, the high-K dielectric layer is formed on the surface of the gate oxide layer, and the polysilicon layer is formed on the surface of the high-K dielectric layer.
[0036] Specifically, the second gate structure is coupled to the word line through a contact hole.
[0037] Specifically, the number of the second gate structures is at least 2, and the second gate structures are arranged at intervals, and each of the second gate structures is located in a region between the first gate structures.
[0038] Specifically, a source and a drain are formed in the active region between the two second gate structures, and the source or the drain is coupled to a bit line.
[0039] Specifically, the source or the drain is coupled to the bit line through the contact hole.
[0040] Specifically, the material of the gate oxide layer includes silicon oxide.
[0041] Specifically, applicable technology nodes include 55nm, 40nm and less than or equal to 28nm.
[0042] In summary, the OTP memory structure of the present invention utilizes the characteristic that the gate oxide layer is thinner in the divot, and the first gate structure (that is, the gate coupled to the programming line) spans the active area and the shallow trench isolation structure, so that the formed memory can improve the programming efficiency, and the physical position of the fuse is concentrated in the divot area, so the fuse structure is more convergent and controllable. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0043] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. An OTP memory structure, characterized in that: The structure includes: a substrate, a first gate structure formed on the substrate, a second gate structure, and active regions located on both sides of the second gate structure. A shallow trench isolation structure is formed in the substrate, the shallow trench isolation structure isolates the active area, and a concave area is provided at the junction between the shallow trench isolation structure and the active area; One side of the first gate structure crosses the recessed area and extends to the surface of the shallow trench isolation structure adjacent thereto, and the other side of the first gate structure is spaced apart from the second gate structure; The first gate structure is coupled to the programming line and includes at least a gate oxide layer, and the thickness of the gate oxide layer formed in the recessed area is less than the thickness of the gate oxide layer formed in the non-recessed area.
2. The OTP memory structure according to claim 1, characterized in that: The first gate structure further includes a high-K dielectric layer, and the high-K dielectric layer is formed on the surface of the gate oxide layer.
3. The OTP memory structure according to claim 2, characterized in that: The first gate structure also includes a polysilicon layer, which is formed on the surface of the gate oxide layer when the first gate structure only includes the gate oxide layer, and is formed on the surface of the high-K dielectric layer when the first gate structure also includes the high-K dielectric layer.
4. The OTP memory structure according to claim 1, characterized in that: The number of the first gate structures is at least 2 and they are arranged at intervals.
5. The OTP memory structure according to claim 4, characterized in that: The second gate structure includes a gate oxide layer and a polysilicon layer formed on a surface of the gate oxide layer, and the second gate structure is coupled to a word line.
6. The OTP memory structure according to claim 5, characterized in that: The second gate structure further includes the high-K dielectric layer. In this case, the high-K dielectric layer is formed on the surface of the gate oxide layer, and the polysilicon layer is formed on the surface of the high-K dielectric layer.
7. The OTP memory structure according to claim 5, characterized in that: The second gate structure is coupled to the word line through a contact hole.
8. The OTP memory structure according to claim 5, characterized in that: The number of the second gate structures is at least 2 and they are arranged at intervals, and each of the second gate structures is located in a region between the first gate structures.
9. The OTP memory structure according to claim 5, characterized in that: A source and a drain are formed in the active region between the two second gate structures, and the source or the drain is coupled to a bit line.
10. The OTP memory structure according to claim 9, characterized in that: The source or the drain is coupled to the bit line through the contact hole.
11. The OTP memory structure according to claim 1, characterized in that: The material of the gate oxide layer includes silicon oxide.
12. The OTP memory structure according to claim 1, characterized in that: Applicable technology nodes include 55nm, 40nm and less than or equal to 28nm.