Three-dimensional memory device and manufacturing method thereof

Abstract

Embodiments of three-dimensional (3D) memory devices and methods of fabricating the same are disclosed. In some embodiments, the disclosed 3D memory device includes: a stack structure including a plurality of dielectric layers and conductive layers alternately stacked in a vertical direction; an array of channel structures, each channel structure vertically penetrating through the stack structure, each channel structure comprising a functional layer and a channel layer; and a plurality of isolation structures extending in parallel in the first lateral direction and vertically located in the upper portion of the stack structure, each isolation structure being in contact with the channel layers of two adjacent rows of channel structures.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor technology, and more particularly, to a three-dimensional (3D) memory device and a manufacturing method for forming a three-dimensional (3D) memory device. Background Art

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches a lower limit, planar processes and manufacturing techniques become challenging and costly. As a result, the storage density for planar memory cells approaches an upper limit. Three-dimensional (3D) memory architectures can address the density limitations in planar memory cells.

[0003] As semiconductor technology advances, 3D memory devices (e.g., 3D NAND memory devices) continue to reduce costs and increase capacity. The density of memory cells in the horizontal plane continues to shrink. The top select gate (TSG) is a necessary structure for NAND memory devices. Since TSG cuts are required between memory strings, the memory cell density of NAND memory devices can be greatly reduced. Summary of the invention

[0004] Embodiments of three-dimensional (3D) memory devices and methods of making the same are disclosed herein.

[0005] One aspect of the present disclosure provides a semiconductor structure, comprising: a stacked structure, the stacked structure comprising a plurality of dielectric layers and conductive layers alternately stacked in a vertical direction; an array of channel structures, each channel structure vertically penetrating the stacked structure, each channel structure comprising a functional layer and a channel layer; and a plurality of isolation structures, the plurality of isolation structures extending in parallel along a first lateral direction and vertically located in an upper portion of the stacked structure, each isolation structure contacting the channel layers of two adjacent rows of channel structures.

[0006] In some embodiments, each isolation structure partially covers two adjacent rows of channel structures located in the lower portion of the stack structure.

[0007] In some embodiments, the plurality of isolation structures include: a plurality of first isolation structures, each of the first isolation structures separating the conductive layer of the upper portion of the stack structure into sub-blocks.

[0008] In some embodiments, the isolation structure contacts curved side surfaces of channel layers of two adjacent rows of channel structures located in an upper portion of the stack structure.

[0009] In some embodiments, the isolation structure contacts the filling structures of two adjacent rows of the channel structures located in the upper portion of the stack structure.

[0010] In some embodiments, a column of channel structures extending along the second lateral direction and located on a same side of the first isolation structure are connected to a common bit line.

[0011] In some embodiments, the multiple isolation structures also include: multiple second isolation structures, each second isolation structure extending along the first lateral direction without separating the conductive layer of the upper portion of the stacked structure; wherein the multiple first isolation structures and the multiple second isolation structures are alternately arranged along the second lateral direction.

[0012] In some embodiments, the plurality of second isolation structures each include a plurality of second isolation segments extending discontinuously along the first lateral direction.

[0013] In some embodiments, a first subset of a column of channel structures extending along the second lateral direction and contacting the first isolation structure is connected to the first common bit line; and a second subset of the column of channel structures contacting the second isolation structure is connected to the second common bit line.

[0014] In some embodiments, the array of channel structures includes: a dummy channel structure contacting a corner of the second isolation section.

[0015] In some embodiments, the semiconductor structure also includes: a plurality of gate line structures extending in parallel along a first lateral direction and vertically penetrating the stacked structure; wherein a first number of isolation structures between adjacent gate line structures plus one is half of a second number of rows of channel structures between adjacent gate line structures.

[0016] In some embodiments, a lateral cross-section of a functional layer of the channel structure located in an upper portion of the stack structure has a partial ring shape; and both lateral ends of the functional layer of the partial ring shape are in contact with the isolation structure.

[0017] In some embodiments, a lateral cross-section of a channel layer of a channel structure located in an upper portion of the stack structure has a partial ring shape; and both lateral ends of the partial ring-shaped channel layer are in contact with the isolation structure.

[0018] In some embodiments, the partial annular shape is larger than one-third of annular.

[0019] In some embodiments, the depth of the isolation structure is greater than the total thickness of the top pair of dielectric and conductive layers and less than the total thickness of the top seven pairs of dielectric and conductive layers.

[0020] Another aspect of the present disclosure provides a method for forming a semiconductor structure, comprising: forming a dielectric stack structure; forming an array of channel structures, each channel structure vertically penetrating the dielectric stack structure, each channel structure comprising a functional layer and a channel layer; transforming the dielectric stack structure into a stack structure comprising a plurality of alternately stacked dielectric layers and conductive layers; removing the channel structures and portions of the stack structure located in an upper portion of the stack structure to form a plurality of grooves extending in parallel along a first lateral direction, each groove exposing channel layers of two adjacent rows of channel structures located in an upper portion of the stack structure; and forming a plurality of isolation structures in the grooves, each isolation structure contacting the channel layers of two adjacent rows of channel structures.

[0021] In some embodiments, each isolation structure is formed to partially cover two adjacent rows of channel structures located in a lower portion of the stack structure.

[0022] In some embodiments, forming the plurality of trenches includes removing a portion of the functional layer of the channel structure in an upper portion of the stacked structure.

[0023] In some embodiments, forming the plurality of trenches further comprises removing a portion of a channel layer of the channel structure located in an upper portion of the stacked structure.

[0024] In some embodiments, forming the plurality of isolation structures includes forming the plurality of isolation structures in the trench, each isolation structure contacting a curved side surface of the channel layers of two adjacent rows of channel structures located in the upper portion of the stack structure.

[0025] In some embodiments, forming the plurality of isolation structures includes forming a plurality of isolation structures in the trench, each isolation structure being in contact with the filling structures of two adjacent rows of the channel structures located in the upper portion of the stack structure.

[0026] In some embodiments, forming the plurality of trenches includes forming a plurality of first trenches, each of the first trenches separating the conductive layer of the upper portion of the stack structure into sub-blocks.

[0027] In some embodiments, the method further includes forming a plurality of bit lines extending in parallel along the second lateral direction, each bit line being connected to a column of channel structures extending along the second lateral direction and located on a same side of the isolation structure.

[0028] In some embodiments, the method also includes: forming a plurality of second trenches, each second trench extending along the first lateral direction without separating the conductive layer of the upper portion of the stacked structure; and forming a plurality of second isolation structures in the second trenches, wherein the plurality of first isolation structures and the plurality of second isolation structures are alternately arranged along the second lateral direction.

[0029] In some embodiments, forming the plurality of second trenches includes: forming a plurality of second trench sections extending discontinuously along the first lateral direction; and forming the plurality of second isolation structures includes: forming a plurality of second isolation sections in the plurality of second trench sections.

[0030] In some embodiments, the method further includes forming a dummy channel structure contacting a corner of the second isolation section.

[0031] In some embodiments, the method also includes: forming a dielectric stack structure includes: forming a plurality of dielectric layers and sacrificial layers alternately stacked in a vertical direction; transforming the dielectric stack structure into a stack structure includes: forming a plurality of gate line structures extending in parallel along a first lateral direction and vertically passing through the dielectric stack structure, and replacing the sacrificial layer with a conductive layer; wherein the first number of isolation structures located between adjacent gate line structures plus one is equal to the second number of rows of channel structures located between adjacent gate line structures.

[0032] Another aspect of the present disclosure provides a semiconductor device, comprising: a plurality of isolation structures extending in parallel along a first lateral direction and vertically located in an upper portion of a stacked structure; and an array of channel structures, each channel structure vertically penetrating the stacked structure and comprising: a lower channel portion having a cylindrical shape in the lower portion of the stacked structure and an upper channel portion having a partial cylindrical shape in the upper portion of the stacked structure and contacting the corresponding isolation structure.

[0033] Other aspects of the present disclosure can be understood by those skilled in the art based on the description, claims and drawings of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those skilled in the relevant art to make and use the present disclosure.

[0035] Figure 1 A schematic diagram showing a portion of a 3D memory device according to some embodiments of the present disclosure is shown in an enlarged top view.

[0036] Figure 2 A schematic diagram showing a portion of a 3D memory device according to some embodiments of the present disclosure is shown in an enlarged top view.

[0037] Figure 3 A schematic diagram showing a portion of a 3D memory device according to some embodiments of the present disclosure is shown in an enlarged top view.

[0038] Figure 4A schematic diagram showing a portion of a 3D memory device according to some embodiments of the present disclosure is shown in an enlarged top view.

[0039] Figure 5 A schematic diagram of a portion of a 3D memory device 600 according to some embodiments of the present disclosure is shown in an enlarged top view.

[0040] Figure 6 A schematic diagram of a 3D memory device according to some embodiments of the present disclosure is shown in a cross-sectional side view.

[0041] Figure 7 A schematic diagram of a portion of a 3D memory device 600 according to some embodiments of the present disclosure is shown in an enlarged top view.

[0042] Figure 8 A schematic diagram of a 3D memory device according to some embodiments of the present disclosure is shown in a cross-sectional side view.

[0043] Fig. 9 A block diagram of a system having a memory device according to some aspects of the present disclosure is shown.

[0044] Fig. 10A A diagram of an exemplary memory card having a memory device in accordance with some embodiments is shown.

[0045] Fig. 10B A diagram of an exemplary solid state drive (SSD) having memory in accordance with some embodiments is shown.

[0046] Fig.11 A flow chart of a method for forming a 3D memory device according to some embodiments of the present disclosure is shown.

[0047] Figure 12-18 The cross-sectional view shows a Fig.11 Schematic diagram of a 3D memory device at certain fabrication stages of the method shown in FIG.

[0048] Fig.19 A top view of a 3D memory device according to some embodiments of the present disclosure is shown.

[0049] Fig. 20 A perspective view of a portion of a 3D memory array structure according to some embodiments of the present disclosure is shown.

[0050] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0051] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in various other applications.

[0052] It should be noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0053] In general, a term can be understood, at least in part, from usage in context. For example, depending, at least in part, on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending, at least in part, on the context, terms such as "a," "an," or "the" can also be understood to convey singular usage or to convey plural usage.

[0054] It should be readily understood that the meanings of “on,” “over,” and “on…” in the present disclosure should be interpreted in the broadest manner, so that “on…” not only means “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over…” or “on…” not only means “above something” or “on something,” but also can include the meaning of “above something” or “on something” with no intervening features or layers therebetween (i.e., directly on something).

[0055] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (or some) elements or features as shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the drawings. The device may be oriented in other ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0056] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0057] As used herein, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entire underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be located between the top surface and the bottom surface of the continuous structure or between any pair of lateral planes at the top surface and the bottom surface. A layer may extend laterally, vertically and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above it and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and a contact layer (wherein contacts, interconnects and / or vias are formed) and one or more dielectric layers.

[0058] As used herein, the term "nominal / nominal" refers to an expected value or target value for a characteristic or parameter set for a component or process operation during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. The range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" refers to a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "approximately" may refer to a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0059] As used herein, the term "3D memory device" refers to a semiconductor device having a vertically oriented string of memory cell transistors (i.e., a region referred to herein as a "memory string", such as a NAND string) on ​​a laterally oriented substrate, such that the memory string extends in a vertical direction relative to the substrate. As used herein, the term "vertical / vertically" means nominally perpendicular to a lateral surface of the substrate.

[0060] As described above, 3D NAND memory devices continue to reduce costs and increase capacity by compressing the density of memory cells in the horizontal plane. However, as a necessary structure for NAND memory devices, the top select gate (TSG) structure located between the storage strings has a negative impact on the density of the memory cells of the NAND memory device. Specifically, a method of TSG structure includes using a stack of multi-row channel structures, arranging a row of dummy channel structures between every four rows of channel structures, and separating the stack of gate layers to form a TSG structure. The first method is low cost and simple manufacturing process, but the loss per wafer die (DPW) is high. Another method of TSG structure includes adding additional TSG stacking on the upper layer of the channel structure, and interconnecting the channel structure through a small aperture TSG channel. Due to the limited space of the small aperture, a wavy TSG structure is allowed to save area on the horizontal plane. However, the second method is costly and has a complex manufacturing process. In addition, the structure usually uses four rows of channel structures as a group, and each bit line and / or TSG in the same group controls two channel structures. Such an arrangement may cause crosstalk during programming and reading, which is detrimental to the reliability of the 3D NAND memory device.

[0061] Therefore, according to various embodiments of the present disclosure, a 3D memory device and a method for manufacturing the same are provided to solve the above-mentioned problems. Specifically, in some embodiments, two rows of channel structures can be used as a group. In this way, the bit line connection does not require a double pattern, but can be implemented by a single pattern. That is, a layer of TSG structure plus a bit line can control a single row of channel structures, thereby reducing interference during programming and reading and reducing metal wiring. In addition, in some embodiments, the channel structure corresponding to the TSG structure can be designed to have a partial circular shape. That is, the current switch of the channel structure can be controlled by a partial circular gate electrode of the TSG. In this way, there is no need to design a segmented area as a dummy channel structure. The disclosed design of the TSG isolation function can be manufactured by a simple process without increasing the process cost and / or manufacturing area.

[0062] Fig. 9 A block diagram of a system 900 having a memory device according to some aspects of the present disclosure is shown. The system 900 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game controller, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device therein. Fig. 9As shown, the system 900 may include a host 908 and a memory system 902 having one or more memory devices 904 and a memory controller 906. The host 908 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 908 may be configured to send data to the memory device 904 or receive data from the memory device 904.

[0063] The memory device 904 may be any memory device disclosed herein, such as a NAND flash memory device. Consistent with the scope of the present disclosure, the memory controller 906 may control multi-pass programming of the memory device 904 so that in a non-last programming pass in the multi-pass programming, an NGS operation is implemented for all memory cells (even those memory cells that have passed the corresponding verification operation). A peripheral circuit (e.g., a word line driver) may apply a low voltage (e.g., a ground (GND) voltage) to the DSG of each memory string coupled to a selected word line, and may apply a low voltage or a negative voltage to the selected word line to implement an NGS operation for all memory cells coupled to the selected word line during a non-last programming pass.

[0064] According to some embodiments, the memory controller 906 is coupled to the memory device 904 and the host 908, and is configured to control the memory device 904. The memory controller 906 can manage data stored in the memory device 904 and communicate with the host 908. In some embodiments, the memory controller 906 is designed to work in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 906 is designed to work in a high duty cycle environment SSD or embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smart phones, tablets, laptops, etc. and enterprise storage arrays. The memory controller 906 can be configured to control the operation of the memory device 904 (e.g., read operation, erase operation, and program operation). The memory controller 906 may also be configured to manage various functions regarding data stored or to be stored in the memory device 904, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the memory controller 906 is also configured to process error correction code (ECC) regarding data read from or written to the memory device 904. The memory controller 906 may also perform any other appropriate functions, such as programming the memory device 904. The memory controller 906 may communicate with an external device (e.g., a host 908) according to a specific communication protocol. For example, the memory controller 906 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, etc.

[0065] The memory controller 906 and the one or more memory devices 904 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage device (UFS) package or an eMMC package). That is, the memory system 902 may be implemented and packaged into different types of terminal electronic products. Fig. 10AIn one example shown, the memory controller 906 and the single memory device 904 may be integrated into the memory card 1002. The memory card 1002 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1002 may also include a computer that connects the memory card 1002 to a host (e.g., Fig. 9 The host 908 in the memory card connector 1004 is coupled. Fig. 10B In another example shown, the memory controller 906 and the plurality of memory devices 904 may be integrated into the SSD 1006. The SSD 1006 may also include a processor that interfaces the SSD 1006 with a host (e.g., Fig. 9 In some implementations, the storage capacity and / or operating speed of the SSD 1006 is greater than the storage capacity and / or operating speed of the memory card 1002.

[0066] Fig.19 1 shows a top view of a 3D memory device 1900 according to some embodiments of the present disclosure. The 3D memory device 1900 may be a memory chip (package), a memory chip, or any portion of a memory chip, and may include one or more memory planes 1901, each of which may include a plurality of memory blocks 1903. The same and simultaneous operations may occur at each memory plane 1901. The memory block 1903, which may be megabytes (MB) in size, may be the minimum size for performing an erase operation. Fig.19 As shown, the 3D memory device 1900 includes four memory planes 1901, and each memory plane 1901 includes six memory blocks 1903. Each memory block 1903 may include a plurality of memory cells, wherein each memory cell may be addressed by interconnections (e.g., bit lines and word lines). The bit lines and word lines may be arranged vertically (e.g., in rows and columns, respectively) to form an array of metal lines. Fig.19 , the direction of the word line is marked as the X direction, and the direction of the bit line is marked as the Y direction. In the present disclosure, the memory block 1903 is also referred to as a "memory array" or "array". The memory array is a core area in a memory device that performs a storage function.

[0067] The 3D memory device 1900 may include a peripheral region 1905, i.e., an area surrounding the storage plane 1901. The peripheral region 1905 may contain many digital, analog, and / or mixed signal circuits to support the functions of the memory array, such as page buffers, row and column decoders, and sense amplifiers. As will be apparent to one of ordinary skill in the art, the peripheral circuits use active semiconductor devices and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc. It should be noted that Fig.19 The arrangement of the memory planes 1901 in the 3D memory device 1900 and the arrangement of the memory blocks 1903 in each memory plane 1901 shown in FIG. 1 are provided only as examples, which do not limit the scope of the present disclosure.

[0068] Fig. 20 A perspective view of a portion of a 3D memory array structure 2000 according to some embodiments of the present disclosure is shown. The memory array structure 2000 includes a substrate 2330, an insulating film 2331 located on the substrate 2330, a tier or multiple tiers of bottom select gates (BSG) 2332 located on the insulating film 2331, and multiple tiers of control gates 2333, also referred to as "word lines (WL)", stacked on top of the BSG 2332 to form a stacked structure 2335 of alternating conductive layers and dielectric layers. For clarity, Fig. 20 The dielectric layers adjacent to the various control gate layers are not shown.

[0069] The control gates 2333 of each layer are separated by gap structures 2216-1 and 2216-2 passing through the stack structure 2335. The memory array structure 2000 may include one or more layers of top select gates (TSGs) 2334 located above the stack of control gates 2333. The stack of TSGs 2334, control gates 2333, and BSGs 2332 is also referred to as a "gate structure." The memory array structure 2000 also includes memory strings 2212 and doped source line regions 2344 in portions of the substrate 2330 located between adjacent BSGs 2332. Each memory string 2212 includes a channel hole 2336 extending through an insulating film 2331 and a stack structure 2335 of alternating conductive layers and dielectric layers. The memory string 2212 may also include a memory film 2337 (also referred to as a "functional layer") located on the sidewalls of the channel hole 2336, a channel layer 2338 located above the memory film 2337, and a core filling film 2339 surrounded by the channel layer 2338. The memory cell 2340 may be formed at the intersection of the control gate 2333 and the memory string 2212. The memory array structure 2000 also includes a plurality of bit lines (BL) 2341 connected to the memory string 2212 located above the TSG 2334. The memory array structure 2000 may include a plurality of metal interconnect lines 2343 connected to the gate structure through a plurality of contact structures 2214. The edge of the stacked structure 2335 is configured as a stepped structure to allow electrical connection to each layer of the gate structure.

[0070] exist Fig. 20 , for illustrative purposes, three layers of control gates 2333-1, 2333-2, and 2333-3 are shown together with a layer of TSG 2334 and a layer of BSG 2332. In this example, each memory string 2212 can include three memory cells 2340-1, 2340-2, and 2340-3, corresponding to the control gates 2333-1, 2333-2, and 2333-3, respectively. In some embodiments, the number of control gates and the number of memory cells can be more than three to increase storage capacity. The memory array structure 2000 can also include other structures, such as TSG cuts, common source contacts, and dummy channel structures. For simplicity, Fig. 20 These structures are not shown in FIG.

[0071] refer to Figure 1 , showing a portion 100 (eg, Fig. 20 2008). As shown in the figure, a plurality of slits may extend in parallel laterally along the word line direction (ie, the X direction). A gate slit (GLS) structure 130 may be formed in each slit to divide the memory array into a plurality of memory fingers 110.

[0072] Each storage finger 110 may include an even number (e.g., 8, 16, 32, etc.) of rows of channel structures 150 arranged between two adjacent GLS structures 130 in a staggered manner. A plurality of top select gate (TSG) cutouts (also referred to as "isolation structures") 190 may be located between the channel structures 150 of adjacent rows. The plurality of TSG cutouts 190 may extend in parallel laterally along the word line direction (i.e., the X direction) and may extend vertically in the upper portion of the stacked structure of the 3D memory device. Each TSG cutout 190 may contact the channel layer of the channel structures 150 of two adjacent rows. The conductive layer located in the upper portion of the stacked structure of the 3D memory device may be divided into a plurality of sub-blocks 120 by the TSG cutouts 190. That is, the channel structures 150 of two adjacent rows located between two adjacent TSG cutouts 190 may share one sub-block 120. In some embodiments, the first number of TSG cuts 190 located between adjacent gate slot structures 130 plus one is half the second number of rows of channel structures 150 located between adjacent gate slot structures 130 .

[0073] refer to Figure 2 , a schematic diagram of a portion 200 of the portion 100 of a 3D memory device according to some embodiments of the present disclosure is shown in an enlarged top view. As shown in the figure, each column of channel structures 150 extending along the bit line direction (i.e., the Y direction) and located on the same side of the TSG cut 190 can be connected to a common bit line 240. For example, a first column of channel structures 150 located on the upper side of the TSG cut 190 can be connected to a first common bit line 240-1, and a second column of channel structures 150 located on the lower side of the TSG cut 190 can be connected to a second common bit line 240-2.

[0074] refer to Figure 3 , showing a portion 300 (eg, Fig. 20 2008). As shown in the figure, a plurality of slits may extend in parallel laterally along the word line direction (ie, the X direction). A gate slit (GLS) structure 130 may be formed in each slit to divide the memory array into a plurality of memory fingers 110.

[0075] Each memory finger 110 may include an even number (e.g., 8, 16, 32, etc.) of rows of channel structures 150 arranged between two adjacent GLS structures 130 in a staggered manner. A plurality of first top select gate (TSG) cutouts (also referred to as "first isolation structures") 390 and second top select gate (TSG) cutouts 380 (also referred to as "second isolation structures") may be located between adjacent rows of channel structures 150. A plurality of first TSG cutouts 390 and second TSG cutouts 380 are alternately arranged along the bit line direction (i.e., the Y direction). A plurality of first TSG cutouts 390 and second TSG cutouts 380 may extend in parallel laterally along the word line direction (i.e., the X direction), and may extend vertically in the upper portion of the stacked structure of the 3D memory device. Each second TSG cutout 380 may include a plurality of second TSG cutout segments (also referred to as "second isolation segments") extending discontinuously along the word line direction (i.e., the X direction).

[0076] Each first TSG cutout 390 or second TSG cutout 380 may contact the channel layer of the channel structure 150 of two adjacent rows. It should be noted that the dummy channel structure 350 may contact the corner of the second TSG cutout section. The conductive layer located in the upper portion of the stacked structure of the 3D memory device may be divided into a plurality of sub-blocks 320 by the first TSG cutout 390, while the discontinuous second TSG cutout section of the second TSG cutout 380 does not separate the conductive layer. That is, the channel structures 150 of the adjacent four rows located between the adjacent two first TSG cutouts 390 may share one sub-block 320.

[0077] refer to Figure 4 , a schematic diagram of a portion 400 of the portion 200 of a 3D memory device according to some embodiments of the present disclosure is shown in an enlarged top view. In some embodiments, a first subset of a column of channel structures extending along a second lateral direction and in contact with a first isolation structure is connected to a first common bit line, and a second subset of the column of channel structures in contact with a second isolation structure is connected to a second common bit line. For example, Figure 4 As shown, a subset of the first column channel structures 150 contacting the second TSG cut structure 380 may be connected to the first common bit line 440 - 1 , and a subset of the first column channel structures 150 contacting the first TSG cut structure 390 may be connected to the second common bit line 440 - 2 .

[0078] refer to Figure 6 , a schematic diagram of a 3D memory device 600 according to some embodiments of the present disclosure is shown in a cross-sectional side view. It should be noted that the 3D memory device 600 can be along Figure 1 AA' line or along Figure 3 BB' line shown. Figure 5, a schematic diagram showing a portion 500 of a 3D memory device 600 in an enlarged top view according to some embodiments of the present disclosure.

[0079] In some embodiments, Figure 6 As shown, a stack structure 620 including a plurality of dielectric layers 622 and conductive layers 624 alternately stacked in a vertical direction may be located on a substrate 610. Gate gap (GLS) structures 630 may each extend vertically through the stack structure 620 into the substrate 610 and extend laterally along the word line direction (X direction). Between adjacent GLS structures 630, a plurality of channel structures 650 may each extend vertically through the stack structure 620 into the substrate 610.

[0080] like Figure 5 and Figure 6 As shown, each channel structure 650 may include a high-K dielectric layer 530 located on the sidewall of the channel hole, a functional layer (or storage film) 540 covering the high-K dielectric layer 530, a channel layer 550 covering the functional layer 540, and a filling structure 560 surrounded by the channel layer 550. In some embodiments, the functional layer 540 may include a barrier layer 542, a storage layer 544, and a tunneling layer 546.

[0081] like Figure 5 and 6 As shown, TSG cutout 590 (eg, Figure 1-Figure 4 The TSG cut structures 190, 390, 380 shown may extend vertically in the upper portion 628 of the stacked structure 620 and may extend laterally along the word line direction (X direction). Each TSG cut 590 may partially cover two adjacent rows of channel structures 650 located in the lower portion 629 of the stacked structure 620. For example, each TSG cut 590 may be located above a portion of the functional layer 540 and the high-K dielectric layer 530 of the channel structure 650 in the lower portion 629 of the stacked structure 620.

[0082] like Figure 5 As shown, in the lateral direction, the TSG cut 590 may contact the channel layer 550 of the channel structure 650 of two adjacent rows. In some embodiments, the TSG cut 590 may contact the curved side surface of the channel layer 550 of the channel structure 650 of two adjacent rows located in the upper portion 628 of the stacked structure 620. That is, along the word line direction (X direction), the TSG cut 590 may have a concave sidewall. The lateral cross-section of the functional layer 540 of the channel structure 650 located in the upper portion 628 of the stacked structure 620 may have a partial annular shape. Both lateral ends of the partially annular functional layer 540 may contact the TSG cut 590. In some embodiments, the partial annular shape is larger than one-third of the annular shape.

[0083] It should be noted that the upper portion 628 of the stacked structure 620 may include any suitable number of dielectric layers 622 and conductive layers 624 . Figure 6 The top four pairs of dielectric layers 622 and conductive layers 624 shown are merely an example and do not limit the scope of the disclosure. In some embodiments, the depth of TSG cut 590 is greater than the total thickness of the top pair of dielectric layers 622 and conductive layers 624, and less than the total thickness of the top seven pairs of dielectric layers 622 and conductive layers 624.

[0084] refer to Figure 8 , a schematic diagram of a 3D memory device 800 according to some embodiments of the present disclosure is shown in a cross-sectional side view. It should be noted that the 3D memory device 800 can be along Figure 1 AA' line or along Figure 3 BB' line shown. Figure 7 , a schematic diagram showing a portion 700 of a 3D memory device 800 in an enlarged top view according to some embodiments of the present disclosure is shown.

[0085] In some embodiments, Figure 8 As shown, a stack structure 820 including a plurality of dielectric layers 822 and conductive layers 824 alternately stacked in a vertical direction may be located on a substrate 810. Gate gap (GLS) structures 830 may each extend vertically through the stack structure 820 into the substrate 810 and extend laterally along the word line direction (X direction). Between adjacent GLS structures 830, a plurality of channel structures 850 may each extend vertically through the stack structure 820 into the substrate 810.

[0086] like Figure 7 and 8 As shown, each channel structure 850 may include a high-K dielectric layer 730 located on the sidewall of the channel hole, a functional layer (or storage film) 740 covering the high-K dielectric layer 730, a channel layer 750 covering the functional layer 740, and a filling structure 760 surrounded by the channel layer 750. In some embodiments, the functional layer 740 may include a barrier layer 742, a storage layer 744, and a tunneling layer 746.

[0087] like Figure 7 and 8 As shown, TSG cutout 790 (eg, Figure 1-4The TSG cut structures 190, 390, 380 shown may extend vertically in the upper portion 828 of the stacked structure 820 and may extend laterally along the word line direction (X direction). Each TSG cut 790 may partially cover two adjacent rows of channel structures 850 located in the lower portion 829 of the stacked structure 820. For example, each TSG cut 790 may be located above portions of the functional layer 740, the high-K dielectric layer 730, and the channel layer 750 of the channel structure 850 in the lower portion 829 of the stacked structure 820.

[0088] like Figure 7 As shown, in the lateral direction, the TSG cutout 790 may contact the channel layer 750 and the filling structure 760 of the channel structure 850 of two adjacent rows in the upper portion 828 of the stacked structure 820. That is, along the word line direction (X direction), the TSG cutout 790 may have a straight sidewall. The lateral cross-section of the functional layer 740 and the channel layer 750 of the channel structure 850 located in the upper portion 828 of the stacked structure 820 may have a partial annular shape. Both lateral ends of the functional layer 740 and the channel layer 750 of the partial annular shape may contact the TSG cutout 790. In some embodiments, the partial annular shape is larger than one-third of the annular shape.

[0089] It should be noted that the upper portion 828 of the stacked structure 820 may include any suitable number of dielectric layers 822 and conductive layers 824 . Figure 8 The top four pairs of dielectric layers 822 and conductive layers 824 shown are merely an example and do not limit the scope of the disclosure. In some embodiments, the depth of TSG cut 790 is greater than the total thickness of the top pair of dielectric layers 822 and conductive layers 824, and less than the total thickness of the top seven pairs of dielectric layers 822 and conductive layers 824.

[0090] refer to Fig.11 , a flow chart of a method 1100 for forming a 3D memory device according to some embodiments of the present disclosure is shown. Figure 12-18 The cross-sectional view shows a Fig.11 Schematic diagram of a 3D memory device at certain manufacturing stages of method 1100 is shown. It should be understood that the operations shown in method 1100 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of these operations may be performed simultaneously or in parallel. Fig.11 The different orders shown in .

[0091] like Fig.11As shown, the method may start at operation 1110 , in which a dielectric stack structure may be formed on a substrate, and a plurality of channel structures may be formed in the dielectric stack structure. Figure 4 A cross-sectional view of a 3D structure after operation 1110 is shown, in accordance with some embodiments of the present disclosure.

[0092] In some embodiments, substrate 1210 may be any suitable semiconductor substrate having any suitable structure, such as a single crystal single layer substrate, a polycrystalline silicon (poly-Si) single layer substrate, a poly-Si and metal multi-layer substrate, and the like.

[0093] A dielectric stack structure 1220 including a plurality of dielectric layer pairs may be formed on a substrate 1210. For example, the dielectric stack structure 1220 may include an alternating stack of first dielectric layers 1222 (e.g., silicon oxide) and second dielectric layers 1224 (e.g., silicon nitride) different from the first dielectric layers 1222. The plurality of first dielectric layers 1222 and second dielectric layers 1224 extend in a lateral direction parallel to the surface of the substrate 1210. In some embodiments, there are more layers than dielectric layer pairs made of different materials and having different thicknesses in the dielectric stack structure 1220. The dielectric stack structure 1220 may be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0094] In some embodiments, the dielectric stack structure 1220 may include a plurality of silicon oxide / silicon nitride layer pairs. Each dielectric layer pair includes a layer of silicon oxide 1222 and a layer of silicon nitride 1224. The plurality of oxide / nitride layer pairs are also referred to herein as "alternating oxide / nitride stacks". That is, in the dielectric stack structure 1220, a plurality of oxide layers 1222 (shown in the solid gray area) and a plurality of nitride layers 1224 (shown in the grid area) alternate in the vertical direction. In other words, except for the top and bottom layers of a given alternating oxide / nitride stack, each of the other oxide layers 1222 may be sandwiched by two adjacent nitride layers 1224, and each of the nitride layers 1224 may be sandwiched by two adjacent oxide layers 1222.

[0095] The oxide layers may all have the same thickness or different thicknesses. For example, the thickness of each oxide layer may be in the range of 10 nm to 1210 nm, preferably about 25 nm. Similarly, the nitride layers may all have the same thickness or different thicknesses. For example, the thickness of each nitride layer may be in the range of 10 nm to 1210 nm, preferably about 35 nm.

[0096] It should be noted that in the present disclosure, the oxide layer 1222 and / or the nitride layer 1224 may include any suitable oxide material and / or nitride material. For example, the oxide material may include silicide, and the elements of the nitride material may include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped silicon, silicide, or any combination thereof. In some embodiments, the oxide layer may be a silicon oxide layer, and the nitride layer may be a silicon nitride layer.

[0097] The dielectric stack structure 1220 may include any suitable number of oxide layers 1222 and nitride layers 1224. In some embodiments, the total number of oxide layers 1222 and nitride layers 1224 in the dielectric stack structure 1220 is equal to or greater than 64. That is, the number of oxide / nitride layer pairs may be equal to or greater than 32. In some embodiments, the alternating oxide / nitride stack 200 includes more oxide layers or nitride layers having different materials and / or thicknesses than oxide / nitride layer pairs.

[0098] In some embodiments, a plurality of channel structures 1230 may be formed in the dielectric stack structure 1220. Each channel structure 1230 may extend vertically into the substrate 1210 through the dielectric stack structure 1220. In some embodiments, a plurality of channel structures 1230 may be formed in an array form. In some embodiments, the array of channel structures 1230 may include multiple rows of channel structures 1230. Each row of channel structures 1230 may be aligned along the word line direction (X direction). The channel structures 1230 of adjacent rows may not be aligned. In some embodiments, the array of channel structures 1230 may include multiple columns of channel structures 1230. Each column of channel structures 1230 may be aligned along the bit line direction (Y direction). The channel structures 1230 of adjacent columns may not be aligned.

[0099] In some embodiments, the manufacturing process for forming the plurality of channel structures 1230 may include forming a plurality of channel holes (not shown) that penetrate the dielectric stack structure 1220. The process for forming the plurality of channel holes may include forming a hard mask layer (not shown) on the dielectric stack structure 1220, and coating a photoresist layer (not shown) on the hard mask layer. A patterning process may be performed to pattern the hard mask layer. Using the hard mask layer as a mask, an etching process may be followed to etch the dielectric stack structure 1220 to form a plurality of channel holes. Each channel hole may completely penetrate the dielectric stack structure 1220 and extend into the substrate 1210. The etching process for forming the plurality of channel holes may be dry etching, wet etching, or a combination thereof. After the etching process, the photoresist layer and the hard mask layer may be removed.

[0100] In some embodiments, a cleaning process can be performed to clean multiple channel holes. The cleaning process can be a plasma ashing process including high temperature ashing and / or wet stripping. For example, a plasma source can be used to generate reactants, such as oxygen or fluorine. The reactants can be combined with the photoresist retained in the channel holes to form ash that can be removed with a vacuum pump. Specifically, in some embodiments, monatomic oxygen plasma can be generated by exposing oxygen to high-power radio waves that ionize oxygen at low pressure. The residue of the reaction between oxygen and the photoresist material can generate ash in a plasma asher. The byproducts of the ashing process, such as volatile carbon oxides and water vapor, can be pumped away with a vacuum pump in a plasma asher.

[0101] A channel structure 1230 may be formed in each channel hole in a subsequent process. A plurality of channel structures 1230 may be arranged in a staggered array. In some embodiments, each channel structure 1230 may include an optional high-K dielectric layer (not shown), a functional layer 1240 located on the sidewall of the channel hole or covering the high-K dielectric layer, a channel layer 1250 covering the functional layer 1240, and a filling structure 1260 surrounded by the channel layer 1250. In some embodiments, the functional layer 1240 may include a barrier layer 1242, a storage layer 1244, and a tunneling layer 1246.

[0102] In some embodiments, the manufacturing process for forming the channel structure 1230 may include forming an epitaxial layer (not shown) at the bottom of each channel hole. In some embodiments, the epitaxial layer may be a polycrystalline silicon (polysilicon) layer formed by using a selective epitaxial growth (SEG) process. For example, a SEG pre-cleaning process may be performed to clean the plurality of channel holes. A subsequent deposition process may be performed to form a polysilicon layer at the bottom of each channel hole. In some embodiments, any suitable doping process (e.g., an ion metal plasma (IMP) process) may be performed on the polysilicon layer to form the epitaxial layer. In some embodiments, the epitaxial layer may not be formed directly on the surface of the substrate 1210. One or more layers may be formed between the epitaxial layer 551 and the substrate 1210. That is, the epitaxial layer covers the substrate 1210.

[0103] In some embodiments, the manufacturing process for forming the channel structure 550 may include forming a high-K dielectric layer (not shown) on the sidewalls of each channel hole, and forming a functional layer 1240 to cover the high-K dielectric layer. The functional layer 1240 may be a composite dielectric layer, such as a combination of a barrier layer 1242, a storage layer 1244, and a tunneling layer 1246. The high-K dielectric layer, the functional layer 1240 including the barrier layer 1242, the storage layer 1244, and the tunneling layer 1246 may be formed by one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0104] In some embodiments, a blocking layer 1242 and / or a high-K dielectric layer may be formed between the storage layer 1244 and the sidewalls of the channel hole. The blocking layer 1242 and / or the high-K dielectric layer may be used to block the outflow of electronic charge. In some embodiments, the blocking layer 1242 may be a silicon oxide layer or a combination of silicon oxide / silicon nitride / silicon oxide (ONO) layers. In some embodiments, the high-K dielectric layer includes any suitable high dielectric constant (high-k value) dielectric (e.g., aluminum oxide). In some embodiments, the thickness of the blocking layer 1242 and / or the high-K dielectric layer may be in a range from about 3 nm to about 20 nm.

[0105] The storage layer 1244 may be formed between the tunneling layer 1246 and the barrier layer 1242. Electrons or holes from the channel layer may tunnel to the storage layer 1244 through the tunneling layer 1246. The storage layer 1244 may be used to store electronic charges (electrons or holes) for memory operations. The storage or removal of charges in the storage layer 1244 may affect the on / off state and / or conductivity of the semiconductor channel. The storage layer 1244 may include one or more material films, including but not limited to silicon nitride, silicon oxynitride, a combination of silicon oxide and silicon nitride, or any combination thereof. In some embodiments, the storage layer 1244 may include a nitride layer formed by using one or more deposition processes. In some embodiments, the thickness of the storage layer 1244 may be in a range from about 3 nm to about 20 nm.

[0106] The tunneling layer 1246 may be formed on the sidewalls of the storage layer 1244. The tunneling layer may be used to tunnel electronic charges (electrons or holes). The tunneling layer 1246 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the tunneling layer 1246 may be an oxide layer formed using a deposition process. In some embodiments, the thickness of the tunneling layer 1246 may be in a range from about 3 nm to about 20 nm.

[0107] In some embodiments, the manufacturing process for forming the channel structure 1230 further includes forming a channel layer 1250 covering the sidewalls of the functional layer 1240. In some embodiments, the channel layer 1250 may be an amorphous silicon layer or a polysilicon layer formed by using a thin film deposition process (e.g., ALD, CVD, PVD, or any other suitable process). In some embodiments, the thickness of the channel layer 1250 may be in a range from about 5 nm to 20 nm.

[0108] In some embodiments, the manufacturing process for forming the channel structure further includes forming a filling structure 1260 to cover the channel layer 1250 and fill the channel hole. In some embodiments, the filling structure 1260 can be an oxide layer formed by using any suitable deposition process (e.g., ALD, CVD, PVD, etc.). In some embodiments, the filling structure 1260 can include one or more air gaps (not shown).

[0109] Return to reference Fig.11 , the method proceeds to operation 1120, in which a plurality of gate slits (GLS) may be formed in the dielectric stack structure, and the dielectric stack structure may be transformed into a stack structure including a plurality of conductive layer / dielectric layer pairs. Fig.13 A cross-sectional view of the 3D structure after operation 1120 is shown.

[0110] like Fig.13 As shown, the gate gaps (GLS) 1380 can extend laterally in a straight line along the word line direction (X direction) between the two arrays of the channel structure 1230, and vertically penetrate the dielectric stack structure 1220 into the substrate 1210. Multiple GLS1380 can be formed by forming a mask layer on the dielectric stack structure 1220 and patterning the mask using, for example, photolithography to form openings corresponding to the multiple GLS1380 in the patterned mask layer. An appropriate etching process (e.g., dry etching and / or wet etching) can be performed to remove the portion of the dielectric stack structure 1220 exposed by the opening until the multiple GLS1380 expose the substrate 1210. The mask layer can be removed after the multiple GLS1380 are formed. In some embodiments, a doped region (not shown) can be formed at the bottom of each GLS1380 in the substrate 1210 by using any appropriate doping process (e.g., ion implantation and / or thermal diffusion) through the GLS1380. The dopant in the doped region may be any suitable N+ or P+ ions. After the conductive walls are formed in the GLS 1380 in a subsequent process, the lower end of each conductive wall may contact the corresponding doped region.

[0111] In some embodiments, a gate replacement process (also referred to as a "word line replacement" process) can be performed to replace the second dielectric layer 1224 (e.g., silicon nitride) of the dielectric stack structure 1220 with the conductive layer 1324. In some embodiments, after forming the plurality of GLS1380, the second dielectric layer 1224 in the dielectric stack structure 1220 can be removed by the GLS1380 to form a plurality of lateral trenches. The plurality of lateral trenches can extend in a lateral direction and can be used as spaces for the conductive layer 1324 to be formed in a subsequent process. The second dielectric layer 1224 in the dielectric stack structure 1220 is used as a sacrificial layer and is removed by using any suitable etching process (e.g., isotropic dry etching or wet etching). The etching process can have a sufficiently high etching selectivity to the material of the second dielectric layer 1224 compared to the material of the first dielectric layer 1222 so that the etching process can have minimal impact on the first dielectric layer 1222. Isotropic dry etching and / or wet etching and subsequent cleaning processes can remove the second dielectric layer 1224 in various directions to expose the top and bottom surfaces of each first dielectric layer 1222. In this way, a plurality of lateral trenches can then be formed between the first dielectric layers 1222.

[0112] like Fig.13 As shown, multiple conductive layers 1324 can be formed in multiple lateral trenches. Multiple conductive layers 1324 can be used as word lines (i.e., gate electrodes) in a 3D memory device. In some embodiments, each conductive layer 1324 can be coated with one or more insulating layers (not shown) useful as gate dielectric layers to insulate the corresponding word line (i.e., gate electrode).

[0113] In some embodiments, one or more insulating layers (not shown) may be formed in each of the plurality of lateral grooves to cover the exposed surface of the lateral groove with one or more suitable insulating materials. For example, one or more suitable deposition processes (e.g., CVD, PVD, and / or ALD) may be used to deposit one or more insulating materials into the lateral grooves. In some embodiments, recess etching and / or chemical-mechanical planarization (CMP) may be used to remove excess insulating material. The one or more insulating materials may include any suitable material (e.g., a high-k dielectric) that provides an electrical insulation function. For example, the one or more insulating materials may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium nitride, etc. and / or any suitable combination thereof. In some embodiments, the plurality of insulating layers may have different insulating materials.

[0114] A conductive layer 1324 may be formed in each lateral groove between one or more insulating layers. The conductive layer 1324 may be formed by filling the lateral groove with an appropriate gate electrode metal material. The conductive layer 1324 may provide a base material for a subsequently formed word line (i.e., a gate electrode). The gate electrode metal material may include any suitable conductive material for forming a word line (i.e., a gate electrode), such as tungsten, aluminum, copper, cobalt, or any combination thereof. The gate electrode material may be deposited into the lateral groove using an appropriate deposition method (e.g., CVD, physical vapor deposition (PVD), plasma enhanced CVD (PECVD), sputtering, metal organic chemical vapor deposition (MOCVD), and / or ALD). In some embodiments, the conductive layer 1324 includes tungsten formed by CVD. In this way, the dielectric stack structure 1220 is transformed into a stack structure 1320 including alternating conductive layers / dielectric layers.

[0115] Return to reference Fig.11 , the method proceeds to operation 1130, where a GLS structure may be formed in each gate slit (GLS). Fig.14 A cross-sectional view of the 3D structure after operation 1130 is shown.

[0116] In some embodiments, the manufacturing process for forming the GLS structure 1480 may include forming a spacer layer 1482 on the sidewalls of the plurality of GLSs 1380. The spacer layer 1482 is also referred to as a gate line spacer (GLSP) layer and may be used to provide electrical insulation between the plurality of conductive layers 1324 and conductive walls formed in subsequent processes.

[0117] In some embodiments, the manufacturing process for forming the spacer layer 1482 may include a word line gate recess process. After forming the plurality of conductive layers 1324, portions of the plurality of conductive layers 1324 (word lines) exposed by the GLS 1380 may be removed by a recess etching process. In some embodiments, in order to ensure insulation between the plurality of conductive layers 1324 (word lines), a recess etching process (e.g., a wet etching process) may be performed to remove portions of the plurality of conductive layers 1324 exposed by the GLS 1380. In doing so, a recess may be formed in each lateral trench adjacent to the GLS 1380.

[0118] In some embodiments, the spacer layer 1482 may have a laminated structure (not shown) including two or more spacer sublayers formed by using any appropriate deposition process (e.g., an atomic layer deposition (ALD) process). For example, the spacer layer 1482 may include a first spacer sublayer (not shown) covering the sidewalls of the GLS1380 and the exposed surfaces of the multiple gate structures. The first spacer sublayer may include a low temperature oxide material (e.g., silicon oxide) configured to prevent the multiple conductive layers 1324 from being oxidized in subsequent processes. The spacer layer 1482 may also include a second spacer sublayer (not shown) to cover the first spacer sublayer. The second spacer sublayer may include a high-k value material, such as silicon nitride. Such a laminated structure can effectively increase the equivalent oxide thickness (EOT) of the spacer layer 1482, thereby improving the isolation performance of the spacer layer 1482.

[0119] In some embodiments, the manufacturing process for forming the GLS structure 1480 may include forming a conductive wall 1845 in each GLS. The conductive wall 1845 may contact a doped region (not shown) in the substrate 1210 and serve as an array common source (ACS) for multiple NAND strings. In some embodiments, the conductive wall 1845 may be formed by depositing a conductive material (e.g., polysilicon, silicide, tungsten, aluminum, copper, and / or combinations thereof, etc.). The conductive material may be deposited into the multiple GLSs 1380 using an appropriate deposition method (e.g., CVD, physical vapor deposition (PVD), plasma enhanced CVD (PECVD), sputtering, metal organic chemical vapor deposition (MOCVD), and / or ALD). A chemical-mechanical planarization (CMP) process may then be performed to planarize the top surface of the formed 3D structure.

[0120] Return to reference Fig.11 , the method proceeds to operation 1140 , where a portion of the stack structure and a portion of the channel structure located in an upper portion of the stack structure may be removed to form a plurality of trenches. Fig.15 A cross-sectional view of the 3D structure after operation 1140 is shown, in accordance with some embodiments of the present disclosure. Fig.17 A cross-sectional view of a 3D structure after operation 1140 is shown, according to some other embodiments of the present disclosure.

[0121] like Fig.15 and 17 As shown, the trenches 1580 / 1780 can extend laterally along the word line direction (X direction). In some embodiments, the trenches 1580 / 1780 can be used to form a subsequent process such as Figure 1The TSG cutout 190 shown. In such an embodiment, the trench 1580 / 1780 can be formed between the channel structures 1230 of adjacent rows. A plurality of trenches 1580 / 1780 can extend in parallel laterally along the word line direction (i.e., the X direction), and can extend vertically in the upper portion 1522 of the stacked structure 1320. Each trench 1580 / 1780 can expose the channel layer 1250 of the channel structures 1230 of two adjacent rows. The conductive layer 1324 located in the upper portion 1522 of the stacked structure 1320 can be divided into a plurality of sub-blocks 1570 / 1770 by the trench 1580 / 1780. That is, the channel structures 1230 of two adjacent rows between two adjacent trenches 1580 / 1780 can share one sub-block 1570 / 1770. In some embodiments, the first number of trenches 1580 / 1780 located between adjacent gate line structures 1480 plus one is half the second number of rows of channel structures 1230 located between adjacent gate line structures 1480 .

[0122] In some other embodiments, the trench 1580 / 1780 can be used to form a Figure 3 The first TSG cutout 390 and the second TSG cutout 380 shown. In such an embodiment, the groove 1580 / 1780 can be formed to include a plurality of first grooves and second grooves arranged alternately along the bit line direction (ie, the Y direction). The plurality of first grooves and second grooves can extend laterally in parallel along the word line direction (ie, the X direction) and can extend vertically in the upper portion 1522 of the stacked structure 1320. Each second groove may include a plurality of second groove segments extending discontinuously along the word line direction (ie, the X direction). Each first groove or second groove may expose the channel layer 1250 of the channel structure 1230 of two adjacent rows. It should be noted that the channel structure at the corner of the second groove segment can be used as a dummy channel structure. The conductive layer 1324 located in the upper portion 1522 of the stacked structure 1320 can be divided into a plurality of sub-blocks 1570 / 1770 by the first groove, and the discontinuous second groove segment does not separate the conductive layer 1324. That is, four adjacent rows of channel structures 1230 located between two adjacent first trenches may share one sub-block 1570 / 1770 .

[0123] An appropriate etching process (e.g., dry etching and / or wet etching) may be performed to remove portions of the stacked structure 1320 and portions of the channel structure 1230 to form the trench 1580 / 1780. In some embodiments, the trench may extend and penetrate the top one to seven oxide / nitride layer pairs of the stacked structure 1320. A mask layer (not shown) may be used to control the shape of the trench 1580 / 1780 during the etching process. Fig.15In some embodiments shown, the channel layer 1250 of the channel structure 1230 is not removed during the etching process. In this way, the formed trench 1580 / 1780 can have a concave sidewall and can be used to form a Figure 5 The GLS cutout 590 is shown. Fig.17 In some other embodiments shown, a portion of the channel layer 1250 of the channel structure 1230 may also be removed during the etching process. In this way, the formed trench 1580 / 1780 may have substantially straight sidewalls and may be used to form a Figure 7 GLS cut 790 is shown. The mask layer may be removed after forming trenches 1580 / 1780.

[0124] Return to reference Fig.11 , the method proceeds to operation 1150 , where TSG cuts may be formed in the plurality of trenches. Fig.16 A cross-sectional view of the 3D structure after operation 1150 is shown, in accordance with some embodiments of the present disclosure. Fig.18 A cross-sectional view of a 3D structure after operation 1150 is shown, according to some other embodiments of the present disclosure.

[0125] like Fig.16 and 18 As shown, in some embodiments, a deposition process may then be performed to fill the trench 1580 / 1780 with any suitable filling material (eg, silicon oxide) to form a TSG cutout 1690 / 1890. It should be noted that the formed TSG cutout 1690 / 1890 may be as shown. Figure 1 The TSG cutout 190 shown or Figure 3 The TSG cutout 380 / 390 shown. The detailed features of the TSG cutout 1690 / 1890 can be referred to above in conjunction with Figure 1 and Figure 3 It should also be noted that the TSG cutout 1690 formed may be as described above in conjunction with Figure 5-6 The TSG cutout 590 described above and the formed TSG cutout 1890 may be as described above in conjunction with Figure 7-8 TSG incision 790 is described.

[0126] Therefore, a 3D memory device and a manufacturing method are provided. In some embodiments of the disclosed 3D memory device, two rows of channel structures can be used as a group. In this way, the bit line connection does not require a double pattern, but can be implemented by a single pattern. That is, a layer of TSG structure plus a bit line can control a single row of channel structures, thereby reducing interference during programming and reading and reducing metal wiring. In addition, in some embodiments of the disclosed 3D memory device, the channel structure corresponding to the TSG structure can be designed to have a partial circular shape. That is, the current switch of the channel structure can be controlled by the partially circular gate electrode of the TSG. In this way, there is no need to design a split region as a dummy channel structure. The disclosed design of the TSG isolation function can be manufactured by a simple process without increasing the process cost and / or manufacturing area.

[0127] The foregoing description of specific embodiments will so completely reveal the general nature of the present disclosure that others can, by applying knowledge within the technical scope of the art, easily modify and / or adjust such specific embodiments for various applications without undue experimentation and without departing from the general concepts of the present disclosure. Therefore, based on the teachings and guidance given herein, such adjustments and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments. It will be understood that the words or terms herein are for descriptive purposes rather than for limiting purposes, so that the terms or terms of this specification will be interpreted by those skilled in the art based on the teachings and guidance.

[0128] The embodiments of the present disclosure have been described above with the help of functional building blocks that illustrate the embodiments of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries may be defined as long as the specified functions and their relationships are properly performed.

[0129] The Summary and Abstract sections may set forth one or more but not all embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0130] The breadth and scope of the present disclosure should not be limited by any of the above-described embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor structure comprising: A stacked structure comprising a plurality of dielectric layers and conductive layers alternately stacked in a vertical direction; an array of channel structures, each channel structure vertically penetrating the stacked structure, each channel structure comprising a functional layer and a channel layer; as well as A plurality of isolation structures extend in parallel along a first lateral direction and are vertically located in an upper portion of the stack structure, each isolation structure being in contact with the channel layers of the channel structures in two adjacent rows.

2. The semiconductor structure according to claim 1, wherein: Each isolation structure partially covers the two adjacent rows of channel structures located in the lower portion of the stack structure.

3. The semiconductor structure according to claim 2, wherein: The plurality of isolation structures include: A plurality of first isolation structures, each of which separates the conductive layer of the upper portion of the stack structure into sub-blocks.

4. The semiconductor structure of claim 1, wherein: The isolation structure contacts curved side surfaces of the channel layers of the channel structures of the two adjacent rows located in the upper portion of the stack structure.

5. The semiconductor structure according to claim 1, wherein: The isolation structure contacts the filling structures of the two adjacent rows of channel structures located in the upper portion of the stack structure.

6. The semiconductor structure of claim 3, wherein: A column of channel structures extending along the second lateral direction and located on a same side of the first isolation structure is connected to a common bit line.

7. The semiconductor structure according to claim 3, wherein: The plurality of isolation structures further include: a plurality of second isolation structures, each second isolation structure extending along the first lateral direction without isolating the conductive layer of the upper portion of the stacked structure; The plurality of first isolation structures and the plurality of second isolation structures are alternately arranged along the second transverse direction.

8. The semiconductor structure according to claim 7, wherein: The plurality of second isolation structures each include a plurality of second isolation segments extending discontinuously along the first lateral direction.

9. The semiconductor structure of claim 7, wherein: A first subset of a column of channel structures extending along a second lateral direction and in contact with the first isolation structure is connected to a first common bit line; and A second subset of the column of channel structures in contact with the second isolation structure is connected to a second common bit line.

10. The semiconductor structure according to claim 8, wherein: The array of channel structures comprises: A dummy channel structure is in contact with a corner of the second isolation section.

11. The semiconductor structure of claim 1 , further comprising: A plurality of gate line structures extending in parallel along the first transverse direction and vertically passing through the stack structure; The first number of the isolation structures between adjacent gate line structures plus one is half of the second number of the rows of the channel structures between adjacent gate line structures.

12. The semiconductor structure of claim 1, wherein: a lateral cross-section of the functional layer of the channel structure located in the upper portion of the stacked structure having a partial annular shape; and Both lateral ends of the partially annular functional layer are in contact with the isolation structure.

13. The semiconductor structure of claim 5, wherein: a lateral cross-section of the channel layer of the channel structure located in the upper portion of the stacked structure having a partial annular shape; and Both lateral ends of the partially annular channel layer are in contact with the isolation structure.

14. The semiconductor structure of claim 12, wherein: The partial annular shape is larger than one-third of a ring.

15. The semiconductor structure of claim 1, wherein: The depth of the isolation structure is greater than the total thickness of the top pair of the dielectric layer and the conductive layer, and less than the total thickness of the top seven pairs of the dielectric layer and the conductive layer.

16. A method of forming a semiconductor structure, comprising: forming a dielectric stack structure; forming an array of channel structures, each channel structure vertically penetrating the dielectric stack structure, each channel structure comprising a functional layer and a channel layer; transforming the dielectric stack structure into a stack structure comprising a plurality of alternately stacked dielectric layers and conductive layers; removing the channel structures and portions of the stacked structure located in an upper portion of the stacked structure to form a plurality of trenches extending in parallel along a first lateral direction, each trench exposing the channel layers of two adjacent rows of channel structures located in the upper portion of the stacked structure; as well as A plurality of isolation structures are formed in the trenches, each of the isolation structures being in contact with the channel layers of the channel structures in two adjacent rows.

17. The method of claim 16, wherein: Each isolation structure is formed to partially cover the two adjacent rows of channel structures located in the lower portion of the stack structure.

18. The method according to claim 17, wherein: Forming the plurality of grooves comprises: A portion of the functional layer of the channel structure located in the upper portion of the stacked structure is removed.

19. The method according to claim 18, wherein: Forming the plurality of grooves further comprises: A portion of the channel layer of the channel structure located in the upper portion of the stacked structure is removed.

20. The method according to claim 17, wherein: Forming the plurality of isolation structures comprises: The plurality of isolation structures are formed in the trench, each isolation structure being in contact with a curved side surface of the channel layer of the channel structures of the two adjacent rows located in the upper portion of the stack structure.

21. The method according to claim 19, wherein: Forming the plurality of isolation structures comprises: The plurality of isolation structures are formed in the trench, each isolation structure being in contact with the filling structures of the two adjacent rows of channel structures located in the upper portion of the stack structure.

22. The method according to claim 17, wherein: Forming the plurality of grooves comprises: A plurality of first trenches are formed, each of which separates the conductive layer of the upper portion of the stack structure into sub-blocks.

23. The method according to claim 22, further comprising: A plurality of bit lines extending in parallel along the second lateral direction are formed, each bit line being connected to a column of channel structures extending along the second lateral direction and located on a same side of the isolation structure.

24. The method of claim 22, further comprising: forming a plurality of second trenches, each second trench extending along the first lateral direction without separating the conductive layer of the upper portion of the stacked structure; as well as forming a plurality of second isolation structures in the second trench, The plurality of first isolation structures and the plurality of second isolation structures are alternately arranged along the second transverse direction.

25. The method of claim 24, wherein: forming the plurality of second trenches includes forming a plurality of second trench segments extending discontinuously along the first lateral direction; Forming the plurality of second isolation structures includes forming a plurality of second isolation segments in the plurality of second trench segments.

26. The method according to claim 25, further comprising: A dummy channel structure is formed in contact with a corner of the second isolation section.

27. The method of claim 16, wherein: Forming the dielectric stack structure includes forming a plurality of dielectric layers and sacrificial layers alternately stacked in a vertical direction; Transforming the dielectric stack structure into a stack structure comprises: forming a plurality of gate line structures extending in parallel along the first lateral direction and vertically penetrating the dielectric stack structure, and replacing the sacrificial layer with a conductive layer; The first number of the isolation structures located between adjacent gate line structures plus one is equal to the second number of the rows of the channel structures located between the adjacent gate line structures.

28. A semiconductor device comprising: a plurality of isolation structures extending in parallel along a first lateral direction and vertically located in an upper portion of the stacked structure; as well as an array of channel structures, each channel structure vertically penetrating the stacked structure and comprising: a lower channel portion having a cylindrical shape in a lower portion of the stack structure, and An upper channel portion having a partial cylindrical shape and contacting a corresponding isolation structure is provided in the upper portion of the stack structure.

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