Three-dimensional memory devices and methods of manufacturing the same

Abstract

Embodiments of three-dimensional (3D) memory devices and methods of manufacturing the same are disclosed. In some embodiments, a disclosed 3D memory device includes a stack structure including a plurality of dielectric layers and conductive layers alternately stacked in a vertical direction, an array of channel structures each vertically penetrating the stack structure, each channel structure including a functional layer and a channel layer, and a plurality of isolation structures extending in parallel along a first lateral direction and vertically located in an upper portion of the stack structure, each isolation structure contacting the channel layers of two adjacent rows of the channel structures.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of semiconductor technology, and more specifically, to three-dimensional (3D) memory devices and manufacturing methods for forming three-dimensional (3D) memory devices. BACKGROUND

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processes and manufacturing technology become challenging and costly. As such, the storage density for planar memory cells approaches an upper limit. Three-dimensional (3D) memory architectures can address the density limitations in planar memory cells.

[0003] As semiconductor technology advances, 3D memory devices (e.g., 3D NAND memory devices) continue to reduce cost and increase capacity. The density of memory cells in horizontal planes continues to compress. Top select gates (TSGs) are a necessary structure for NAND memory devices. The density of memory cells for NAND memory devices can be greatly reduced due to the need for TSG cutouts between memory strings. SUMMARY

[0004] Embodiments of three-dimensional (3D) memory devices and manufacturing methods thereof are disclosed herein.

[0005] One aspect of the present disclosure provides a semiconductor structure, comprising: a stack structure comprising a plurality of dielectric layers and conductive layers alternately stacked in a vertical direction; an array of channel structures, each channel structure vertically penetrating the stack structure, each channel structure comprising a functional layer and a channel layer; and a plurality of isolation structures extending in parallel along a first lateral direction and vertically located in an upper portion of the stack structure, each isolation structure contacting the channel layers of two adjacent rows of channel structures.

[0006] In some embodiments, each isolation structure partially covers two adjacent rows of channel structures located in a lower portion of the stack structure.

[0007] In some embodiments, the plurality of isolation structures comprises: a plurality of first isolation structures, each first isolation structure separating the conductive layers of the upper portion of the stack structure into sub-blocks.

[0008] In some embodiments, the isolation structure contacts curved side surfaces of the channel layers of two adjacent rows of channel structures located in the upper portion of the stack structure.

[0009] In some embodiments, the isolation structure contacts the fill structures of two adjacent rows of channel structures located in the upper portion of the stack structure.

[0010] In some embodiments, a column of the channel structures extending along the second lateral direction and located on a same side of the first isolation structure is connected to a common bit line.

[0011] In some embodiments, the plurality of isolation structures further comprises: a plurality of second isolation structures each extending along the first lateral direction without separating the conductive layers of the upper portion of the stack structure; wherein the plurality of first isolation structures and the plurality of second isolation structures are arranged alternately along the second lateral direction.

[0012] In some embodiments, each of the plurality of second isolation structures comprises a plurality of second isolation segments discontinuously extending along the first lateral direction.

[0013] In some embodiments, a first subset of the column of channel structures extending along the second lateral direction and in contact with the first isolation structure is connected to a first common bit line; and a second subset of the column of channel structures in contact with the second isolation structure is connected to a second common bit line.

[0014] In some embodiments, the array of channel structures comprises: a dummy channel structure in contact with a corner of the second isolation segment.

[0015] In some embodiments, the semiconductor structure further comprises: a plurality of gate line structures extending in parallel along the first lateral direction and vertically through the stack structure; wherein a first number of isolation structures between adjacent gate line structures plus one is half of a second number of rows of channel structures between the adjacent gate line structures.

[0016] In some embodiments, a lateral cross-section of the functional layer of the channel structure located in the upper portion of the stack structure has a partial ring shape; and two lateral ends of the functional layer of the partial ring shape are in contact with the isolation structure.

[0017] In some embodiments, a lateral cross-section of the channel layer of the channel structure located in the upper portion of the stack structure has a partial ring shape; and two lateral ends of the channel layer of the partial ring shape are in contact with the isolation structure.

[0018] In some embodiments, the partial ring shape is greater than one-third of a ring.

[0019] In some embodiments, a depth of the isolation structure is greater than a total thickness of the top pair of dielectric layers and the conductive layer, and is less than a total thickness of the top seven pairs of dielectric layers and the conductive layer.

[0020] Another aspect of the present disclosure provides a method of forming a semiconductor structure, comprising: forming a dielectric stack structure; forming an array of channel structures each vertically traversing the dielectric stack structure, each channel structure comprising a functional layer and a channel layer; transforming the dielectric stack structure into a stack structure comprising a plurality of alternating stacked dielectric layers and conductive layers; removing portions of the channel structures and the stack structure located in an upper portion of the stack structure to form a plurality of trenches extending in parallel along a first lateral direction, each trench exposing the channel layers of two adjacent rows of channel structures located in the upper portion of the stack structure; and forming a plurality of isolation structures in the trenches, each isolation structure contacting the channel layers of the two adjacent rows of channel structures.

[0021] In some embodiments, each isolation structure is formed to partially cover the two adjacent rows of channel structures located in a lower portion of the stack structure.

[0022] In some embodiments, forming the plurality of trenches comprises: removing portions of the functional layers of the channel structures located in the upper portion of the stack structure.

[0023] In some embodiments, forming the plurality of trenches further comprises: removing portions of the channel layers of the channel structures located in the upper portion of the stack structure.

[0024] In some embodiments, forming the plurality of isolation structures comprises: forming the plurality of isolation structures in the trenches, each isolation structure contacting curved side surfaces of the channel layers of the two adjacent rows of channel structures located in the upper portion of the stack structure.

[0025] In some embodiments, forming the plurality of isolation structures comprises: forming the plurality of isolation structures in the trenches, each isolation structure contacting the fill structures of the two adjacent rows of channel structures located in the upper portion of the stack structure.

[0026] In some embodiments, forming the plurality of trenches comprises: forming a plurality of first trenches each separating the conductive layers of the upper portion of the stack structure into sub-blocks.

[0027] In some embodiments, the method further comprises: forming a plurality of bit lines extending in parallel along a second lateral direction, each bit line connected to a column of channel structures extending along the second lateral direction and located on a same side of the isolation structures.

[0028] In some embodiments, the method further comprises: forming a plurality of second trenches each extending along the first lateral direction without separating the conductive layers of the upper portion of the stack structure; and forming a plurality of second isolation structures in the second trenches, wherein the plurality of first isolation structures and the plurality of second isolation structures are arranged in alternation along the second lateral direction.

[0029] In some embodiments, forming the plurality of second trenches includes forming a plurality of second trench segments extending discontinuously along the first lateral direction; and forming the plurality of second isolation structures includes forming a plurality of second isolation segments in the plurality of second trench segments.

[0030] In some embodiments, the method further includes forming a dummy channel structure in contact with a corner of the second isolation segment.

[0031] In some embodiments, the method further includes forming the dielectric stack structure includes forming a plurality of dielectric layers and a plurality of sacrificial layers stacked alternately in the vertical direction; and transforming the dielectric stack structure into the stack structure includes forming a plurality of gate line structures extending parallel along the first lateral direction and vertically through the dielectric stack structure, and replacing the sacrificial layers with electrically conductive layers; wherein a first number of isolation structures plus one located between adjacent gate line structures is equal to a second number of rows of channel structures located between adjacent gate line structures.

[0032] Another aspect of the disclosure provides a semiconductor device, comprising: a plurality of isolation structures extending parallel along a first lateral direction and located vertically in an upper portion of a stack structure; and an array of channel structures, each channel structure vertically through the stack structure and comprising: a lower channel portion having a cylindrical shape in a lower portion of the stack structure and an upper channel portion having a partial cylindrical shape in the upper portion of the stack structure and in contact with a corresponding isolation structure.

[0033] Other aspects of the disclosure will become apparent to those skilled in the art from the description, claims, and drawings of the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the relevant art to make and use the present disclosure.

[0035] Figure 1 A schematic diagram illustrating a portion of a 3D memory device according to some embodiments of the present disclosure is shown in an enlarged top view.

[0036] Figure 2 A schematic diagram illustrating a portion of a 3D memory device according to some embodiments of the present disclosure is shown in an enlarged top view.

[0037] Figure 3 A schematic diagram illustrating a portion of a 3D memory device according to some embodiments of the present disclosure is shown in an enlarged top view.

[0038] Figure 4A schematic diagram of a portion of a 3D memory device according to some embodiments of the disclosure is shown in an enlarged top view.

[0039] Figure 5 A schematic diagram of a portion of a 3D memory device 600 according to some embodiments of the disclosure is shown in an enlarged top view.

[0040] Figure 6 A schematic diagram of a 3D memory device according to some embodiments of the disclosure is shown in a cross-sectional side view.

[0041] Figure 7 A schematic diagram of a portion of a 3D memory device 600 according to some embodiments of the disclosure is shown in an enlarged top view.

[0042] Figure 8 A schematic diagram of a 3D memory device according to some embodiments of the disclosure is shown in a cross-sectional side view.

[0043] Figure 9 A block diagram of a system having a memory device according to some aspects of the disclosure is shown.

[0044] Figure 10A A diagram of an exemplary memory card having a memory device according to some embodiments is shown.

[0045] Figure 10B A diagram of an exemplary solid state drive (SSD) having a memory according to some embodiments is shown.

[0046] Figure 11 A flow diagram of a method for forming a 3D memory device according to some embodiments of the disclosure is shown.

[0047] Figures 12-18 A schematic diagram of a 3D memory device at certain manufacturing stages of the method shown in Figure 11

[0048] A schematic diagram of a 3D memory device at certain manufacturing stages of the method shown in Figure 19

[0049] A perspective view of a portion of a 3D memory array structure according to some embodiments of the disclosure is shown. Figure 20 Embodiments of the disclosure will be described with reference to the accompanying drawings.

[0050] DETAILED DESCRIPTION DETAILED DESCRIPTION

[0051] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Alternative configurations and arrangements can be employed without departing from the spirit and scope of the disclosure. It will be apparent to those skilled in the relevant arts that the disclosure can also be employed in various other applications.

[0052] It should be noted that references to “one embodiment,” “an embodiment,” “example embodiments,” “some embodiments,” etc. in the present disclosure mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily referring to the same embodiment.

[0053] In general, terminology can be understood at least in part from usage in context. For example, terms, such as “one or more” as used herein, can be understood as in some contexts to mean any feature, structure, or characteristic single or plural, and in other contexts to mean some feature, structure, or characteristic single or plural. Similarly, terms, such as “a,” “an,” or “the,” again, can be understood, at least in part, depending on the context in which they are used, as taking the plural form or as taking the singular form.

[0054] It will be readily understood that the terms “on,” “above,” and “on top of,” in the present disclosure, are to be interpreted in the broadest context, such that “on” means not only “directly on” but also includes the meaning of “on” with intervening features or layers therebetween, and “above” or “on top of” means not only the meaning of “above” or “on top of” but also can include the meaning of “above” or “on top of” without intervening features or layers therebetween (i.e., directly on).

[0055] In addition, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0056] As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Further, the substrate can comprise a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0057] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an underlying or overlying structure, or can have a extent that is less than the underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform continuous structure, having a thickness that is less than the thickness of the continuous structure. For example, a layer can be between any pair of lateral planes between or at the top and bottom surfaces of a continuous structure. A layer can extend laterally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, thereabove, and / or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which contacts, interconnect lines, and / or vias are formed) and one or more dielectric layers.

[0058] As used herein, the term "nominal / nominally" refers to a desired or target value of a characteristic or parameter set for a component or process operation during a design phase of a product or process, and a range of values above and / or below the desired value due to slight variations in manufacturing processes or tolerances. As used herein, the term "about" denotes a value of a given quantity that can vary based on a particular technology node associated with a subject semiconductor device. Based on a particular technology node, the term "about" can denote a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0059] As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (i.e., regions herein as "memory strings," such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertically / vertically" means nominally perpendicular to a lateral surface of the substrate.

[0060] As described above, 3D NAND memory devices continue to reduce costs and increase capacity by compressing the density of memory cells in a horizontal plane. However, as a necessary structure for NAND memory devices, a top select gate (TSG) structure located between memory strings has a negative impact on the memory cell density of NAND memory devices. Specifically, one approach to the TSG structure includes using a stack of multiple rows of channel structures, arranging one row of dummy channel structures between every four rows of channel structures, and separating the stack of gate layers to form the TSG structure. The first approach is low cost and simple manufacturing process, but has a high loss per die per wafer (DPW). Another approach to the TSG structure includes adding an additional TSG layer on the upper layer of the channel structures, and interconnecting with the channel structures through a small aperture TSG channel. Due to the limited space of the small aperture, a wavy TSG structure is allowed to save area in the horizontal plane. However, the second approach is high cost and complex manufacturing process. Furthermore, the structure typically uses four rows of channel structures as a group, and each bit line and / or TSG in the same group controls two channel structures. Such an arrangement can cause crosstalk during programming and reading, which is detrimental to the reliability of 3D NAND memory devices.

[0061] Accordingly, various embodiments according to the present disclosure provide 3D memory devices and methods of manufacturing the same to address the above-described problems. Specifically, in some embodiments, two rows of channel structures can be used as a group. As such, bit line connections do not require double patterning, but can be achieved through single patterning. That is, one layer of TSG structure plus one bit line can control a single row of channel structures, thereby reducing interference during programming and reading and reducing metal wiring. Furthermore, in some embodiments, channel structures corresponding to the TSG structure can be designed to have a partial circular shape. That is, the current switching of the channel structures can be controlled by the partial circular gate electrode of the TSG. As such, there is no need to design a split region as a dummy channel structure. The disclosed design of TSG isolation function can be manufactured through a simple process without increasing the process cost and / or manufacturing area.

[0062] Figure 9 A block diagram of a system 900 having a memory device according to some aspects of the present disclosure is shown. The system 900 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game controller, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other appropriate electronic device having a memory device therein. As Figure 9As shown, the system 900 can include a host 908 and a memory system 902 having one or more memory devices 904 and a memory controller 906. The host 908 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 908 can be configured to send data to or receive data from the memory device 904.

[0063] The memory device 904 can be any memory device disclosed herein, such as a NAND flash memory device. In keeping with the scope of the present disclosure, the memory controller 906 can control multi-pass programming to the memory device 904 such that, in a non-final pass of the multi-pass programming, NGS operations are implemented to all memory cells, even those that passed a corresponding verify operation. Peripheral circuitry (e.g., word line drivers) can apply a low voltage (e.g., a ground (GND) voltage) to the DSG of each memory string coupled to a selected word line and can apply a low or negative voltage to the selected word line to implement NGS operations to all memory cells coupled to the selected word line during the non-final pass of programming.

[0064] According to some embodiments, a memory controller 906 is coupled to the memory devices 904 and the host 908 and is configured to control the memory devices 904. The memory controller 906 can manage data stored in the memory devices 904 and communicate with the host 908. In some embodiments, the memory controller 906 is designed to work in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 906 is designed to work in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 906 can be configured to control operations of the memory devices 904 (e.g., read, erase, and program operations). The memory controller 906 can also be configured to manage various functions related to data stored or to be stored in the memory devices 904, including, but not limited to, bad block management, garbage collection, logical to physical address translations, wear leveling, etc. In some embodiments, the memory controller 906 is also configured to handle error-correcting codes (ECCs) related to data read from or written to the memory devices 904. The memory controller 906 can also perform any other suitable functions, such as programming the memory devices 904. The memory controller 906 can communicate with external devices (e.g., the host 908) according to a particular communication protocol. For example, the memory controller 906 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, etc.

[0065] The memory controller 906 and the one or more memory devices 904 can be integrated into various types of memory devices, such as included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 902 can be implemented and packaged into different types of end electronic products. In Figure 10AIn one example shown, the memory controller 906 and the single memory device 904 can be integrated into a memory card 1002. The memory card 1002 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and the like. The memory card 1002 can also include a memory card connector 1004 that couples the memory card 1002 with a host (e.g., the host 908 in Figure 9 Figure 10B In another example shown, the memory controller 906 and the plurality of memory devices 904 can be integrated into an SSD 1006. The SSD 1006 can also include an SSD connector 1008 that couples the SSD 1006 with a host (e.g., the host 908 in Figure 9

[0066] Figure 19 A top view of a 3D memory device 1900 according to some embodiments of the present disclosure is shown. The 3D memory device 1900 can be a memory chip (package), a memory chip, or any part of a memory chip, and can include one or more memory planes 1901, each of which can include a plurality of memory blocks 1903. The same and simultaneous operations can occur at each memory plane 1901. The size of a memory block 1903, which can be a megabyte (MB), can be the smallest size to perform an erase operation. As Figure 19 shown, the 3D memory device 1900 includes four memory planes 1901, and each memory plane 1901 includes six memory blocks 1903. Each memory block 1903 can include a plurality of memory cells, each of which can be addressed by interconnections (e.g., bit lines and word lines). The bit lines and word lines can be arranged perpendicularly (e.g., in rows and columns, respectively), forming an array of metal lines. In Figure 19 the X direction and the direction of the bit lines is labeled as the Y direction. In the present disclosure, the memory block 1903 is also referred to as a “memory array” or an “array.” The memory array is a core area in a memory device that performs a memory function.

[0067] ​​The 3D memory device 1900 can include a peripheral region 1905, which is a region surrounding the memory faces 1901. The peripheral region 1905 can contain a number of digital, analog, and / or mixed-signal circuits to support the functionality of the memory array, such as page buffers, row decoders and column decoders, and sense amplifiers. As will be apparent to those of ordinary skill in the art, the peripheral circuits use active semiconductor devices and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc. It should be noted that, Figure 19 The arrangement of the memory faces 1901 in the 3D memory device 1900 and the arrangement of the memory blocks 1903 in each memory face 1901 shown in FIG. 1A are provided by way of example only and do not limit the scope of the present disclosure.

[0068] Figure 20 A perspective view of a portion of a 3D memory array structure 2000 is shown in accordance with some embodiments of the present disclosure. The memory array structure 2000 includes a substrate 2330, an insulating film 2331 located on the substrate 2330, one tier or multiple tiers of bottom select gates (BSG) 2332 located on the insulating film 2331, and multiple tiers of control gates 2333, also referred to as “word lines (WL),” stacked on top of the BSG 2332 to form a stacked structure 2335 of alternating conductive and dielectric layers. For clarity, Figure 20 The dielectric layers adjacent to each tier of control gates are not shown in FIG. 2A.

[0069] The control gates 2333 of each layer are separated by slit structures 2216-1 and 2216-2 that pass through the stack structure 2335. The memory array structure 2000 can include one or more layers of top select gates (TSG) 2334 located above the stack of control gates 2333. The stack of TSG 2334, control gates 2333, and BSG 2332 is also referred to as a “gate structure.” The memory array structure 2000 also includes doped source line regions 2344 in portions of the substrate 2330 between adjacent BSGs 2332. Each memory string 2212 includes a channel hole 2336 that extends through the insulating film 2331 and the stack structure 2335 of alternating conductive and dielectric layers. The memory string 2212 can also include a memory film 2337 (also referred to as a “functional layer”) located on the sidewalls of the channel hole 2336, a channel layer 2338 located above the memory film 2337, and a core fill film 2339 surrounded by the channel layer 2338. A memory cell 2340 can be formed at the intersection of the control gate 2333 and the memory string 2212. The memory array structure 2000 also includes a plurality of bit lines (BL) 2341 connected to the memory strings 2212 above the TSG 2334. The memory array structure 2000 can include a plurality of metal interconnect lines 2343 connected to the gate structure by a plurality of contact structures 2214. The edges of the stack structure 2335 are configured as a staircase structure to allow electrical connections to each layer of the gate structure.

[0070] In Figure 20 , three layers of control gates 2333-1, 2333-2, and 2333-3 are shown along with one layer of TSG 2334 and one layer of BSG 2332 for illustrative purposes. In this example, each memory string 2212 can include three memory cells 2340-1, 2340-2, and 2340-3 corresponding to the control gates 2333-1, 2333-2, and 2333-3, respectively. In some embodiments, the number of control gates and the number of memory cells can be more than three to increase storage capacity. The memory array structure 2000 can also include other structures such as TSG cutouts, common source contacts, and dummy channel structures. For simplicity, Figure 20 , these structures are not shown.

[0071] Referring to Figure 1 , a schematic diagram of a portion 100 of a 3D memory device (e.g., region 2008 in Figure 20 ) is shown in an enlarged top view according to some embodiments of the present disclosure. As shown, a plurality of slits can extend laterally in parallel along the word line direction (i.e., the X direction). A gate slit (GLS) structure 130 can be formed in each slit to divide the memory array into a plurality of memory fingers 110.

[0072] Each memory finger 110 may include an even number (e.g., 8, 16, 32, etc.) of channel structures 150 arranged in an interleaved manner between two adjacent GLS structures 130. Multiple top select gate (TSG) cutouts (also referred to as “isolation structures”) 190 may be located between adjacent rows of channel structures 150. The multiple TSG cutouts 190 may extend laterally parallel along the word line direction (i.e., the X direction) and may extend vertically in the upper portion of the stacked structure of the 3D memory device. Each TSG cutout 190 may contact the channel layer of two adjacent rows of channel structures 150. The conductive layer in the upper portion of the stacked structure of the 3D memory device may be divided into multiple sub-blocks 120 by the TSG cutouts 190. That is, two adjacent rows of channel structures 150 located between two adjacent TSG cutouts 190 may share a sub-block 120. In some embodiments, the first number of TSG cutouts 190 located between adjacent gate slot structures 130 plus one is half the second number of rows of channel structures 150 located between adjacent gate slot structures 130.

[0073] refer to Figure 2 The diagram shows a portion 200 of a portion 100 of a 3D memory device according to some embodiments of the present disclosure, in an enlarged top view. As shown, each column of channel structures 150 extending along the bit line direction (i.e., the Y direction) and located on the same side of the TSG cutout 190 can be connected to a common bit line 240. For example, a first column of channel structures 150 located on the upper side of the TSG cutout 190 can be connected to a first common bit line 240-1, and a second column of channel structures 150 located on the lower side of the TSG cutout 190 can be connected to a second common bit line 240-2.

[0074] refer to Figure 3 A portion 300 of a 3D memory device according to some other embodiments of the present disclosure is shown in an enlarged top view (e.g., Figure 20 A schematic diagram of region 2008 in the diagram. As shown, multiple slots can extend laterally in parallel along the word line direction (i.e., the X direction). A gate slot (GLS) structure 130 can be formed in each slot to divide the memory array into multiple memory fingers 110.

[0075] Each storage finger 110 can include an even number (e.g., 8, 16, 32, etc.) of rows of channel structures 150 arranged in an interleaved manner between two adjacent GLS structures 130. A plurality of first top select gate (TSG) cuts (also referred to as“first isolation structures”) 390 and second top select gate (TSG) cuts 380 (also referred to as“second isolation structures”) can be located between adjacent rows of channel structures 150. The plurality of first TSG cuts 390 and second TSG cuts 380 are arranged in an alternating manner along the bit line direction (i.e., Y direction). The plurality of first TSG cuts 390 and second TSG cuts 380 can extend laterally in parallel along the word line direction (i.e., X direction) and can extend vertically in an upper portion of the stack structure of the 3D memory device. Each second TSG cut 380 can include a plurality of second TSG cut segments (also referred to as“second isolation segments”) that extend discontinuously along the word line direction (i.e., X direction).

[0076] Each first TSG cut 390 or second TSG cut 380 can be in contact with the channel layer of two adjacent rows of channel structures 150. It should be noted that the dummy channel structure 350 can be in contact with a corner of a second TSG cut segment. The conductive layer located in the upper portion of the stack structure of the 3D memory device can be divided into a plurality of sub-blocks 320 by the first TSG cuts 390, while the discontinuous second TSG cut segments of the second TSG cuts 380 do not partition the conductive layer. That is, four adjacent rows of channel structures 150 located between two adjacent first TSG cuts 390 can share one sub-block 320.

[0077] Referring to Figure 4 A diagram illustrating a portion 400 in a portion 200 of a 3D memory device according to some embodiments of the present disclosure is shown in an enlarged top view. In some embodiments, a first subset of a column of channel structures extending along a second lateral direction and in contact with a first isolation structure is connected to a first common bit line, and a second subset of the column of channel structures in contact with a second isolation structure is connected to a second common bit line. For example, as shown, a subset of the first column of channel structures 150 in contact with the second TSG cut structure 380 can be connected to a first common bit line 440-1, and a subset of the first column of channel structures 150 in contact with the first TSG cut structure 390 can be connected to a second common bit line 440-2. Figure 4

[0078] Referring to Figure 6 A diagram illustrating a 3D memory device 600 according to some embodiments of the present disclosure is shown in a cross-sectional side view. It should be noted that the 3D memory device 600 can be along the AA’ line shown or along the BB’ line shown. Figure 1 Figure 3 Figure 5 ​​​A schematic diagram of a portion 500 of a 3D memory device 600 according to some embodiments of the present disclosure is shown in an enlarged top view.

[0079] In some embodiments, as shown in FIG. 6A, a stack structure 620 including a plurality of dielectric layers 622 and conductive layers 624 alternately stacked in a vertical direction can be located on a substrate 610. A plurality of gate-last select (GLS) structures 630 can each vertically extend through the stack structure 620 into the substrate 610 and laterally extend along a word line direction (X direction). Between adjacent GLS structures 630, a plurality of channel structures 650 can each vertically extend through the stack structure 620 into the substrate 610. Figure 6

[0080] Figure 5 Figure 6 As shown in FIG. 6B, each channel structure 650 can include a high-K dielectric layer 530 located on sidewalls of a channel hole, a functional layer (or a memory film) 540 covering the high-K dielectric layer 530, a channel layer 550 covering the functional layer 540, and a fill structure 560 surrounded by the channel layer 550. In some embodiments, the functional layer 540 can include a blocking layer 542, a storage layer 544, and a tunneling layer 546.

[0081] As shown in FIG. 6C, a TSG cut 590 (e.g., a TSG cut structure 190, 390, 380 as shown in FIGS. 1A, 1B, 1C, 3A, 3B, 3C, 4A, 4B, 4C, 5A, 5B, 5C) can vertically extend in an upper portion 628 of the stack structure 620 and can laterally extend along the word line direction (X direction). Each TSG cut 590 can partially cover two adjacent rows of channel structures 650 located in a lower portion 629 of the stack structure 620. For example, each TSG cut 590 can be located over portions of the functional layer 540 and the high-K dielectric layer 530 of the channel structures 650 in the lower portion 629 of the stack structure 620. Figure 5 6 As shown in FIG. 6D, in a lateral direction, the TSG cut 590 can be in contact with the channel layer 550 of two adjacent rows of channel structures 650. In some embodiments, the TSG cut 590 can be in contact with curved side surfaces of the channel layer 550 of two adjacent rows of channel structures 650 located in the upper portion 628 of the stack structure 620. That is, along the word line direction (X direction), the TSG cut 590 can have a concave sidewall. A lateral cross-section of the functional layer 540 of the channel structures 650 located in the upper portion 628 of the stack structure 620 can have a partial ring shape. Two lateral ends of the partial ring-shaped functional layer 540 can be in contact with the TSG cut 590. In some embodiments, the partial ring shape is greater than a one-third ring shape. Figures 1-4

[0082] As shown in FIG. 6E, in a lateral direction, the TSG cut 590 can be in contact with the channel layer 550 of two adjacent rows of channel structures 650. In some embodiments, the TSG cut 590 can be in contact with curved side surfaces of the channel layer 550 of two adjacent rows of channel structures 650 located in the upper portion 628 of the stack structure 620. That is, along the word line direction (X direction), the TSG cut 590 can have a concave sidewall. A lateral cross-section of the functional layer 540 of the channel structures 650 located in the upper portion 628 of the stack structure 620 can have a partial ring shape. Two lateral ends of the partial ring-shaped functional layer 540 can be in contact with the TSG cut 590. In some embodiments, the partial ring shape is greater than a one-third ring shape. Figure 5 ​​​​​​

[0083] It should be noted that the upper portion 628 of the stack structure 620 can include any suitable number of layers of dielectric layers 622 and conductive layers 624. Figure 6 The top four pairs of dielectric layers 622 and conductive layers 624 shown are merely an example, but do not limit the scope of the disclosure. In some embodiments, the depth of the TSG cut 590 is greater than the total thickness of the top pair of dielectric layers 622 and conductive layers 624, and is less than the total thickness of the top seven pairs of dielectric layers 622 and conductive layers 624.

[0084] Referring to Figure 8 A schematic diagram of a 3D memory device 800 according to some embodiments of the present disclosure is shown in a cross-sectional side view. It should be noted that the 3D memory device 800 can be along the Figure 1 AA’ line shown or along the Figure 3 BB’ line shown. Referring to Figure 7 A schematic diagram of a portion 700 of the 3D memory device 800 according to some embodiments of the present disclosure is shown in an enlarged top view.

[0085] In some embodiments, as Figure 8 shown, a stack structure 820 including a plurality of dielectric layers 822 and conductive layers 824 alternately stacked in a vertical direction can be located on a substrate 810. Gate-last spacer (GLS) structures 830 can each extend vertically through the stack structure 820 into the substrate 810 and laterally along a word line direction (X direction). Between adjacent GLS structures 830, a plurality of channel structures 850 can each extend vertically through the stack structure 820 into the substrate 810.

[0086] As Figure 7 and 8 shown, each channel structure 850 can include a high-K dielectric layer 730 located on sidewalls of a channel hole, a functional layer (or memory film) 740 covering the high-K dielectric layer 730, a channel layer 750 covering the functional layer 740, and a fill structure 760 surrounded by the channel layer 750. In some embodiments, the functional layer 740 can include a blocking layer 742, a memory layer 744, and a tunneling layer 746.

[0087] As Figure 7 and 8 shown, a TSG cut 790 (e.g., Figures 1-4The TSG cutout structures 190, 390, and 380 shown can extend vertically in the upper portion 828 of the stack structure 820 and can extend laterally along the word line direction (X direction). Each TSG cutout 790 can partially cover two adjacent rows of channel structures 850 located in the lower portion 829 of the stack structure 820. For example, each TSG cutout 790 can be located above a portion of the functional layer 740, the high-k dielectric layer 730, and the channel layer 750 of the channel structure 850 in the lower portion 829 of the stack structure 820.

[0088] like Figure 7 As shown, in the lateral direction, the TSG cutout 790 can contact the channel layer 750 and filler structure 760 of the channel structure 850 in two adjacent rows located in the upper portion 828 of the stack structure 820. That is, the TSG cutout 790 can have straight sidewalls along the letter line direction (X direction). The lateral cross-section of the functional layer 740 and channel layer 750 of the channel structure 850 in the upper portion 828 of the stack structure 820 can have a partially annular shape. The two lateral ends of the partially annular functional layer 740 and channel layer 750 can contact the TSG cutout 790. In some embodiments, the partially annular shape is greater than one-third of an annular shape.

[0089] It should be noted that the upper portion 828 of the stacked structure 820 may include any appropriate number of dielectric layers 822 and conductive layers 824. Figure 8 The top four pairs of dielectric layers 822 and conductive layers 824 shown are merely an example and do not limit the scope of the disclosure. In some embodiments, the depth of the TSG notch 790 is greater than the total thickness of the top pair of dielectric layers 822 and conductive layers 824, and less than the total thickness of the top seven pairs of dielectric layers 822 and conductive layers 824.

[0090] refer to Figure 11 The diagram shows a flowchart of a method 1100 for forming a 3D memory device according to some embodiments of the present disclosure. Figures 12-18 Cross-sectional views illustrate various embodiments of the present disclosure. Figure 11 This is a schematic diagram of a 3D memory device at certain manufacturing stages of method 1100. It should be understood that the operations shown in method 1100 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some of these operations may be performed simultaneously or in conjunction with... Figure 11 The different execution orders shown.

[0091] like Figure 11As shown, the method can begin at operation 1110, in which a dielectric stack structure can be formed on a substrate, and a plurality of channel structures can be formed in the dielectric stack structure. Figure 4 A cross-sectional view of a 3D structure after operation 1110 is shown according to some embodiments of the present disclosure.

[0092] In some embodiments, the substrate 1210 can be any appropriate semiconductor substrate having any appropriate structure, such as a single-crystalline monolayer substrate, a polycrystalline silicon (poly-silicon) monolayer substrate, a poly-silicon and metal multilayer substrate, etc.

[0093] A dielectric stack structure 1220 including a plurality of dielectric layer pairs can be formed on the substrate 1210. For example, the dielectric stack structure 1220 can include an alternating stack of first dielectric layers 1222 (e.g., silicon oxide) and second dielectric layers 1224 (e.g., silicon nitride) different from the first dielectric layers 1222. The plurality of first dielectric layers 1222 and second dielectric layers 1224 extend in a lateral direction parallel to a surface of the substrate 1210. In some embodiments, there are more layers in the dielectric stack structure 1220 than pairs of dielectric layers made of different materials and having different thicknesses. The dielectric stack structure 1220 can be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0094] In some embodiments, the dielectric stack structure 1220 can include a plurality of silicon oxide / silicon nitride layer pairs. Each dielectric layer pair includes one layer of silicon oxide 1222 and one layer of silicon nitride 1224. The plurality of oxide / nitride layer pairs is also referred to herein as an "alternating oxide / nitride stack". That is, in the dielectric stack structure 1220, the plurality of oxide layers 1222 (shown in the solid gray regions) and the plurality of nitride layers 1224 (shown in the regions of the grid) alternate in the vertical direction. In other words, each of the other oxide layers 1222, except for the top and bottom layers of a given alternating oxide / nitride stack, can be sandwiched by two adjacent nitride layers 1224, and each of the nitride layers 1224 can be sandwiched by two adjacent oxide layers 1222.

[0095] The oxide layers can all have the same thickness or have different thicknesses. For example, the thickness of each oxide layer can be in a range from 10 nm to 1210 nm, preferably about 25 nm. Similarly, the nitride layers can all have the same thickness or have different thicknesses. For example, the thickness of each nitride layer can be in a range from 10 nm to 1210 nm, preferably about 35 nm.

[0096] It should be noted that in the present disclosure, the oxide layers 1222 and / or the nitride layers 1224 can include any appropriate oxide material and / or nitride material. For example, the oxide material can include silicide, and the elements of the nitride material can include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped silicon, silicide, or any combination thereof. In some embodiments, the oxide layers can be silicon oxide layers, and the nitride layers can be silicon nitride layers.

[0097] The dielectric stack structure 1220 can include any appropriate number of oxide layers 1222 and nitride layers 1224. In some embodiments, the total number of oxide layers 1222 and nitride layers 1224 located in the dielectric stack structure 1220 is equal to or greater than 64. That is, the number of oxide / nitride layer pairs can be equal to or greater than 32. In some embodiments, the alternating oxide / nitride stack 200 includes more oxide layers or nitride layers having different materials and / or thicknesses than oxide / nitride layer pairs.

[0098] In some embodiments, a plurality of channel structures 1230 can be formed in the dielectric stack structure 1220. Each channel structure 1230 can extend vertically through the dielectric stack structure 1220 into the substrate 1210. In some embodiments, the plurality of channel structures 1230 can be formed in an array. In some embodiments, the array of channel structures 1230 can include a plurality of rows of channel structures 1230. Each row of channel structures 1230 can be aligned along a word line direction (X direction). Adjacent rows of channel structures 1230 can be misaligned. In some embodiments, the array of channel structures 1230 can include a plurality of columns of channel structures 1230. Each column of channel structures 1230 can be aligned along a bit line direction (Y direction). Adjacent columns of channel structures 1230 can be misaligned.

[0099] In some embodiments, a manufacturing process for forming the plurality of channel structures 1230 can include forming a plurality of channel holes (not shown) through the dielectric stack structure 1220. The process for forming the plurality of channel holes can include forming a hard mask layer (not shown) on the dielectric stack structure 1220, and coating a photoresist layer (not shown) on the hard mask layer. A patterning process can be performed to pattern the hard mask layer. Using the hard mask layer as a mask, an etching process can be followed to etch the dielectric stack structure 1220 to form the plurality of channel holes. Each channel hole can extend completely through the dielectric stack structure 1220 and into the substrate 1210. The etching process for forming the plurality of channel holes can be a dry etching, a wet etching, or a combination thereof. After the etching process, the photoresist layer and the hard mask layer can be removed.

[0100] In some embodiments, a cleaning process can be performed to clean the plurality of trench holes. The cleaning process can be a plasma ashing process including high temperature ashing and / or wet stripping. For example, a plasma source can be used to generate a reactant, such as oxygen or fluorine. The reactant can combine with photoresist remaining in the trench holes to form ash that can be removed with a vacuum pump. Specifically, in some embodiments, a monatomic oxygen plasma can be generated by exposing oxygen gas to high power radio waves that ionize the oxygen gas at low pressure. Residue of the reaction between the oxygen and the photoresist material can generate ash in a plasma ashing machine. Byproducts of the ashing process, such as volatile carbon oxides, water vapor, can be pumped away with a vacuum pump inside the plasma ashing machine.

[0101] A channel structure 1230 can be formed in each trench hole in a subsequent process. The plurality of channel structures 1230 can be arranged in a staggered array. In some embodiments, each channel structure 1230 can include an optional high-K dielectric layer (not shown), a functional layer 1240 on sidewalls of the trench hole or covering the high-K dielectric layer, a channel layer 1250 covering the functional layer 1240, and a fill structure 1260 surrounded by the channel layer 1250. In some embodiments, the functional layer 1240 can include a blocking layer 1242, a storage layer 1244, and a tunneling layer 1246.

[0102] In some embodiments, the fabrication process for forming the channel structure 1230 can include forming an epitaxial layer (not shown) at the bottom of each trench hole. In some embodiments, the epitaxial layer can be a polycrystalline silicon (poly-silicon) layer formed by using a selective epitaxial growth (SEG) process. For example, a SEG pre-cleaning process can be performed to clean the plurality of trench holes. A subsequent deposition process can be performed to form a poly-silicon layer at the bottom of each trench hole. In some embodiments, any appropriate doping process (e.g., ion metal plasma (IMP) process) can be performed on the poly-silicon layer to form the epitaxial layer. In some embodiments, the epitaxial layer can not be formed directly on the surface of the substrate 1210. One or more layers can be formed between the epitaxial layer 551 and the substrate 1210. That is, the epitaxial layer covers the substrate 1210.

[0103] In some embodiments, the fabrication process for forming the channel structure 550 can include forming a high-K dielectric layer (not shown) on the sidewalls of each channel hole, and forming a functional layer 1240 to cover the high-K dielectric layer. The functional layer 1240 can be a composite dielectric layer, such as a combination of a blocking layer 1242, a storage layer 1244, and a tunneling layer 1246. The high-K dielectric layer, the functional layer 1240 including the blocking layer 1242, the storage layer 1244, and the tunneling layer 1246 can be formed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other appropriate process, or any combination thereof.

[0104] In some embodiments, the blocking layer 1242 and / or the high-K dielectric layer can be formed between the storage layer 1244 and the sidewalls of the channel hole. The blocking layer 1242 and / or the high-K dielectric layer can be used to block the outflow of electronic charges. In some embodiments, the blocking layer 1242 can be a silicon oxide layer or a combination of silicon oxide / silicon nitride / silicon oxide (ONO) layers. In some embodiments, the high-K dielectric layer includes any appropriate high-dielectric constant (high-k value) dielectric (e.g., aluminum oxide). In some embodiments, the thickness of the blocking layer 1242 and / or the high-K dielectric layer can be in a range from about 3 nm to about 20 nm.

[0105] The storage layer 1244 can be formed between the tunneling layer 1246 and the blocking layer 1242. Electrons or holes from the channel layer can tunnel through the tunneling layer 1246 to the storage layer 1244. The storage layer 1244 can be used to store electronic charges (electrons or holes) for memory operations. The storage or removal of charges in the storage layer 1244 can affect the on / off state and / or conductivity of the semiconductor channel. The storage layer 1244 can include one or more films of materials including, but not limited to, silicon nitride, silicon oxynitride, silicon oxide, and a combination of silicon nitride and silicon oxide, or any combination thereof. In some embodiments, the storage layer 1244 can include a nitride layer formed by using one or more deposition processes. In some embodiments, the thickness of the storage layer 1244 can be in a range from about 3 nm to about 20 nm.

[0106] The tunneling layer 1246 can be formed on the sidewalls of the storage layer 1244. The tunneling layer can be used to tunnel electronic charges (electrons or holes). The tunneling layer 1246 can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the tunneling layer 1246 can be an oxide layer formed by using a deposition process. In some embodiments, the thickness of the tunneling layer 1246 can be in a range from about 3 nm to about 20 nm.

[0107] In some embodiments, the fabrication process for forming the channel structure 1230 further includes forming a channel layer 1250 covering the sidewalls of the functional layer 1240. In some embodiments, the channel layer 1250 can be an amorphous silicon layer or a polysilicon layer formed by using a thin film deposition process (e.g., ALD, CVD, PVD, or any other appropriate process). In some embodiments, the thickness of the channel layer 1250 can be in a range from about 5 nm to 20 nm.

[0108] In some embodiments, the fabrication process for forming the channel structure further includes forming a fill structure 1260 to cover the channel layer 1250 and fill the channel hole. In some embodiments, the fill structure 1260 can be an oxide layer formed by using any appropriate deposition process (e.g., ALD, CVD, PVD, etc.). In some embodiments, the fill structure 1260 can include one or more air gaps (not shown).

[0109] Referring back to Figure 11 , the method proceeds to operation 1120, in which a plurality of gate slits (GLSs) can be formed in the dielectric stack structure, and the dielectric stack structure can be transformed into a stack structure including a plurality of conductive / dielectric layer pairs. Figure 13 A cross-sectional view of the 3D structure after operation 1120 is shown.

[0110] As shown in Figure 13 , the gate slits (GLSs) 1380 can each extend laterally along a straight line along the word line direction (X direction) between the two arrays of channel structures 1230, and vertically through the dielectric stack structure 1220 into the substrate 1210. The plurality of GLSs 1380 can be formed by forming a mask layer over the dielectric stack structure 1220 and patterning the mask using, for example, photolithography to form openings in the patterned mask layer corresponding to the plurality of GLSs 1380. An appropriate etching process (e.g., dry etching and / or wet etching) can be performed to remove portions of the dielectric stack structure 1220 exposed by the openings until the plurality of GLSs 1380 expose the substrate 1210. The mask layer can be removed after the plurality of GLSs 1380 are formed. In some embodiments, a doped region (not shown) can be formed at the bottom of each GLS 1380 in the substrate 1210 by using any appropriate doping process (e.g., ion implantation and / or thermal diffusion) through the GLS 1380. The dopant in the doped region can be any appropriate N+ or P+ ion. After the conductive walls are formed in the GLSs 1380 in a subsequent process, the lower end of each conductive wall can be in contact with the corresponding doped region.

[0111] In some embodiments, a gate replacement process (also known as a "word line replacement" process) can be performed to replace the second dielectric layer 1224 (e.g., silicon nitride) of the dielectric stack structure 1220 with a conductive layer 1324. In some embodiments, after forming a plurality of GLS1380s, the second dielectric layer 1224 in the dielectric stack structure 1220 can be removed by the GLS1380s to form a plurality of lateral trenches. The plurality of lateral trenches can extend in the lateral direction and can be used as spaces for the conductive layer 1324 to be formed in subsequent processes. The second dielectric layer 1224 in the dielectric stack structure 1220 serves as a sacrificial layer and is removed by using any suitable etching process (e.g., isotropic dry etching or wet etching). The etching process can have sufficiently high etch selectivity for the material of the second dielectric layer 1224 compared to the material of the first dielectric layer 1222, such that the etching process has minimal impact on the first dielectric layer 1222. Isotropic dry etching and / or wet etching, followed by a cleaning process, can remove the second dielectric layer 1224 in all directions to expose the top and bottom surfaces of each first dielectric layer 1222. In this way, a plurality of lateral trenches can then be formed between the first dielectric layers 1222.

[0112] like Figure 13 As shown, multiple conductive layers 1324 can be formed in multiple lateral trenches. The multiple conductive layers 1324 can serve as word lines (i.e., gate electrodes) in a 3D memory device. In some embodiments, each conductive layer 1324 may be coated with one or more insulating layers (not shown) useful as gate dielectric layers to insulate the corresponding word lines (i.e., gate electrodes).

[0113] In some embodiments, one or more insulating layers (not shown) may be formed in each of a plurality of lateral trenches to cover the exposed surface of the lateral trench with one or more suitable insulating materials. For example, one or more suitable deposition processes (e.g., CVD, PVD, and / or ALD) may be used to deposit one or more insulating materials into the lateral trenches. In some embodiments, recess etching and / or chemical-mechanical planarization (CMP) may be used to remove excess insulating material. The one or more insulating materials may include any suitable material that provides electrical insulation (e.g., a high-k dielectric). For example, one or more insulating materials may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium nitride, and / or any suitable combination thereof. In some embodiments, the plurality of insulating layers may have different insulating materials.

[0114] A conductive layer 1324 can be formed in each lateral trench located between one or more insulating layers. The conductive layer 1324 can be formed by filling the lateral trench with an appropriate gate electrode metal material. The conductive layer 1324 can provide a base material for subsequently formed word lines (i.e., gate electrodes). The gate electrode metal material can include any appropriate conductive material for forming word lines (i.e., gate electrodes), such as tungsten, aluminum, copper, cobalt, or any combination thereof. The gate electrode material can be deposited into the lateral trench using an appropriate deposition method, such as CVD, physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), sputtering, metal organic chemical vapor deposition (MOCVD), and / or ALD. In some embodiments, the conductive layer 1324 includes tungsten formed by CVD. As such, the dielectric stack structure 1220 is transformed into a stack structure 1320 including alternating conductive layers / dielectric layers.

[0115] Referring back to Figure 11 , the method proceeds to operation 1130 in which a GLS structure can be formed in each gate line slit (GLS). Figure 14 A cross-sectional view of the 3D structure after operation 1130 is shown.

[0116] In some embodiments, the manufacturing process for forming the GLS structure 1480 can include forming a spacer layer 1482 on the sidewalls of the plurality of GLSs 1380. The spacer layer 1482 is also referred to as a gate line spacer (GLSP) layer and can be used to provide electrical isolation between the plurality of conductive layers 1324 and conductive walls formed in subsequent processes.

[0117] In some embodiments, the manufacturing process for forming the spacer layer 1482 can include a word line gate recessing process. After the plurality of conductive layers 1324 are formed, portions of the plurality of conductive layers 1324 (word lines) exposed by the GLSs 1380 can be removed by a recess etching process. In some embodiments, to ensure isolation between the plurality of conductive layers 1324 (word lines), a recess etching process (e.g., a wet etching process) can be performed to remove portions of the plurality of conductive layers 1324 exposed by the GLSs 1380. In doing so, a recess can be formed in each lateral trench adjacent to the GLSs 1380.

[0118] In some embodiments, the spacer layer 1482 can have a laminate structure (not shown) including two or more spacer sub-layers formed by using any appropriate deposition process (e.g., an atomic layer deposition (ALD) process). For example, the spacer layer 1482 can include a first spacer sub-layer (not shown) covering the sidewalls of the GLSs 1380 and the exposed surfaces of the plurality of gate structures. The first spacer sub-layer can include a low temperature oxide material (e.g., silicon oxide) configured to prevent the plurality of conductive layers 1324 from being oxidized in subsequent processes. The spacer layer 1482 can further include a second spacer sub-layer (not shown) to cover the first spacer sub-layer. The second spacer sub-layer can include a high-k material, such as silicon nitride. Such a laminate structure can effectively increase the equivalent oxide thickness (EOT) of the spacer layer 1482, thereby improving the isolation performance of the spacer layer 1482.

[0119] In some embodiments, the fabrication process for forming the GLS structure 1480 can include forming a conductive wall 1845 in each GLS. The conductive wall 1845 can be in contact with a doped region (not shown) in the substrate 1210 and serve as an array common source (ACS) for the plurality of NAND strings. In some embodiments, the conductive wall 1845 can be formed by depositing a conductive material (e.g., polysilicon, silicide, tungsten, aluminum, copper, and / or combinations thereof, etc.). The conductive material can be deposited into the plurality of GLSs 1380 using an appropriate deposition method (e.g., CVD, physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), sputtering, metal organic chemical vapor deposition (MOCVD), and / or ALD). A chemical-mechanical planarization (CMP) process can be subsequently performed to planarize the top surface of the formed 3D structure.

[0120] Referring back to Figure 11 , the method proceeds to operation 1140, in which portions of the stack structure and the channel structure located in the upper portion of the stack structure can be removed to form a plurality of trenches. Figure 15 A cross-sectional view of the 3D structure after operation 1140 is shown according to some embodiments of the present disclosure. Figure 17 A cross-sectional view of the 3D structure after operation 1140 is shown according to some other embodiments of the present disclosure.

[0121] As shown in Figure 15 and 17 , the trenches 1580 / 1780 can each extend laterally along the word line direction (X direction). In some embodiments, the trenches 1580 / 1780 can be used to form a plurality of dummy word lines (not shown) in subsequent processes, as shown in Figure 1The TSG cutouts 190 are shown. In such embodiments, the trenches 1580 / 1780 can be formed between adjacent rows of the channel structures 1230. The plurality of trenches 1580 / 1780 can extend laterally in parallel along the word line direction (i.e., the X direction) and can extend vertically in the upper portion 1522 of the stack structure 1320. Each trench 1580 / 1780 can expose the channel layer 1250 of the channel structures 1230 of two adjacent rows. The conductive layer 1324 located in the upper portion 1522 of the stack structure 1320 can be divided into a plurality of sub-blocks 1570 / 1770 by the trenches 1580 / 1780. That is, the channel structures 1230 of two adjacent rows between two adjacent trenches 1580 / 1780 can share one sub-block 1570 / 1770. In some embodiments, a first number of the trenches 1580 / 1780 plus one between two adjacent gate line structures 1480 is half of a second number of rows of the channel structures 1230 between the two adjacent gate line structures 1480.

[0122] In some other embodiments, the trenches 1580 / 1780 can be used to form the first TSG cutouts 390 and the second TSG cutouts 380 in subsequent processes as shown. Figure 3 The first TSG cutouts 390 and the second TSG cutouts 380 are shown. In such embodiments, the trenches 1580 / 1780 can be formed to include a plurality of first trenches and second trenches arranged in an alternating manner along the bit line direction (i.e., the Y direction). The plurality of first trenches and second trenches can extend laterally in parallel along the word line direction (i.e., the X direction) and can extend vertically in the upper portion 1522 of the stack structure 1320. Each second trench can include a plurality of second trench segments that extend discontinuously along the word line direction (i.e., the X direction). Each first trench or second trench can expose the channel layer 1250 of the channel structures 1230 of two adjacent rows. It should be noted that the channel structures located at the corners of the second trench segments can be used as dummy channel structures. The conductive layer 1324 located in the upper portion 1522 of the stack structure 1320 can be divided into a plurality of sub-blocks 1570 / 1770 by the first trenches, while the discontinuous second trench segments do not separate the conductive layer 1324. That is, the channel structures 1230 of four adjacent rows between two adjacent first trenches can share one sub-block 1570 / 1770.

[0123] An appropriate etching process (e.g., dry etching and / or wet etching) can be performed to remove portions of the stack structure 1320 and portions of the channel structures 1230 to form the trenches 1580 / 1780. In some embodiments, the trenches can extend and penetrate through the top one to seven oxide / nitride layer pairs of the stack structure 1320. A mask layer (not shown) can be used to control the shape of the trenches 1580 / 1780 during the etching process. In the case of the first TSG cutouts 390 and the second TSG cutouts 380 as shown, the mask layer can be used to control the shape of the second trench segments. Figure 15In some embodiments shown, portions of the channel layer 1250 of the channel structure 1230 are also removed during the etching process. As such, the formed trenches 1580 / 1780 can have substantially straight sidewalls and can be used to form GLS cuts 790 as shown. Figure 5 In some other embodiments shown, portions of the channel layer 1250 of the channel structure 1230 are also removed during the etching process. As such, the formed trenches 1580 / 1780 can have substantially straight sidewalls and can be used to form GLS cuts 790 as shown. Figure 17 In some other embodiments shown, portions of the channel layer 1250 of the channel structure 1230 are also removed during the etching process. As such, the formed trenches 1580 / 1780 can have substantially straight sidewalls and can be used to form GLS cuts 790 as shown. Figure 7 The mask layer can be removed after the trenches 1580 / 1780 are formed.

[0124] Referring back to Figure 11 , the method proceeds to operation 1150 in which TSG cuts can be formed in the plurality of trenches. Figure 16 A cross-sectional view of a 3D structure after operation 1150 is shown in accordance with some embodiments of the present disclosure. Figure 18 A cross-sectional view of a 3D structure after operation 1150 is shown in accordance with some other embodiments of the present disclosure.

[0125] As shown in Figure 16 and 18 , in some embodiments, a deposition process can then be performed to fill the trenches 1580 / 1780 with any appropriate fill material (e.g., silicon oxide) to form TSG cuts 1690 / 1890. It should be noted that the formed TSG cuts 1690 / 1890 can be TSG cuts 190 as shown in Figure 1 or TSG cuts 380 / 390 as shown in Figure 3 Detailed features of the TSG cuts 1690 / 1890 can be referred to the descriptions above in connection with Figure 1 and Figure 3 . It should also be noted that the formed TSG cuts 1690 can be TSG cuts 590 as described above in connection with Figures 5-6 and the formed TSG cuts 1890 can be TSG cuts 790 as described above in connection with Figures 7-8 .

[0126] Accordingly, 3D memory devices and fabrication methods are provided. In some embodiments of the disclosed 3D memory devices, two rows of channel structures can be used as a set. As such, bit line connections do not require double patterning, but can be achieved by single patterning. That is, one layer of TSG structure plus one bit line can control a single row of channel structures, thereby reducing interference during programming and reading and reducing metal wiring. Further, in some embodiments of the disclosed 3D memory devices, channel structures corresponding to TSG structures can be designed to have a partial circular shape. That is, current switching of the channel structures can be controlled by the partial circular gate electrode of the TSG. As such, there is no need to design a split region as a dummy channel structure. The disclosed design of TSG isolation function can be fabricated by a simple process without increasing process cost and / or fabrication area.

[0127] The foregoing description of specific implementations will so fully reveal the general nature of the disclosure that others can apply its teachings in varied ways to other implementations without the exercise of inventive faculty and without the dedication of additional experiments to their further fruition. Accordingly, all such modifications and variations are intended to be included within the scope of the disclosed implementations as defined by the claims. Such

[0128] Embodiments of the disclosure have been described above with the aid of functional building blocks. Boundaries between functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified

[0129] The Summary and Abstract sections can have been set forth herein to especially delineate one or more implementations of the disclosure and are not intended to limit the disclosure and the appended claims in any way.

[0130] The breadth and scope of the present disclosure should not be limited by any of the above-described implementations, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor structure, comprising: a stack structure including a plurality of dielectric layers and conductive layers stacked alternately in a vertical direction; an array of channel structures each vertically penetrating the stack structure, each channel structure including a functional layer and a channel layer; a plurality of isolation structures extending in parallel along a first lateral direction and located vertically in an upper portion of the stack structure, each isolation structure contacting the channel layers of two adjacent rows of channel structures; and a plurality of gate line structures extending in parallel along the first lateral direction and vertically penetrating the stack structure; wherein a first number of the isolation structures located between adjacent gate line structures plus one is half of a second number of rows of channel structures located between the adjacent gate line structures.

2. The semiconductor structure of claim 1, wherein: each isolation structure partially covers the two adjacent rows of channel structures located in a lower portion of the stack structure.

3. The semiconductor structure of claim 2, wherein, the plurality of isolation structures includes: a plurality of first isolation structures each separating the conductive layers of the upper portion of the stack structure into sub-blocks.

4. The semiconductor structure of claim 1, wherein: the isolation structures contact curved side surfaces of the channel layers of the two adjacent rows of channel structures located in the upper portion of the stack structure.

5. The semiconductor structure of claim 1, wherein, the isolation structures contact fill structures of the two adjacent rows of channel structures located in the upper portion of the stack structure.

6. The semiconductor structure of claim 3, wherein: a column of channel structures extending along a second lateral direction and located on a same side of the first isolation structures is connected to a common bit line.

7. The semiconductor structure of claim 3, wherein, the plurality of isolation structures further includes: a plurality of second isolation structures each extending along the first lateral direction without separating the conductive layers of the upper portion of the stack structure; wherein the plurality of first isolation structures and the plurality of second isolation structures are arranged alternately along a second lateral direction.

8. The semiconductor structure of claim 7, wherein, the plurality of second isolation structures each includes a plurality of second isolation segments discontinuously extending along the first lateral direction.

9. The semiconductor structure of claim 7, wherein: a first subset of a column of channel structures extending along a second lateral direction and contacting the first isolation structures is connected to a first common bit line; and a second subset of the column of channel structures contacting the second isolation structures is connected to a second common bit line.

10. The semiconductor structure of claim 8, wherein, the array of channel structures includes: dummy channel structures contacting corners of the second isolation segments.

11. The semiconductor structure of claim 1, wherein: a lateral cross-section of the functional layer of the channel structures located in the upper portion of the stack structure has a partial ring shape; and two lateral ends of the partial ring shaped functional layer contact the isolation structures.

12. The semiconductor structure of claim 5, wherein: a lateral cross-section of the channel layer of the channel structures located in the upper portion of the stack structure has a partial ring shape; and The two lateral ends of the partially annular shaped channel layer are in contact with the isolation structures.

13. The semiconductor structure of claim 11, wherein: The partially annular shape is greater than one-third annular.

14. The semiconductor structure of claim 1, wherein: The isolation structures have a depth greater than a total thickness of a top pair of the dielectric layers and the conductive layers and less than a total thickness of a top seven pairs of the dielectric layers and the conductive layers.

15. A method of forming a semiconductor structure, comprising: forming a dielectric stack structure; forming an array of channel structures, each channel structure vertically traversing the dielectric stack structure, each channel structure including a functional layer and a channel layer; transforming the dielectric stack structure into a stack structure including a plurality of alternating stacked dielectric layers and conductive layers; removing portions of the channel structures and the stack structure located in an upper portion of the stack structure to form a plurality of trenches extending in parallel along a first lateral direction, each trench exposing the channel layers of two adjacent rows of channel structures located in the upper portion of the stack structure; and forming a plurality of isolation structures in the trenches, each isolation structure in contact with the channel layers of two adjacent rows of channel structures, wherein a plurality of gate line structures extending in parallel along the first lateral direction and vertically traversing the stack structure are formed, and wherein a first number of the isolation structures located between adjacent gate line structures plus one is equal to half of a second number of rows of channel structures located between the adjacent gate line structures.

16. The method of claim 15, wherein: each isolation structure is formed to partially cover the two adjacent rows of channel structures located in a lower portion of the stack structure.

17. The method of claim 16, wherein, forming the plurality of trenches includes: removing portions of the functional layers of the channel structures located in the upper portion of the stack structure.

18. The method of claim 17, wherein, forming the plurality of trenches further includes: removing portions of the channel layers of the channel structures located in the upper portion of the stack structure.

19. The method of claim 16, wherein, forming the plurality of isolation structures includes: forming the plurality of isolation structures in the trenches, each isolation structure in contact with curved side surfaces of the channel layers of the two adjacent rows of channel structures located in the upper portion of the stack structure.

20. The method of claim 18, wherein, forming the plurality of isolation structures includes: forming the plurality of isolation structures in the trenches, each isolation structure in contact with fill structures of the two adjacent rows of channel structures located in the upper portion of the stack structure.

21. The method of claim 16, wherein, forming the plurality of trenches includes: forming a plurality of first trenches, each first trench separating the conductive layers of the upper portion of the stack structure into sub-blocks.

22. The method of claim 21, further comprising: forming a plurality of bit lines extending in parallel along a second lateral direction, each bit line connected to a column of channel structures extending along the second lateral direction and located on a same side of the isolation structures.

23. The method of claim 21, further comprising: forming a plurality of second trenches each extending along the first lateral direction without separating the conductive layers of the upper portion of the stack structure; and forming a plurality of second isolation structures in the second trenches, wherein the plurality of first isolation structures and the plurality of second isolation structures are arranged alternately along a second lateral direction.

24. The method of claim 23, wherein: forming the plurality of second trenches comprises forming a plurality of second trench segments extending discontinuously along the first lateral direction; forming the plurality of second isolation structures comprises forming a plurality of second isolation segments in the plurality of second trench segments.

25. The method of claim 24, further comprising: forming dummy trench structures in contact with corners of the second isolation segments.

26. The method of claim 15, wherein: forming the dielectric stack structure comprises forming a plurality of dielectric layers and sacrificial layers stacked alternately in a vertical direction; transforming the dielectric stack structure into a stack structure comprises: forming a plurality of gate line structures extending in parallel along the first lateral direction and vertically through the dielectric stack structure, and replacing the sacrificial layers with conductive layers.

27. A semiconductor device, comprising: a plurality of isolation structures extending in parallel along a first lateral direction and vertically in an upper portion of a stack structure; and an array of trench structures each vertically through the stack structure and comprising: a lower trench portion having a cylindrical shape in a lower portion of the stack structure, and an upper trench portion having a partial cylindrical shape in the upper portion of the stack structure and in contact with a corresponding isolation structure. ​

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