Method for improving damage of ONO charge storage layer of SONOS device
By forming a bottom-up stacked ONO layer and gate structure in the SONOS device, and using an oxide layer and a sacrificial material layer to protect the ONO charge storage layer during the etching process, the problem of SONOS devices in the prior art damage to the ONO charge storage layer during the etching process is solved, and the performance and reliability of the device are improved.
Patent Information
- Application Number
- CN202510008405.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-05-06
AI Technical Summary
During the etching process, existing SONOS devices are prone to damage the ONO charge storage layer, thereby damaging the substrate, seriously affecting device performance.
The bottom-up ONO layer, gate and hard mask layer are formed on the substrate, and the cellular region LDD end etching is performed, the ONO layer outside the first side wall is removed, the oxide layer and the sacrificial material layer are deposited, the sacrificial material layer is etched and the hard mask layer is removed to protect the ONO charge storage layer.
Through this method, after the etching at the LDD end of the cell region is completed, the oxide layer prevents the ONO charge storage layer from being damaged, effectively protecting the charge storage layer and substrate, and improving device performance.
Smart Images
Figure CN119947113A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for improving damage to an ONO charge storage layer of a SONOS device. Background Art
[0002] As the size of devices decreases, the thickness of the gate oxide layer gradually decreases, and the device's data storage capacity decreases. SONOSFLASH is widely used due to its advantages such as lower wafer cost, easy integration of standard CMOS, lower programming voltage and higher reliability. SONOS devices use a gate stack structure of substrate-tunneling oxide layer-nitride layer-blocking oxide layer-polysilicon gate layer (i.e. SONOS), which is a charge trap type memory.
[0003] The nitride layer in ONO is a charge storage layer. When a positive bias voltage is applied to the gate and a negative bias voltage is applied to the S / D, the nitride electrons injected from the inversion region are stored in the nitride, the threshold voltage increases, the transistor is "off", and the battery is in the "0" state; when a negative bias is applied to the gate and a positive bias is applied to the S / D, positive charges are injected from the accumulation channel into the holes of the nitride and stored in the nitride, the threshold voltage decreases, the transistor is "on", and the battery is in the "1" state.
[0004] In the existing SONOS device logic process, the blocking oxide layer (upper oxide layer) in ONO is relatively thin, and the charge storage layer is easily damaged when the hard mask layer on the top of the gate is removed by wet etching. In the subsequent etching process, the damage is transferred to the bottom layer, that is, the substrate is damaged, which seriously affects the device performance. Summary of the invention
[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for improving damage to the ONO charge storage layer of a SONOS device, so as to solve the problem that the etching process of forming a SONOS device in the prior art causes damage to the charge storage layer and then damages the substrate.
[0006] To achieve the above-mentioned purpose and other related purposes, the present application provides a method for improving damage to an ONO charge storage layer of a SONOS device, comprising:
[0007] Step 1, providing a substrate, forming an ONO layer, a gate and a hard mask layer stacked from bottom to top on a cell region of the substrate, and forming a gate oxide layer, a gate and a hard mask layer stacked from bottom to top on a non-cell region of the substrate;
[0008] Step 2, forming a first spacer on both sides of the gate;
[0009] Step 3, performing LDD etching on the cell region to remove the ONO layer outside the first sidewall;
[0010] Step 4, depositing an oxide layer and a sacrificial material layer on the substrate in sequence;
[0011] Step 5, etching the sacrificial material layer to remove the sacrificial material layer located on the substrate surface and the top of the gate;
[0012] Step six, removing the hard mask layer.
[0013] Preferably, the thickness of the oxide layer is 25 angstroms to 30 angstroms, and the thickness of the sacrificial material layer is 100 angstroms to 150 angstroms.
[0014] Preferably, the sacrificial material layer and the hard mask layer are made of the same material.
[0015] Preferably, the materials of the sacrificial material layer and the hard mask layer include silicon nitride.
[0016] Preferably, the etching in step five is anisotropic dry etching.
[0017] Preferably, in step six, the hard mask layer is removed by a wet etching process.
[0018] Preferably, the wet etching solution is hydrofluoric acid and phosphoric acid.
[0019] Preferably, hydrofluoric acid removes oxides on the surfaces of the hard mask layer and the sacrificial material layer.
[0020] Preferably, the etching in step three is dry etching.
[0021] Preferably, the material of the first spacer includes silicon nitride.
[0022] As described above, the method for improving damage to the ONO charge storage layer of a SONOS device provided in the present application has the following beneficial effects: after etching of the LDD end of the cell region is completed, an oxide layer and a sacrificial material layer are deposited, and when the hard mask layer on the top of the gate is subsequently removed by pickling, the oxide layer prevents the ONO charge storage layer from being damaged. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0024] Figure 1A-Figure 1C It is a schematic diagram showing a cross-sectional structure of a device formed after each step is completed in a method of forming a gate structure of a cell region of a SONOS device in the prior art;
[0025] Figure 2 A flow chart showing a method for improving damage to the ONO charge storage layer of a SONOS device provided in an embodiment of the present application;
[0026] Figure 3A-Figure 3F It is a schematic diagram showing a cross-sectional structure of a device formed after each step is completed in the method for improving damage to the ONO charge storage layer of a SONOS device provided in an embodiment of the present application;
[0027] Figure 4 Electronic photograph showing that the ONO charge storage layer is not damaged compared with the method for improving the damage of the ONO charge storage layer of the SONOS device provided by the embodiment of the present application and the prior art. DETAILED DESCRIPTION
[0028] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0029] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0030] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0031] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0032] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0033] The steps of forming the gate structure of the cell region of a SONOS device in the prior art are as follows:
[0034] First, if Figure 1A As shown, an ONO layer 102 is first formed on a substrate 100 , and then a gate oxide layer 103 is formed by thermal oxidation, and then a gate 101 and a hard mask layer 105 are formed.
[0035] Then, if Figure 1B As shown, the hard mask layer 105 is removed by pickling with hydrofluoric acid and phosphoric acid. The pickling process causes damage 106 to the ONO layer 102 on both sides of the gate 101 .
[0036] Finally, if Figure 1C As shown, LDD etching is performed at the cell region end to remove the ONO layer 102 on both sides of the gate 101, and then sidewalls 107 are formed on both sides of the gate 101. During the LDD etching process at the cell region end, the thickness of the ONO layer 102 with damage 106 becomes thinner, and damage 108 is caused to the substrate 100 after etching. The damage to the active area seriously affects the device performance.
[0037] In order to solve this problem, the present application provides a method for improving the damage of the ONO charge storage layer of a SONOS device.
[0038] See also Figure 2 , which shows a flow chart of a method for improving damage to the ONO charge storage layer of a SONOS device provided in an embodiment of the present application.
[0039] like Figure 2 As shown, the method for improving the damage of the ONO charge storage layer of the SONOS device includes the following steps:
[0040] Step 1, providing a substrate, forming an ONO layer, a gate and a hard mask layer stacked from bottom to top on a cell region of the substrate, and forming a gate oxide layer, a gate and a hard mask layer stacked from bottom to top on a non-cell region of the substrate;
[0041] Step 2, forming a first spacer on both sides of the gate;
[0042] Step 3, performing LDD etching on the cell region to remove the ONO layer outside the first sidewall;
[0043] Step 4, depositing an oxide layer and a sacrificial material layer on the substrate in sequence;
[0044] Step 5, etching the sacrificial material layer to remove the sacrificial material layer located on the substrate surface and the top of the gate;
[0045] Step six, removing the hard mask layer.
[0046] In step one, if Figure 3A As shown, optionally, the substrate 300 is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate 1775.6, etc.; or the material of the substrate 300 may also include other materials, such as III-V compounds such as gallium arsenide. Those skilled in the art can select the constituent material of the substrate according to the type of device structure formed on the substrate 300, so the type of the substrate 300 should not limit the protection scope of the present invention.
[0047] Next, an ONO layer 302 is formed on the substrate 300. Exemplarily, the ONO layer 302 is composed of an oxide layer-a nitride layer-an oxide layer stacked in sequence, the nitride layer serves as a charge storage layer, and the thickness of the ONO layer 302 is 100 angstroms to 150 angstroms.
[0048] Next, the gate oxide layer 303 is grown by a thermal oxidation process, and the gate oxide layer 303 cannot be grown in the area covered by the ONO layer 302. Exemplarily, the thickness of the gate oxide layer 303 is 40 angstroms to 120 angstroms.
[0049] Afterwards, a gate material layer and a hard mask layer 305 are formed by a deposition process. The material of the gate material layer includes polysilicon, and the material of the hard mask layer 305 includes silicon nitride.
[0050] Next, the gate material layer is etched using the hard mask layer 305 as a mask to form the gate 301. After etching, an ONO layer 302, a gate 301, and a hard mask layer 305 are stacked from bottom to top on the cell region of the substrate 300, and a gate oxide layer 303, a gate 301, and a hard mask layer 305 are stacked from bottom to top on the non-cell region of the substrate 300.
[0051] In step 2, first spacers 306 are formed on both sides of the gate 301. As an example, the step of forming the first spacers 306 includes: forming a spacer material layer on the substrate 300 by a conformal deposition process; and etching the spacer material layer by an anisotropic etching process to form the first spacers 306.
[0052] Exemplarily, the material of the first spacer 306 includes silicon nitride.
[0053] In step three, LDD etching is performed on the cell region to remove the ONO layer 302 outside the first sidewall 306. As an example, before performing the etching, a photoresist mask layer is formed on the substrate 300 to expose only the cell region; the etching is dry etching, and after the etching is completed, the photoresist mask layer is removed by an ashing process.
[0054] In step 4, an oxide layer 307 and a sacrificial material layer 308 are sequentially deposited on the substrate 300 by a conformal deposition process. Exemplarily, the material of the oxide layer 307 includes silicon oxide, and the material of the sacrificial material layer 308 is the same as that of the hard mask layer 305; the thickness of the oxide layer 307 is 25 angstroms to 30 angstroms, and the thickness of the sacrificial material layer 308 is 100 angstroms to 150 angstroms.
[0055] In step five, the sacrificial material layer 308 is etched to remove the sacrificial material layer 308 located on the surface of the substrate 300 and the top of the gate 301. As an example, the etching is anisotropic dry etching.
[0056] In step six, the hard mask layer 305 is removed by a wet etching process. As an example, the wet etching solution is hydrofluoric acid and phosphoric acid, and the hydrofluoric acid is used to remove the oxide on the surface of the hard mask layer 305 and the sacrificial material layer 308. The process of removing the hard mask layer 305 removes the remaining sacrificial material layer 308 and the oxide layer 307 located on the surface of the substrate 300 and the top of the gate 301, and the remaining oxide layer 307 serves as the second sidewall of the gate 301.
[0057] See also Figure 4 Compared with the prior art, the method for improving damage to the ONO charge storage layer of a SONOS device provided in the present application does not cause damage to the ONO charge storage layer when the hard mask layer on the top of the gate is removed by wet etching.
[0058] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0059] In summary, the method for improving the damage of the ONO charge storage layer of the SONOS device provided by the present application is to deposit an oxide layer and a sacrificial material layer after the etching of the LDD end of the cell region is completed. When the hard mask layer on the top of the gate is subsequently removed by pickling, the oxide layer prevents the ONO charge storage layer from being damaged. Therefore, the present application effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0060] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present application.
Claims
1. A method for improving the damage of the ONO charge storage layer of a SONOS device, characterized in that: The method comprises: Step 1, providing a substrate, forming an ONO layer, a gate and a hard mask layer stacked from bottom to top on a cell region of the substrate, and forming a gate oxide layer, a gate and a hard mask layer stacked from bottom to top on a non-cell region of the substrate; Step 2, forming a first sidewall spacer on both sides of the gate; Step 3, performing LDD etching on the cell region to remove the ONO layer outside the first sidewall; Step 4, depositing an oxide layer and a sacrificial material layer on the substrate in sequence; Step 5, etching the sacrificial material layer to remove the sacrificial material layer located on the surface of the substrate and the top of the gate; Step six, removing the hard mask layer.
2. The method according to claim 1, characterized in that The thickness of the oxide layer is 25 angstroms to 30 angstroms, and the thickness of the sacrificial material layer is 100 angstroms to 150 angstroms.
3. The method according to claim 1, characterized in that The sacrificial material layer and the hard mask layer are made of the same material.
4. The method according to claim 3, characterized in that The materials of the sacrificial material layer and the hard mask layer include silicon nitride.
5. The method according to claim 1, characterized in that The etching in step five is anisotropic dry etching.
6. The method according to claim 1, characterized in that In the step six, the hard mask layer is removed by a wet etching process.
7. The method according to claim 6, characterized in that The wet etching solution is hydrofluoric acid and phosphoric acid.
8. The method according to claim 7, characterized in that The hydrofluoric acid removes oxides on the surfaces of the hard mask layer and the sacrificial material layer.
9. The method according to claim 1, characterized in that: The etching in step three is dry etching.
10. The method according to claim 1, characterized in that The material of the first spacer includes silicon nitride.