Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate, sequentially forming a gate oxide layer and a gate structure on the surface of the substrate from bottom to top, and enabling the gate structure to expose the peripheral region of the gate oxide layer; etching the substrate at two sides of the gate oxide layer to form a groove; performing ion implantation on the peripheral area to form an anti-diffusion area so as to prevent diffusion of boron elements; and forming a germanium-silicon epitaxial layer in the groove. In the forming process of the germanium-silicon epitaxial layer, the ion implantation is performed on the substrate to form the anti-diffusion region so as to prevent boron elements in the subsequently formed germanium-silicon epitaxial layer from diffusing to the substrate to influence the lattice structure of the substrate and further cause failure of time-dependent breakdown performance of the gate oxide layer covering the surface of the foundation; and the reliability of the device can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In the existing semiconductor device manufacturing process, since stress can change the carrier mobility of silicon materials, improving the performance of semiconductor devices by changing stress has become a common method.

[0003] At present, embedded silicon germanium technology is an effective technology for improving carrier mobility. That is, silicon germanium material is first formed in the area where the source and drain regions of the PMOS area need to be formed, and then doped to form the source and drain regions of the PMOS device. The formation of silicon germanium material can introduce compressive stress formed by lattice mismatch between silicon and silicon germanium, so as to improve the performance of the PMOS device.

[0004] However, in actual applications, it was found that the boron contained in the germanium silicon epitaxial layer would diffuse into the channel. Since the atoms of the boron element are relatively large, diffusing into the channel would affect the lattice structure of silicon, causing the gate oxide layer formed on the channel to fail due to time-dependent dielectric breakdown (TDDB), thereby reducing the reliability of the device. Summary of the invention

[0005] The object of the present invention is to provide a semiconductor structure and a method for forming the same, so as to solve the problem of failure of the breakdown performance of the gate oxide layer over time.

[0006] In order to solve the above technical problems, the present invention provides a semiconductor structure and a method for forming the same, wherein the method for forming the semiconductor structure comprises: providing a substrate, and sequentially forming a gate oxide layer and a gate structure on the surface of the substrate from bottom to top, wherein the gate structure exposes the peripheral area of ​​the gate oxide layer; performing an etching process on the substrate on both sides of the gate oxide layer to form a groove; performing ion implantation on the substrate below the peripheral area to form an anti-diffusion area, wherein the anti-diffusion area is used to prevent the diffusion of boron elements; and forming a germanium silicon epitaxial layer in the groove.

[0007] Preferably, in the method for forming the semiconductor structure, the element implanted by the ions includes carbon.

[0008] Preferably, in the method for forming the semiconductor structure, after performing the ion implantation process, the method further comprises: using a heat treatment process to repair lattice damage on the surface of the substrate caused by the ion implantation process.

[0009] Preferably, in the method for forming the semiconductor structure, after repairing the surface of the substrate and before forming the germanium silicon epitaxial layer, the method further includes: performing a hydrogen plasma process on the surface of the substrate.

[0010] Preferably, in the method for forming the semiconductor structure, after performing the hydrogen plasma process and before forming the germanium silicon epitaxial layer, it also includes: performing a silicon-cobalt-nickel deoxidation process on the surface of the substrate.

[0011] Preferably, in the method for forming the semiconductor structure, the trench is a sigma-type trench.

[0012] Preferably, in the method for forming the semiconductor structure, the method for etching the surface of the substrate to form the sigma-type groove includes: dry etching the substrate to form an initial groove in the substrate; wet etching the initial groove to form the sigma-type groove in the substrate.

[0013] Preferably, in the method for forming the semiconductor structure, the etching solution used in the wet etching includes tetramethylammonium hydroxide.

[0014] Preferably, in the method for forming the semiconductor structure, the germanium silicon epitaxial layer includes a buffer layer, a main layer and a cap layer stacked in sequence from bottom to top in the groove, and the buffer layer, the main layer and the cap layer are doped with boron elements with increasing concentrations.

[0015] The present invention further provides a semiconductor structure, wherein the semiconductor structure is formed using any of the above-mentioned methods for forming a semiconductor structure.

[0016] To sum up, the present invention forms an anti-diffusion region by performing ion implantation on the substrate to block the diffusion of boron elements in the subsequently formed germanium silicon epitaxial layer, thereby avoiding the influence of the lattice structure of the substrate due to the diffusion of boron elements into the substrate, thereby avoiding the failure of the breakdown performance of the gate oxide layer covering the surface of the substrate over time, and effectively improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of a structure for forming an initial groove according to an embodiment of the present invention;

[0019] Figure 3 is a schematic diagram of a structure for forming a sigma-type groove according to an embodiment of the present invention;

[0020] Figure 4 is a schematic structural diagram of performing ion implantation on a substrate after forming an initial trench according to an embodiment of the present invention;

[0021] Figure 5 is a schematic structural diagram of performing ion implantation on a substrate after forming a sigma-type trench according to an embodiment of the present invention;

[0022] Figure 6 is a schematic structural diagram of forming a germanium silicon epitaxial layer according to an embodiment of the present invention;

[0023] Wherein, each figure is marked as:

[0024] 10-base;

[0025] 20-gate oxide layer;

[0026] 30-gate structure;

[0027] 410 - initial groove;

[0028] 420-sigma type groove;

[0029] 50-silicon germanium epitaxial layer;

[0030] 510- buffer layer;

[0031] 520-main layer;

[0032] 530-capping layer;

[0033] 60-Ion implantation direction. DETAILED DESCRIPTION

[0034] The present embodiment provides a semiconductor structure and a method for forming the same, which will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis that each drawing needs to show is different, and sometimes different proportions are used.

[0035] It should be understood that spatial relationship terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0036] See also Figure 1 , an embodiment of the present invention provides a method for forming a semiconductor structure, comprising:

[0037] S1, providing a substrate, and forming a gate oxide layer and a gate structure from bottom to top on the surface of the substrate, wherein the gate structure exposes a peripheral area of ​​the gate oxide layer;

[0038] S2, performing an etching process on the substrate at both sides of the gate oxide layer to form a groove;

[0039] S3, performing an ion implantation process on the substrate below the peripheral region to form an anti-diffusion region, wherein the anti-diffusion region is used to prevent diffusion of boron elements; and

[0040] S4, forming a silicon germanium epitaxial layer in the trench.

[0041] The embodiment of the present invention forms the anti-diffusion region by performing ion implantation on the substrate to block the diffusion of the boron element in the subsequently formed germanium silicon epitaxial layer, thereby preventing the boron element from diffusing into the substrate and affecting the lattice structure of the substrate, thereby preventing the time-dependent breakdown performance failure of the gate oxide layer covering the surface of the substrate, and effectively improving the reliability of the device.

[0042] The following combination Figure 2 to Figure 6 Steps S1 to S4 are described in further detail.

[0043] First, step S1 is performed to provide a substrate 10 , and to form a gate oxide layer 20 and a gate structure 30 from bottom to top on the surface of the substrate 10 , wherein the gate structure 30 exposes the peripheral region of the gate oxide layer 20 .

[0044] Optionally, the substrate 10 may include semiconductor elements, such as silicon or silicon germanium (SiGe) in a single crystal structure, or a mixed semiconductor structure, such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, an alloy semiconductor or a combination thereof; it may also be silicon on insulator (SOI). In addition, the substrate 10 may also include other materials, such as a multilayer structure of an epitaxial layer or a buried layer. Although several examples of materials that can form the substrate 10 are described herein, any material that can be used as the substrate 10 falls within the scope of protection of the present invention.

[0045] Optionally, the gate oxide layer 20 is made of silicon oxide with good insulation performance. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which is conducive to reducing the process difficulty and cost of forming the gate oxide layer 20.

[0046] In this embodiment, the gate structure 30 is made of polysilicon; in some other embodiments, the gate structure 30 may also be made of amorphous carbon.

[0047] It should be understood that when the gate oxide layer 20 and the gate structure 30 are formed in sequence, the gate oxide layer 20 is not completely covered by the gate structure 30, so that the gate oxide layer 20 is exposed. The peripheral area refers to the area of ​​the gate oxide layer 20 that is not covered by the gate structure 210. The present application does not impose any specific limitation on the size of the peripheral area.

[0048] For the performance of the semiconductor structure, the time-dependent breakdown performance of the gate oxide layer 20 is a very important performance parameter. If the time-dependent breakdown performance of the gate oxide layer 20 is too low, the leakage failure ratio between the gate structure 30 and the source region and the drain region formed on both sides of the gate structure 30 will increase, and in severe cases, it may even cause the entire semiconductor structure to be scrapped. Therefore, it is very necessary to improve the reliability of the time-dependent breakdown performance of the gate oxide layer 20.

[0049] Then, execute step S2, see Figure 2-3 , an etching process is performed on the substrate 10 at both sides of the gate oxide layer 20 to form trenches.

[0050] In this embodiment, a plurality of gate structures 30 are generally formed on the surface of the substrate 10, and trenches are formed in the source / drain regions on both sides of the gate structures 30. In a subsequent process, a germanium silicon epitaxial layer is formed in the trenches to enhance the stress on the channel region below the gate structures 30. To simplify the description, only two trenches on both sides of one gate structure 30 are shown in the drawings of this embodiment.

[0051] Optionally, the groove may be a U-shaped groove or a sigma-shaped groove 420. In the embodiment of the present invention, the sigma-shaped groove 420 is taken as an example. The method of forming the sigma-shaped groove 420 includes: Figure 2 As shown, the substrate 10 is dry-etched to form an initial trench 410 in the substrate 10; the initial trench 410 is wet-etched to form a Figure 3 Sigma-type groove 420 is shown.

[0052] The initial groove 410 may be U-shaped or spherical. The cross section of the U-shaped groove is U-shaped, and the cross section of the spherical groove is a bowl-shaped groove with an open top. In this embodiment, the initial groove 410 is a U-shaped groove.

[0053] Optionally, the dry etching process used in step S2 includes, but is not limited to, reactive ion etching, ion beam etching, plasma etching or laser cutting.

[0054] Specifically, the wet etching etching solution includes: ammonia solution, tetramethylammonium hydroxide etching solution, potassium hydroxide etching solution, etc. Preferably, the etching solution used for wet etching includes tetramethylammonium hydroxide etching solution. The tetramethylammonium hydroxide etching solution has a high corrosion rate and good crystal surface selectivity. When etching the groove, different directions of the groove can have different etching rates, and the operation space is large. In addition, the tetramethylammonium hydroxide etching solution does not contain metal ions, and there will be no metal ion residue and contamination after etching, which will not cause damage to the structure of the groove, and has a very high etching selectivity, which makes it easier to etch and form a sigma-type groove 420.

[0055] Next, execute step S3, see Figure 4-5 , an ion implantation process is performed on the substrate 10 below the peripheral region to form an anti-diffusion region, wherein the anti-diffusion region is used to prevent the diffusion of boron elements.

[0056] In this embodiment, carbon ion implantation is performed on the substrate 10 below the peripheral area, and the ion implantation direction is as shown in the direction 60. The anti-diffusion region formed after the carbon ion implantation can effectively inhibit the diffusion of boron elements to protect the lattice structure of the substrate 10 from the influence of the diffusion of boron elements, thereby improving the reliability of the time-dependent breakdown performance of the gate oxide layer 20.

[0057] It is understandable that in a general ion implantation process, although ions are implanted in a certain direction at a specific position, in this embodiment, the specific position is the substrate 10 below the peripheral area, but in actual operation, due to process errors, a small amount of ions may also exist in other areas besides the specific position.

[0058] After the ion implantation process is performed, a heat treatment process is required to repair the lattice damage on the surface of the substrate 10 caused by the ion implantation process. Optionally, the heat treatment process is performed in a hydrogen atmosphere so that the lattice on the surface of the substrate 10 caused by the ion implantation process is self-reorganized in a thermal environment to repair the ion implantation damage.

[0059] As in the above step S2, the groove in this embodiment is a sigma-type groove 420, and the method for forming the sigma-type groove 420 includes: forming an initial groove 410 and continuing to etch on the basis of the initial groove 410 to form the sigma-type groove 420; it is worth noting that, as an embodiment, Figure 4 As shown, the carbon ion implantation process can be performed after forming the initial trench 410 and before forming the sigma-type trench 420; as another embodiment, Figure 5 As shown, the carbon ion implantation process may be performed after forming the sigma-type trench 420 .

[0060] Further, when the carbon ion implantation process is performed after the initial groove 410 is formed and before the sigma-type groove 420 is formed, the subsequent heat treatment process is also performed after the initial groove 410 is formed and before the sigma-type groove 420 is formed, and then the sigma-type groove 420 is formed by etching on the basis of the initial groove 410; when the ion implantation process is performed after the sigma-type groove 420 is formed, the subsequent heat treatment process is also performed after the sigma-type groove 420 is formed. The above two embodiments are both within the protection scope of the present invention.

[0061] After repairing the surface of the substrate 10 and before forming the germanium silicon epitaxial layer, it also includes: sequentially performing a hydrogen plasma process and a silicon cobalt nickel deoxidation process on the surface of the substrate 10, wherein the hydrogen plasma process can effectively remove carbon on the surface of the substrate 10, and the silicon cobalt nickel deoxidation process can effectively remove oxygen on the surface of the substrate 10, so as to provide a good formation environment for the subsequent formation of the germanium silicon epitaxial layer in the groove, and ensure the better structure and performance of the germanium silicon epitaxial layer. It can be understood that the above-mentioned carbon elements and oxygen elements are both present in the form of thin films. Among them, the above-mentioned oxygen element that needs to be removed comes from the oxygen in the air. When the substrate 10 is subjected to processes such as ion implantation or high-temperature heat treatment, it comes into contact with the oxygen in the air to form an oxide film.

[0062] The silicon cobalt nickel deoxidation process (SiCoNi) used in this embodiment is a low-intensity chemical etching method, which is mainly used to remove oxide films from the surface of cobalt silicon and nickel silicon. Unlike the traditional etching method using plasma bombardment, the silicon cobalt nickel deoxidation process removes the oxide film in an environment without plasma and particle bombardment, which can reduce the degree of damage to the substrate 10, not only effectively remove the oxygen element on the surface of the substrate 10, but also ensure the integrity of the surface structure of the substrate 10.

[0063] In order to further provide a good formation environment for the formation of the germanium silicon epitaxial layer, before forming the germanium silicon epitaxial layer, it also includes: performing a wet cleaning process on the surface of the substrate 10, optionally, the cleaning liquid used in the wet cleaning process includes DHF cleaning liquid, and the DHF cleaning liquid is a diluted hydrofluoric acid cleaning liquid.

[0064] Finally, execute step S4, see Figure 6 , a silicon germanium epitaxial layer 50 is formed in the trench.

[0065] Specifically, the SiGe epitaxial layer 50 includes a buffer layer 510 , a main layer 520 and a cap layer 530 stacked in sequence from bottom to top in the trench, and the buffer layer 510 , the main layer 520 and the cap layer 530 are doped with boron elements with increasing concentrations.

[0066] like Figure 6As shown, generally, the cap layer 530 with a higher boron doping portion protrudes from the surface of the substrate 10, and since the content of boron in the cap layer 530 is higher than that in the buffer layer 510 and the main layer 520, the boron diffusion of the germanium silicon epitaxial layer 50 mainly comes from the diffusion of the boron in the cap layer 530, and the diffusion position is the portion of the substrate 10 close to the opening end of the groove.

[0067] In order to effectively prevent the diffusion of boron elements, this embodiment performs an ion implantation process on the substrate 10 below the peripheral area, and forms an anti-diffusion area on the substrate 10 near the cap layer 530, which can prevent the diffusion of boron elements and avoid affecting the lattice structure of the substrate 10 due to the diffusion of boron elements into the substrate 10, thereby avoiding the failure of the breakdown performance of the gate oxide layer 20 covering the surface of the substrate 10 over time, and effectively improving the reliability of the device.

[0068] An embodiment of the present invention also provides a semiconductor structure formed using the above-mentioned semiconductor structure forming method, wherein an anti-diffusion region is formed in the substrate of the semiconductor structure, which can effectively inhibit the diffusion of boron elements in the germanium silicon epitaxial layer to avoid the failure of the gate oxide layer's breakdown performance over time.

[0069] In summary, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, wherein the method for forming the semiconductor structure comprises: providing a substrate, sequentially forming a gate oxide layer and a gate structure on the surface of the substrate from bottom to top, wherein the gate structure exposes the peripheral region of the gate oxide layer; performing an etching process on the substrate on both sides of the gate oxide layer to form a groove; performing an ion implantation process on the substrate below the peripheral region to form an anti-diffusion region, wherein the anti-diffusion region is used to prevent the diffusion of boron elements; and forming a germanium silicon epitaxial layer in the groove. The embodiment of the present invention forms the anti-diffusion region by performing ion implantation on the substrate to block the diffusion of boron elements in the subsequently formed germanium silicon epitaxial layer, thereby preventing the lattice structure of the substrate from being affected by the diffusion of boron elements into the substrate, thereby preventing the time-dependent breakdown performance failure of the gate oxide layer covering the surface of the substrate, and effectively improving the reliability of the device.

[0070] In addition, it should be recognized that although the present invention application has been disclosed as above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, and forming a gate oxide layer and a gate structure in sequence from bottom to top on the surface of the substrate, wherein the gate structure exposes a peripheral area of ​​the gate oxide layer; Performing an etching process on the substrate at both sides of the gate oxide layer to form a groove; Performing an ion implantation process on the substrate below the peripheral region to form an anti-diffusion region, wherein the anti-diffusion region is used to prevent diffusion of boron elements; as well as, A silicon germanium epitaxial layer is formed in the trench.

2. The method for forming a semiconductor structure according to claim 1, wherein: The ion implantation includes carbon ion implantation.

3. The method for forming a semiconductor structure according to claim 1, wherein: After performing the ion implantation process, the method further includes: using a heat treatment process to repair the lattice damage on the surface of the substrate caused by the ion implantation process.

4. The method for forming a semiconductor structure according to claim 1, wherein: After repairing the surface of the substrate and before forming the germanium silicon epitaxial layer, the method further includes: performing a hydrogen plasma process on the surface of the substrate.

5. The method for forming a semiconductor structure according to claim 1, wherein: After performing the hydrogen plasma process and before forming the germanium silicon epitaxial layer, the method further includes: performing a silicon-cobalt-nickel deoxidation process on the surface of the substrate.

6. The method for forming a semiconductor structure according to claim 1, wherein: The groove is a sigma-type groove.

7. The method for forming a semiconductor structure according to claim 6, wherein: The method of etching the surface of the substrate to form the sigma-type groove comprises: dry etching the substrate to form an initial trench in the substrate; The initial trench is wet etched to form the sigma trench in the substrate.

8. The method for forming a semiconductor structure according to claim 7, wherein: The etching solution used in the wet etching includes tetramethylammonium hydroxide etching solution.

9. The method for forming a semiconductor structure according to claim 1, wherein: The silicon germanium epitaxial layer includes a buffer layer, a main layer and a cap layer which are sequentially stacked from bottom to top in the trench, and the buffer layer, the main layer and the cap layer are doped with boron elements with increasing concentrations.

10. A semiconductor structure, characterized in that: The semiconductor structure is formed by the method for forming a semiconductor structure according to any one of claims 1 to 9.

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