Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, in the preparation method of the semiconductor device, firstly, an interlayer dielectric layer is formed on the surface of a semiconductor structure, the interlayer dielectric layer comprises a first silicon nitride layer, a silicon-rich oxide layer and a silicon oxide layer, then, a conductive plug is formed in the interlayer dielectric layer, and the first silicon nitride layer, the silicon-rich oxide layer and the silicon oxide layer are formed on the surface of the semiconductor structure. And forming a patterned metal layer on the surfaces of the interlayer dielectric layer and the conductive plug, and finally forming a passivation layer. According to the invention, the first silicon nitride layer, the silicon-rich oxide layer and the silicon oxide layer which are stacked in sequence are used as the interlayer dielectric layer, and movable charges brought by plasma at a packaging end or in a back-end process can be effectively blocked, so that the influence of electrons or impurities on a channel when the device is started is effectively avoided, and the reliability of the device is remarkably improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] In traditional planar MOS (metal oxide semiconductor) devices, the source, gate and drain of the MOS transistor are all located on the horizontal plane of the silicon wafer, which not only occupies a large area, but also has a large on-resistance and power consumption, and cannot meet the requirements of miniaturization and low power consumption of power devices. Trench MOS devices, on the other hand, cleverly form the gate of the transistor in a trench perpendicular to the surface of the silicon wafer, so that the conduction channel is transferred to the longitudinal direction of the silicon wafer. This has three advantages: (1) reducing the device area and further improving the device integration density; (2) effectively reducing the on-resistance and power consumption; (3) basically eliminating the lateral flow of holes in the P well, effectively suppressing the pnpn latch effect (the pnpn latch effect refers to the parasitic pnpn transistor of the device being turned on when the operating current of the device is greater than the latch critical current, while the MOS transistor that actually controls the device may not be turned on at this time, so the external circuit cannot control the shutdown of the device through the MOS transistor). Therefore, trench MOS devices are widely used in power devices.

[0003] As a power device, the reliability of trench MOS devices is particularly important. The reliability HTRB (High Temperature Reverse Bias) test of the power device manufacturing process is closely related to product design and process conditions.

[0004] However, due to the poor barrier performance of the interlayer dielectric layer of existing products, electrons or impurities enter the product channel during the process, causing the existing products to fail in the reliability HTRB assessment. Summary of the invention

[0005] The present application provides a semiconductor device and a method for preparing the same, which can solve the problem of poor barrier performance of an interlayer dielectric layer affecting device reliability in existing power device products.

[0006] On the one hand, an embodiment of the present application provides a method for preparing a semiconductor device, comprising: Providing a semiconductor structure, wherein a conductive structure is formed in the semiconductor structure; forming an interlayer dielectric layer, wherein the interlayer dielectric layer comprises: a first silicon nitride layer, a silicon-rich oxide layer and a silicon oxide layer, wherein the first silicon nitride layer covers the semiconductor structure and the conductive structure, the silicon-rich oxide layer covers the first silicon nitride layer, and the silicon oxide layer covers the silicon-rich oxide layer; Etching the interlayer dielectric layer to the surface of the conductive structure to form a plurality of through holes; forming a conductive plug, wherein the conductive plug fills the through hole; forming a patterned metal layer, wherein the patterned metal layer covers the conductive plug and a portion of the interlayer dielectric layer; A passivation layer is formed, wherein the passivation layer covers the patterned metal layer and a portion of the interlayer dielectric layer.

[0007] Optionally, in the method for preparing the semiconductor device, the step of forming the interlayer dielectric layer includes: forming the first silicon nitride layer by a furnace tube process, wherein the first silicon nitride layer covers the semiconductor structure and the conductive structure; The silicon-rich oxide layer is formed by a PECVD (plasma enhanced chemical vapor deposition) process, and the silicon-rich oxide layer covers the first silicon nitride layer; TEOS gas is introduced into the process chamber and the PECVD process is adopted to form the silicon oxide layer, and the silicon oxide layer covers the silicon-rich oxide layer.

[0008] Optionally, in the method for preparing the semiconductor device, the thickness of the first silicon nitride layer is 300Å~1000Å; the thickness of the silicon-rich oxide layer is 1000Å~2000Å; and the thickness of the silicon oxide layer is 3000Å~8000Å.

[0009] Optionally, in the method for preparing the semiconductor device, the step of forming a passivation layer includes: forming a second silicon nitride layer by a PECVD process, wherein the second silicon nitride layer covers the patterned metal layer; A silicon-rich nitride layer is formed by adopting a PECVD process, and the silicon-rich nitride layer covers the second silicon nitride layer.

[0010] Optionally, in the method for preparing the semiconductor device, the thickness of the second silicon nitride layer is 800Å~2000Å; the thickness of the silicon-rich nitride layer is 8000Å~20000Å.

[0011] Optionally, in the method for preparing the semiconductor device, the semiconductor device is a trench MOS device, and the conductive structure is a trench gate structure.

[0012] On the other hand, an embodiment of the present application further provides a semiconductor device, including: A semiconductor structure having a conductive structure formed therein; An interlayer dielectric layer, wherein the interlayer dielectric layer comprises: a first silicon nitride layer, a silicon-rich oxide layer and a silicon oxide layer, the first silicon nitride layer covers the semiconductor structure and the conductive structure, the silicon-rich oxide layer covers the first silicon nitride layer, and the silicon oxide layer covers the silicon-rich oxide layer; A plurality of through holes, wherein the through holes are located in the interlayer dielectric layer; a conductive plug filling the through hole; A patterned metal layer, wherein the patterned metal layer covers the conductive plug and a portion of the interlayer dielectric layer; A passivation layer covers the patterned metal layer and a portion of the interlayer dielectric layer.

[0013] Optionally, in the semiconductor device, the thickness of the first silicon nitride layer is 300Å~1000Å; the thickness of the silicon-rich oxide layer is 1000Å~2000Å; and the thickness of the silicon oxide layer is 3000Å~8000Å.

[0014] Optionally, in the semiconductor device, the passivation layer includes: a second silicon nitride layer and a silicon-rich nitride layer, the second silicon nitride layer covers the patterned metal layer, and the silicon-rich nitride layer covers the second silicon nitride layer.

[0015] Optionally, in the semiconductor device, the thickness of the second silicon nitride layer is 800Å~2000Å; the thickness of the silicon-rich nitride layer is 8000Å~20000Å.

[0016] The technical solution of this application has at least the following advantages: The present application adopts a first silicon nitride layer, a silicon-rich oxide layer and a silicon oxide layer stacked in sequence as the interlayer dielectric layer of the semiconductor device, which can effectively block the movable charges brought by the plasma at the packaging end or the back-end process (such as PECVD process, etching process, etc.), thereby preventing electrons or impurities from affecting the channel when the device is turned on, thereby significantly improving the reliability of the device.

[0017] Furthermore, the present application uses a second silicon nitride layer and a silicon-rich nitride layer stacked in sequence as a passivation layer covering the patterned metal layer, which can further effectively block the movable charges brought by the Plasma at the packaging end or the back-end process (such as PECVD process, etching process, etc.), thereby avoiding electrons or impurities from affecting the channel when the device is turned on, and further significantly improving the device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 is a flow chart of a method for preparing a semiconductor device according to an embodiment of the present invention; Figure 2-Figure 6 is a schematic diagram of a semiconductor structure in each process step of preparing a semiconductor device according to an embodiment of the present invention; The reference numerals are described as follows: 10-substrate, 11-isolation oxide material, 12-trench gate, 13-ion implantation region, 14-shielding gate, 15-pad oxide layer, 20-interlayer dielectric layer, 21-first silicon nitride layer, 22-silicon-rich oxide layer, 23-silicon oxide layer, 31-first conductive plug, 32-second conductive plug, 33-third conductive plug, 40-patterned metal layer, 50-passivation layer, 51-second silicon nitride layer, 52-silicon-rich nitride layer. DETAILED DESCRIPTION

[0020] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0021] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0022] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0023] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0024] The present application provides a method for preparing a semiconductor device, referring to Figure 1 , Figure 1 1 is a flow chart of a method for preparing a semiconductor device according to an embodiment of the present invention, wherein the method for preparing a semiconductor device comprises: First, perform step S1: refer to Figure 2 , Figure 2 Schematic diagram of a semiconductor structure having a conductive structure formed therein according to an embodiment of the present application, providing a semiconductor structure having a conductive structure formed therein.

[0025] In this embodiment, the semiconductor device can be a trench MOS device, and the conductive structure is a trench gate 12, a shielding gate 14 and an ion implantation region 13 on the side of the trench gate structure in the trench gate structure. Specifically, the semiconductor device at least includes: a substrate 10, multiple trench gate structures, an ion implantation region 13 located in the substrate 10 and close to the surface of the substrate 10, and a pad oxide layer 15 covering the ion implantation region 13.

[0026] Furthermore, the trench gate structure is located in a trench in the substrate 10, and the trench gate structure at least includes: an isolation oxide material 11, a trench gate 12 and a shield gate 14, and the trench gate 12 serves as a gate of a trench MOS device. Figure 2 In the figure, from left to right, the trench gate structures in the first trench and the second trench are trench gate structures at the device ends, the first trench gate structure leads to the gate of the trench MOS device, and the second trench gate structure leads to the shielding gate of the trench MOS device; the third trench gate structure and the fourth trench gate structure are both normal trench gate structures inside the trench MOS device.

[0027] The shield gate 14 serves as a field plate of the trench MOS device, which helps balance the charge inside the device and improves the withstand voltage of the device. When the ion implantation region 13 applies pressure to the trench gate 12, it can attract electrons and form a channel when the device is turned on.

[0028] It is worth noting that the present application does not impose any limitation on the specific film layers in the semiconductor structure. It is only necessary to ensure that a conductive structure that needs to be led out by a conductive plug is formed in the semiconductor structure.

[0029] Then, execute step S2: refer to Figure 3 , Figure 3 It is a schematic diagram of the semiconductor structure after the interlayer dielectric layer is formed in an embodiment of the present application, wherein the interlayer dielectric layer 20 is formed, wherein the interlayer dielectric layer 20 includes: a first silicon nitride layer 21, a silicon-rich oxide layer 22 and a silicon oxide layer 23, the first silicon nitride layer 21 covers the ion implantation region 13 and the trench gate structure, the silicon-rich oxide layer 22 covers the first silicon nitride layer 21, and the silicon oxide layer 23 covers the silicon-rich oxide layer 22.

[0030] Preferably, the steps of forming the interlayer dielectric layer 20 include: Step S2.1: forming the first silicon nitride layer 21 by a furnace process, wherein the first silicon nitride layer 21 covers the ion implantation region 13 and the trench gate structure; Step S2.2: forming the silicon-rich oxide layer 22 by a PECVD process, wherein the silicon-rich oxide layer 22 covers the first silicon nitride layer 21; Step S2.3: TEOS gas is introduced into the process chamber and the PECVD process is used to decompose the TEOS (tetraethyl orthosilicate) gas, thereby forming the silicon oxide layer 23 (PETEOS) on the silicon-rich oxide layer 22 , and the silicon oxide layer 23 covers the silicon-rich oxide layer 22 .

[0031] Preferably, the thickness of the first silicon nitride layer 21 is 300Å~1000Å; the thickness of the silicon-rich oxide layer 22 is 1000Å~2000Å; and the thickness of the silicon oxide layer 23 is 3000Å~8000Å.

[0032] In the interlayer dielectric layer 20, the first silicon nitride layer 21 has good compactness and can prevent the mobile ions brought by the plasma in the later process from invading the semiconductor structure at the bottom of the interlayer dielectric layer; in addition, since the first silicon nitride layer 21 is generated by introducing gases such as methane and ammonia into the process chamber and adopting a furnace tube process reaction, the first silicon nitride layer 21 contains H atoms, and the H atoms mainly exist in the form of Si-H bonds. After high-temperature diffusion, the H atoms will diffuse to the interface between the pad oxide layer 15 and the substrate 10 (SiO2 / Si) and the interface between the isolation oxide material 11 and the substrate 10 (SiO2 / Si), which can reduce interface states and trapped charges; H atoms will also diffuse into the semiconductor structure at the bottom of the interlayer dielectric layer 20 and recombine with the mobile ions inside the semiconductor structure. Furthermore, the silicon-rich oxide layer 22 has a number of Si dangling bonds, and the mobile ions generated in the subsequent process can be captured on the extra Si dangling bonds of the silicon-rich oxide layer 22 through the extra Si dangling bonds of the silicon-rich oxide layer 22, making it difficult for the mobile ions to pass through the silicon-rich oxide layer 22, thereby achieving the purpose of blocking the mobile ions. Furthermore, the silicon oxide layer 23 mainly plays the role of interlayer insulation, effectively isolating the semiconductor structure at the bottom of the interlayer dielectric layer 20 and the subsequently formed patterned metal layer.

[0033] It is worth noting that in the interlayer dielectric layer 20, the stacking order of the first silicon nitride layer 21, the silicon-rich oxide layer 22 and the silicon oxide layer 23 cannot be changed. The interlayer dielectric layer 20 composed of the first silicon nitride layer 21, the silicon-rich oxide layer 22 and the silicon oxide layer 23 stacked in sequence can effectively block the movable charges brought by the Plasma at the packaging end or the back-end process (such as PECVD process, etching process, etc.) from entering the device, and can prevent electrons or impurities from affecting the channel when the device is turned on.

[0034] Next, execute step S3: refer to Figure 4 , Figure 4 1 is a schematic diagram of a semiconductor structure after forming a plurality of conductive plugs according to an embodiment of the present application, wherein the interlayer dielectric layer 20 is etched to the surface of the conductive structure, wherein the area above the ion implantation region 13 is etched to the surface of the ion implantation region 13 by etching the interlayer dielectric layer 20 and the liner oxide layer 15 to form a plurality of through holes. Specifically, the through holes expose a portion of the trench gate 12, a portion of the ion implantation region 13, and a portion of the shielding gate 14 on the surface of the substrate 10.

[0035] In this embodiment, a dry etching process may be used to etch the interlayer dielectric layer 20 to the surface of the conductive structure, and to etch the interlayer dielectric layer 20 and the liner oxide layer 15 to the surface of the ion implantation region 13 to form a plurality of through holes.

[0036] Further, execute step S4: continue to refer to Figure 4 , forming a plurality of conductive plugs, the conductive plugs filling the through hole. In this embodiment, a first conductive plug 31, a second conductive plug 32 and a third conductive plug 33 are formed, and the materials of the first conductive plug 31, the second conductive plug 32 and the third conductive plug 33 can be metal materials such as metal copper and metal tungsten. In this embodiment, the trench gate 12 is led out to the surface of the interlayer dielectric layer 20 through the first conductive plug 31 and the second conductive plug 32; the ion implantation area 13 is led out to the surface of the interlayer dielectric layer 20 through the third conductive plug 33; the present application can also lead the shielding grid 14 to the surface of the interlayer dielectric layer 20 through other conductive plugs (not shown).

[0037] Next, execute step S5: refer to Figure 5 , Figure 5 It is a schematic diagram of the semiconductor structure after a patterned metal layer is formed in an embodiment of the present application, wherein a patterned metal layer 40 is formed, and the patterned metal layer 40 covers the first conductive plug 31, the second conductive plug 32, the third conductive plug 33 and a portion of the interlayer dielectric layer 20 (a portion of the silicon oxide layer 23).

[0038] Finally, execute step S6: reference Figure 6 , Figure 6 Schematic diagram of the semiconductor structure after forming a passivation layer according to an embodiment of the present application, wherein a passivation layer 50 is formed, and the passivation layer 50 covers the patterned metal layer 40 and a portion of the interlayer dielectric layer 20 (a portion of the silicon oxide layer 23 ).

[0039] Preferably, the step of forming the passivation layer 50 includes: A second silicon nitride layer 51 is formed by a PECVD process, wherein the second silicon nitride layer 51 covers the patterned metal layer 40 and a portion of the silicon oxide layer 23; A silicon-rich nitride layer 52 is formed by adopting a PECVD process, and the silicon-rich nitride layer 52 covers the second silicon nitride layer 51 .

[0040] Preferably, the thickness of the second silicon nitride layer 51 is 800Å~2000Å; the thickness of the silicon-rich nitride layer 52 is 8000Å~20000Å.

[0041] In the passivation layer 50, the second silicon nitride layer 51 has good density and can prevent external gas and moisture from invading the device; further, the silicon-rich nitride layer 52 has a plurality of Si dangling bonds, and the silicon-rich nitride layer 52 has a plurality of Si dangling bonds, which can prevent mobile ions generated from the outside from entering the device.

[0042] In a subsequent reliability HTRB (High Temperature Reverse Bias) test, a preset voltage can be applied to the drain of the device (not shown), and a ground voltage can be applied to the trench gate structure (trench gate 12) and the source of the device (not shown) (i.e., the trench gate 12 and the source of the device are grounded), thereby performing a high temperature reverse bias test on the trench gate MOS device.

[0043] Based on the same inventive concept, Figure 6 The present application also provides a semiconductor device, comprising: a semiconductor structure, an interlayer dielectric layer 20, a plurality of through holes, a plurality of conductive plugs, a patterned metal layer and a passivation layer, wherein: A conductive structure is formed in the semiconductor structure; in this embodiment, the semiconductor device may be a trench MOS device, and the conductive structure is a trench gate structure. Specifically, the semiconductor device at least includes: a substrate 10, a plurality of trench gate structures, and an ion implantation region 13 located in the substrate 10 and close to the surface of the substrate 10; Further, the trench gate structure is located in the trench in the substrate 10, and the trench gate structure at least includes: an isolation oxide material 11 and a trench gate 12, and the trench gate 12 serves as a gate of the trench MOS device; it is worth noting that the present application does not impose any restrictions on the specific film layer in the semiconductor structure, and it is only necessary to ensure that a conductive structure that needs to be led out by a conductive plug is formed in the semiconductor structure; The interlayer dielectric layer 20 includes: a first silicon nitride layer 21, a silicon-rich oxide layer 22 and a silicon oxide layer 23, wherein the first silicon nitride layer 21 covers the semiconductor structure and the conductive structure, the silicon-rich oxide layer 22 covers the first silicon nitride layer 21, and the silicon oxide layer 23 covers the silicon-rich oxide layer 22; A plurality of through holes, wherein the through holes are located in the interlayer dielectric layer 20; In this embodiment, the first conductive plug 31, the second conductive plug 32 and the third conductive plug 33 fill the through hole; The patterned metal layer 40 covers the first conductive plug 31 , the second conductive plug 32 , the third conductive plug 33 and a portion of the interlayer dielectric layer 20 ; The passivation layer 50 covers the patterned metal layer 40 and a portion of the interlayer dielectric layer 20 .

[0044] Furthermore, the passivation layer 50 includes: a second silicon nitride layer 51 and a silicon-rich nitride layer 52 , the second silicon nitride layer 51 covers the patterned metal layer and a portion of the interlayer dielectric layer 20 , and the silicon-rich nitride layer 52 covers the second silicon nitride layer 51 .

[0045] Preferably, the thickness of the first silicon nitride layer 21 is 300Å~1000Å; the thickness of the silicon-rich oxide layer 22 is 1000Å~2000Å; and the thickness of the silicon oxide layer 23 is 3000Å~8000Å.

[0046] Preferably, the thickness of the second silicon nitride layer 51 is 800Å~2000Å; the thickness of the silicon-rich nitride layer 52 is 8000Å~20000Å.

[0047] In the present application, a first silicon nitride layer, a silicon-rich oxide layer and a silicon oxide layer stacked in sequence are used as the interlayer dielectric layer of the semiconductor device, and a second silicon nitride layer and a silicon-rich nitride layer stacked in sequence are used as the passivation layer covering the patterned metal layer. This can effectively block the movable charges brought by the plasma generated in the PECVD process, etching process and other processes at the packaging end or the back end, thereby preventing electrons or impurities from affecting the channel when the device is turned on, and significantly improving the reliability of the device.

[0048] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a semiconductor structure, wherein a conductive structure is formed in the semiconductor structure; forming an interlayer dielectric layer, wherein the interlayer dielectric layer comprises: a first silicon nitride layer, a silicon-rich oxide layer and a silicon oxide layer, wherein the first silicon nitride layer covers the semiconductor structure and the conductive structure, the silicon-rich oxide layer covers the first silicon nitride layer, and the silicon oxide layer covers the silicon-rich oxide layer; Etching the interlayer dielectric layer to the surface of the conductive structure to form a plurality of through holes; forming a conductive plug, wherein the conductive plug fills the through hole; forming a patterned metal layer, wherein the patterned metal layer covers the conductive plug and a portion of the interlayer dielectric layer; A passivation layer is formed, wherein the passivation layer covers the patterned metal layer and a portion of the interlayer dielectric layer.

2. The method for preparing a semiconductor device according to claim 1, wherein: The steps of forming the interlayer dielectric layer include: forming the first silicon nitride layer by a furnace tube process, wherein the first silicon nitride layer covers the semiconductor structure and the conductive structure; Forming the silicon-rich oxide layer by a PECVD process, wherein the silicon-rich oxide layer covers the first silicon nitride layer; TEOS gas is introduced into the process chamber and the PECVD process is adopted to form the silicon oxide layer, and the silicon oxide layer covers the silicon-rich oxide layer.

3. The method for preparing a semiconductor device according to claim 1 or 2, characterized in that: The thickness of the first silicon nitride layer is 300Å~1000Å; the thickness of the silicon-rich oxide layer is 1000Å~2000Å; and the thickness of the silicon oxide layer is 3000Å~8000Å.

4. The method for preparing a semiconductor device according to claim 1, wherein: The steps of forming the passivation layer include: forming a second silicon nitride layer by a PECVD process, wherein the second silicon nitride layer covers the patterned metal layer; A silicon-rich nitride layer is formed by adopting a PECVD process, and the silicon-rich nitride layer covers the second silicon nitride layer.

5. The method for preparing a semiconductor device according to claim 4, characterized in that: The thickness of the second silicon nitride layer is 800Å~2000Å; the thickness of the silicon-rich nitride layer is 8000Å~20000Å.

6. The method for preparing a semiconductor device according to claim 1, wherein: The semiconductor device is a trench MOS device, and the conductive structure is a trench gate structure.

7. A semiconductor device, characterized in that: include: A semiconductor structure having a conductive structure formed therein; An interlayer dielectric layer, wherein the interlayer dielectric layer comprises: a first silicon nitride layer, a silicon-rich oxide layer and a silicon oxide layer, the first silicon nitride layer covers the semiconductor structure and the conductive structure, the silicon-rich oxide layer covers the first silicon nitride layer, and the silicon oxide layer covers the silicon-rich oxide layer; A plurality of through holes, wherein the through holes are located in the interlayer dielectric layer; a conductive plug filling the through hole; A patterned metal layer, wherein the patterned metal layer covers the conductive plug and a portion of the interlayer dielectric layer; A passivation layer covers the patterned metal layer and a portion of the interlayer dielectric layer.

8. The semiconductor device according to claim 7, characterized in that The thickness of the first silicon nitride layer is 300Å~1000Å; the thickness of the silicon-rich oxide layer is 1000Å~2000Å; and the thickness of the silicon oxide layer is 3000Å~8000Å.

9. The semiconductor device according to claim 7, characterized in that The passivation layer includes: a second silicon nitride layer and a silicon-rich nitride layer, the second silicon nitride layer covers the patterned metal layer, and the silicon-rich nitride layer covers the second silicon nitride layer.

10. The semiconductor device according to claim 9, characterized in that The thickness of the second silicon nitride layer is 800Å~2000Å; the thickness of the silicon-rich nitride layer is 8000Å~20000Å.

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