Semiconductor Structure and Semiconductor Device

Abstract

The present application provides a semiconductor structure and a semiconductor device. The semiconductor structure includes: a substrate; an epitaxial layer located on the surface of the substrate; a floating doping region located in the epitaxial layer, the surface of the floating doping region not in contact with the surface of the epitaxial layer, the doping type of the floating doping region being the same as that of the epitaxial layer, and the doping concentration of the floating doping region being greater than that of the epitaxial layer; at least one first doping region located in the epitaxial layer and on the side of the floating doping region away from the substrate, the surface of the first doping region away from the substrate being a partial surface of the epitaxial layer away from the substrate, the surface of the first doping region close to the substrate not in contact with the surface of the floating doping region away from the substrate, and the doping type of the first doping region being different from that of the floating doping region. The present application solves the problem in the prior art that in a silicon carbide MOSFET device, current concentration and heat concentration in a cell during a surge current occur, resulting in easy damage to the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a semiconductor device. Background Art

[0002] A silicon carbide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device has a natural parasitic body diode. When a surge current is formed in a circuit, the body diode is often turned on to carry the surge current. However, the surge current is concentrated at the position of the body diode, and at the same time, the heat concentration is also at the position of the body diode, resulting in problems of current concentration and heat concentration, causing irreversible damage to the device. Summary of the Invention

[0003] The main object of this application is to provide a semiconductor structure and a semiconductor device to solve the problem in the prior art that the current concentration and heat concentration in the cells of a silicon carbide MOSFET device during the occurrence of a surge current easily cause damage to the device.

[0004] To achieve the above object, according to one aspect of this application, a semiconductor structure is provided, including: a substrate; an epitaxial layer located on the surface of the substrate; a floating doping region located in the epitaxial layer, the surface of the floating doping region not being in contact with the surface of the epitaxial layer, the doping type of the floating doping region being the same as that of the epitaxial layer, and the doping concentration of the floating doping region being greater than that of the epitaxial layer; at least one first doping region located in the epitaxial layer and on the side of the floating doping region away from the substrate, the surface of the first doping region away from the substrate being a part of the surface of the epitaxial layer away from the substrate, the surface of the first doping region close to the substrate not being in contact with the surface of the floating doping region away from the substrate, and the doping type of the first doping region being different from that of the floating doping region; and a gate structure located on a part of the surface of the epitaxial layer away from the substrate.

[0005] Optionally, there are multiple first doping regions, and the semiconductor structure further includes: a plurality of second doping regions arranged at intervals, the second doping regions being located in the first doping regions one by one, the surface of the second doping region away from the substrate being a part of the surface of the first doping region away from the substrate, and the doping type of the second doping region being the same as that of the first doping region.

[0006] Optionally, the semiconductor structure further includes: a plurality of third doping regions disposed at intervals, each of the third doping regions being located in the first doping region, the third doping region being on a side of the second doping region close to the gate structure, a surface of the third doping region away from the substrate being a partial surface of the first doping region away from the substrate, sidewalls of the third doping region being in contact with sidewalls of the second doping region, and a doping type of the third doping region being different from a doping type of the first doping region.

[0007] Optionally, the first doping region includes a first sub-doping region and a second sub-doping region. The first sub-doping region is on a surface of the second doping region, the third doping region, and the second sub-doping region close to the substrate. The second sub-doping region is on a sidewall of the third doping region away from the second doping region. The first sub-doping region has a graded doping, and the closer to the substrate, the smaller the doping concentration of the first sub-doping region.

[0008] Optionally, a maximum doping concentration of the first sub-doping region is a first doping concentration, a minimum doping concentration of the first sub-doping region is a second doping concentration, and a doping concentration of the second sub-doping region is greater than the second doping concentration and less than the first doping concentration.

[0009] Optionally, the semiconductor structure further includes: a first electrode on a surface of the second doping region away from the substrate, a partial surface of the third doping region away from the substrate, and a surface of the gate structure away from the substrate; and a second electrode on a surface of the substrate away from the epitaxial layer.

[0010] Optionally, a doping concentration of the second doping region is greater than a doping concentration of the first doping region, and a doping concentration of the third doping region is greater than a doping concentration of the epitaxial layer.

[0011] Optionally, in a first direction parallel to a thickness direction of the substrate, a distance between a surface of the floating doping region away from the substrate and a surface of the first doping region close to the substrate is less than a distance between a surface of the floating doping region close to the substrate and a surface of the epitaxial layer close to the substrate.

[0012] Optionally, the gate structure includes: a gate dielectric layer on a partial surface of the epitaxial layer away from the substrate; and a gate in the gate dielectric layer, with the gate dielectric layer surrounding the gate.

[0013] Optionally, the floating doping region includes a plurality of floating sub-doping regions spaced apart in a second direction perpendicular to the thickness direction of the substrate.

[0014] Optionally, there are two of the first doping regions, and the semiconductor structure further includes: a fourth doping region located between the two first doping regions and in contact with sidewalls of both of the first doping regions. A surface of the fourth doping region close to the substrate is not in contact with a surface of the floating doping region away from the substrate. The doping type of the fourth doping region is the same as that of the epitaxial layer. The doping concentration of the fourth doping region is greater than that of the epitaxial layer and less than that of the floating doping region.

[0015] According to another aspect of the present application, there is provided a semiconductor device including any one of the semiconductor structures described above.

[0016] Applying the technical solution of the present application, the semiconductor structure includes a substrate, an epitaxial layer on the surface of the substrate, a floating doping region in the epitaxial layer, a first doping region, and a gate structure. Among them, a surface of the floating doping region is not in contact with a surface of the epitaxial layer. The doping type of the floating doping region is the same as that of the epitaxial layer. The doping concentration of the floating doping region is greater than that of the epitaxial layer. The first doping region is located on a side of the floating doping region away from the substrate. A surface of the first doping region close to the substrate is not in contact with a surface of the floating doping region away from the substrate. The doping type of the first doping region is different from that of the floating doping region. The gate structure is located on a partial surface of the epitaxial layer away from the substrate. Compared with the problem in the prior art that in a silicon carbide MOSFET device, current concentration and heat concentration in a cell during a surge current cause the device to be easily damaged, in the present application, a floating doping region having the same doping type as the epitaxial layer is added in the epitaxial layer to form a lateral low-resistance layer, such that the surge current flows through the floating doping region, that is, the surge current near the body diode is dispersed through the floating doping region, ensuring less current concentration and heat concentration in the cell, thereby ensuring less damage to the device and better performance of the device. Description of the Drawings

[0017] The specification drawings forming a part of the present application are used to provide a further understanding of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0018] Figure 1 A schematic cross-sectional view of a semiconductor structure provided according to an embodiment of the present application is shown;

[0019] Figure 2 A schematic cross-sectional view of another semiconductor structure provided according to an embodiment of the present application is shown;

[0020] Figure 3 A schematic cross-sectional view of still another semiconductor structure provided according to an embodiment of the present application is shown;

[0021] Figure 4 The structural cross-sectional schematic diagram of yet another semiconductor structure provided according to an embodiment of the present application is shown;

[0022] Figure 5 The structural cross-sectional schematic diagram of yet another semiconductor structure provided according to an embodiment of the present application is shown.

[0023] Among them, the above-mentioned drawings include the following reference numerals:

[0024] 10. Substrate; 11. Epitaxial layer; 12. Floating doping region; 13. First doping region; 14. Gate structure; 15. Second doping region; 16. Third doping region; 17. First electrode; 18. Second electrode; 141. Gate dielectric layer; 142. Gate; 121. Floating sub-doping region; 19. Fourth doping region; 131. First sub-doping region; 132. Second sub-doping region. Detailed implementation manners

[0025] It should be noted that the following detailed description is exemplary and is intended to provide further illustration of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs.

[0026] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary implementation manners according to the present application. As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0027] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element can be directly on the other element, or there can also be an intermediate element. Moreover, in the specification and claims, when an element is described as being "connected" to another element, the element can be "directly connected" to the other element, or "connected" to the other element through a third element.

[0028] As introduced in the background art, in the prior art, current concentration and heat concentration in the cells of a silicon carbide MOSFET device during a surge current occurrence cause the device to be easily damaged. To solve the above problems, embodiments of the present application provide a semiconductor structure and a semiconductor device.

[0029] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention.

[0030] In this embodiment, a semiconductor structure is provided, as Figures 1 to 5 shown, including:

[0031] A substrate 10;

[0032] An epitaxial layer 11, located on the surface of the above-mentioned substrate 10;

[0033] A floating doped region 12, located in the above-mentioned epitaxial layer 11, the surface of the floating doped region 12 is not in contact with the surface of the epitaxial layer 11, the doping type of the floating doped region 12 is the same as the doping type of the epitaxial layer 11, and the doping concentration of the floating doped region 12 is greater than the doping concentration of the epitaxial layer 11;

[0034] At least one first doped region 13, located in the above-mentioned epitaxial layer 11 and on the side of the floating doped region 12 away from the substrate 10, the surface of the first doped region 13 away from the substrate 10 is a part of the surface of the epitaxial layer 11 away from the substrate 10, the surface of the first doped region 13 close to the substrate 10 is not in contact with the surface of the floating doped region 12 away from the substrate 10, and the doping type of the first doped region 13 is different from the doping type of the floating doped region 12;

[0035] A gate structure 14, located on a part of the surface of the above-mentioned epitaxial layer 11 away from the substrate 10.

[0036] Through the above embodiment, the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a floating doped region located in the epitaxial layer, a first doped region, and a gate structure. Among them, the surface of the floating doped region is not in contact with the surface of the epitaxial layer, the doping type of the floating doped region is the same as the doping type of the epitaxial layer, the doping concentration of the floating doped region is greater than the doping concentration of the epitaxial layer, the first doped region is located on the side of the floating doped region away from the substrate, the surface of the first doped region close to the substrate is not in contact with the surface of the floating doped region away from the substrate, the doping type of the first doped region is different from the doping type of the floating doped region, and the gate structure is located on a part of the surface of the epitaxial layer away from the substrate. Compared with the problem that in the prior art, the current concentration and heat concentration in the cell of the silicon carbide MOSFET device during the occurrence of surge current easily cause device damage, in this application, a floating doped region with the same doping type as the epitaxial layer is added in the epitaxial layer to form a lateral low-resistance layer, so that the surge current flows through the floating doped region, that is, the surge current near the body diode is dispersed through the floating doped region, ensuring less current concentration and heat concentration in the cell, thereby ensuring less device damage and better device performance.

[0037] Specifically, the floating doped region is used to reduce the heat concentration inside the device, and can also correspondingly reduce the highest temperature inside the device.

[0038] Specifically, the material of the substrate includes silicon carbide, diamond, etc. The doping concentration of the substrate is heavily doped. The substrate has a supporting function and has the characteristics of low on-resistance and low contact resistance. The doping type of the substrate can be N-type or P-type, and the present application does not make specific restrictions on this. In the embodiments of the present application, the doping type of the substrate is N-type.

[0039] Specifically, the thickness, doping type, and doping concentration of the epitaxial layer can be determined according to device design requirements. In the embodiments of the present application, the doping type of the epitaxial layer is N-type.

[0040] Specifically, the doping particles of the first doping region include but are not limited to Al, B, etc., and the doping concentration includes but is not limited to 1E18 cm -3 -1E21 cm -3 , and the doping type is P-type. The doping particles of the floating doping region include but are not limited to N, P, etc., and the doping concentration is 1E18 cm -3 -1E21 cm -3 , and the doping type is N-type. The floating doping region forms a lateral low-resistance channel to help the surge current at the position of the body diode disperse within the cell to reduce current concentration and heat concentration.

[0041] Specifically, as Figure 1 and Figure 5 shown, the side wall of the floating doping region 12 can be in contact with the side wall of the epitaxial layer 11. As Figures 2 to 4 shown, the side wall of the floating doping region 12 may not be in contact with the side wall of the epitaxial layer 11, and the present application does not make specific restrictions on this. The shape of the floating doping region 12 can be a rectangle as Figure 1 and Figure 2 shown, or can be a shape as Figure 3 shown, or can be other shapes, and the present application does not make specific restrictions on this.

[0042] In an exemplary embodiment, as Figures 1 to 5 shown, there are multiple of the above-mentioned first doping regions 13, and the semiconductor structure further includes: a plurality of second doping regions 15 arranged at intervals. The second doping regions 15 are located in the first doping regions 13 one by one. The surface of the second doping region 15 away from the substrate 10 is a part of the surface of the first doping region 13 away from the substrate 10, and the doping type of the second doping region 15 is the same as the doping type of the first doping region 13. In this embodiment, the second doping region is located in the first doping region, and the doping type of the second doping region is the same as the doping type of the first doping region. By setting the second doping region, it is ensured that the device has a large number of carriers and good current driving ability.

[0043] Specifically, the doping particles in the second doping region include, but are not limited to, Al, B, etc., and the doping concentration includes, but is not limited to, 1E18 cm -3 -1E21 cm -3 , and the doping type is P-type.

[0044] In other embodiments, as Figures 1 to 5 shown, the above semiconductor structure further includes: a plurality of third doping regions 16 arranged at intervals, the third doping regions 16 are located in the first doping region 13 one by one, the third doping regions 16 are located on the side of the second doping region 15 close to the gate structure 14, the surface of the third doping region 16 far from the substrate 10 is a part of the surface of the first doping region 13 far from the substrate 10, the side walls of the third doping region 16 are in contact with the side walls of the second doping region 15, and the doping type of the third doping region is different from that of the first doping region 13. In this embodiment, the third doping region is located in the first doping region, and the doping type of the third doping region is different from that of the first doping region. The third doping region serves as the source region or drain region of the device, providing a path for electron injection and collection, and further ensuring that the device has a relatively high electron mobility.

[0045] Specifically, the doping particles in the third doping region include, but are not limited to, N, P, etc., and the doping concentration includes, but is not limited to, 1E18 cm -3 -1E21 cm -3 , and the doping type is N-type.

[0046] In other embodiments, as Figure 5 shown, the first doping region 13 includes a first sub-doping region 131 and a second sub-doping region 132. The first sub-doping region 131 is located on the surface of the second doping region 15, the third doping region 16, and the second sub-doping region 132 close to the substrate 10. The second sub-doping region 132 is located on the side wall of the third doping region 16 far from the second doping region 15. The first sub-doping region 131 is a graded doping, and the closer to the substrate 10, the smaller the doping concentration of the first sub-doping region 131. In this embodiment, by designing the graded doping of the first sub-doping region, the PN junction barrier height between the first sub-doping region and the N-drift is reduced, thereby reducing the body diode turn-on voltage and further enhancing the device's surge resistance.

[0047] In yet another embodiment, the maximum doping concentration of the first sub-doping region is the first doping concentration, the minimum doping concentration of the first sub-doping region is the second doping concentration, the doping concentration of the second sub-doping region is greater than the second doping concentration and less than the first doping concentration.

[0048] Specifically, the first doping concentration is 1E18 cm -3, the above-mentioned second doping concentration is 1E16 cm -3 .

[0049] In some other exemplary embodiments, such as Figures 1 to 5 shown, the above-mentioned semiconductor structure further includes: a first electrode 17, located on the surface of the above-mentioned second doping region 15 away from the above-mentioned substrate 10, a partial surface of the above-mentioned third doping region 16 away from the above-mentioned substrate 10, and the surface of the above-mentioned gate structure 14 away from the above-mentioned substrate 10; a second electrode 18, located on the surface of the above-mentioned substrate 10 away from the above-mentioned epitaxial layer 11. In this embodiment, the first electrode and the second electrode serve as the source and drain of the device, used to control the inflow and outflow of current, control the on-off state of the device, and further ensure better performance of the device.

[0050] Specifically, the material of the first electrode includes but is not limited to Ti, Al, Ni, Au, etc., and the material of the second electrode includes but is not limited to Ti, Al, Ni, Au, etc.

[0051] In some alternative solutions, the doping concentration of the above-mentioned second doping region is greater than that of the above-mentioned first doping region, and the doping concentration of the above-mentioned third doping region is greater than that of the above-mentioned epitaxial layer. In this embodiment, the doping concentration of the second doping region is greater than that of the first doping region, and the doping concentration of the third doping region is greater than that of the epitaxial layer, which further ensures a higher carrier concentration in the device, thereby further ensuring a higher conductivity of the device, and further ensuring better performance of the device.

[0052] In still some other alternative solutions, such as Figures 1 to 5 shown, in the first direction, the distance between the surface of the above-mentioned floating doping region 12 away from the above-mentioned substrate 10 and the surface of the above-mentioned first doping region 13 close to the above-mentioned substrate 10 is less than the distance between the surface of the above-mentioned floating doping region 12 close to the above-mentioned substrate 10 and the surface of the above-mentioned epitaxial layer 11 close to the above-mentioned substrate 10, and the first direction is parallel to the thickness direction of the above-mentioned substrate 10. In this embodiment, the floating doping region is located near the body diode PN junction, which further ensures a better dispersion effect of the surge current near the body diode, further ensures less current concentration and heat concentration inside the device cell, and further ensures better performance of the device.

[0053] In still some other alternative solutions, such as Figures 1 to 5As shown, the above-mentioned gate structure 14 includes: a gate dielectric layer 141 located on a partial surface of the above-mentioned epitaxial layer 11 away from the above-mentioned substrate 10; a gate 142 located in the above-mentioned gate dielectric layer 141, and the above-mentioned gate dielectric layer 141 is located around the above-mentioned gate 142. In this embodiment, the gate structure includes a gate dielectric layer and a gate. The gate is located in the gate dielectric layer, and the gate dielectric layer provides an electrically insulating layer to isolate the gate from the epitaxial layer, preventing current from directly flowing from the gate to the epitaxial layer, thereby controlling the conductivity of the device and further ensuring better device performance.

[0054] Specifically, the surface of the gate does not contact the outer surface of the gate dielectric layer, the side wall of the gate does not contact the outer wall of the gate dielectric layer, the surface of the gate contacts the inner surface of the gate dielectric layer, the side wall of the gate contacts the inner wall of the gate dielectric layer, and the gate dielectric layer surrounds the gate.

[0055] Specifically, the material of the gate includes polysilicon, silicon carbide, etc. The gate has the characteristics of high temperature resistance and low resistance. The dopants include but are not limited to P, N, B, etc., and the doping concentration includes but is not limited to 1E18 cm -3 -1E20 cm -3 . The gate dielectric layer is also called the gate oxide layer. The material of the gate dielectric layer includes but is not limited to silicon oxide (SiO2), hafnium oxide (HfO2), aluminum oxide (Al2O3), aluminum nitride (AlN), etc. The thickness of the gate dielectric layer is 10 nm - 1000 nm.

[0056] In an exemplary embodiment, as Figure 4 shown, the floating doping region 12 includes a plurality of floating sub-doping regions 121 arranged at intervals in the second direction, and the above-mentioned second direction is perpendicular to the thickness direction of the above-mentioned substrate 10. In this embodiment, the floating doping region includes a plurality of floating sub-doping regions arranged at intervals in the second direction, further ensuring better dispersion of the surge current near the body diode in the device, thereby further ensuring better device performance.

[0057] In an exemplary embodiment, as Figures 1 to 5As shown, there are two of the above-mentioned first doping regions 13, and the semiconductor structure further includes: a fourth doping region 19, which is located between the two first doping regions 13 and is in contact with the sidewalls of both of the two first doping regions 13. The surface of the fourth doping region 19 close to the substrate 10 is not in contact with the surface of the floating doping region 12 far from the substrate 10. The doping type of the fourth doping region 19 is the same as that of the epitaxial layer 11, the doping concentration of the fourth doping region 19 is greater than the doping concentration of the epitaxial layer 11, and the doping concentration of the fourth doping region 19 is less than the doping concentration of the floating doping region 12. In this embodiment, the fourth doping region is located between the two first doping regions, and the doping type of the fourth doping region is the same as that of the epitaxial layer. By setting the fourth doping region, the on-resistance of the device is further ensured to be small, the current control of the device is further ensured to be good, and the performance of the device is further ensured to be good.

[0058] Specifically, the semiconductor structure further includes a channel region (CH region). The doping particles in the channel region include, but are not limited to, Al and B, and the doping concentration includes, but is not limited to, 1E17 cm -3 -1E21 cm -3 .

[0059] Specifically, the first doping region is a P-well region, the second doping region is a P+ region, the third doping region is an N+ region, and the fourth doping region is a JFET region.

[0060] The embodiment of the present application further provides a semiconductor device, including: any one of the above-mentioned semiconductor structures.

[0061] In the above embodiment, the semiconductor device includes a semiconductor structure. Among them, the semiconductor structure includes a substrate, an epitaxial layer on the surface of the substrate, a floating doping region in the epitaxial layer, a first doping region, and a gate structure. Among them, the surface of the floating doping region is not in contact with the surface of the epitaxial layer. The doping type of the floating doping region is the same as that of the epitaxial layer, and the doping concentration of the floating doping region is greater than the doping concentration of the epitaxial layer. The first doping region is located on the side of the floating doping region far from the substrate, and the surface of the first doping region close to the substrate is not in contact with the surface of the floating doping region far from the substrate. The doping type of the first doping region is different from that of the floating doping region, and the gate structure is located on a part of the surface of the epitaxial layer far from the substrate. Compared with the problem in the prior art that the current concentration and heat concentration in the cell of the silicon carbide MOSFET device during the occurrence of surge current easily cause damage to the device, in the present application, a floating doping region with the same doping type as the epitaxial layer is added in the epitaxial layer to form a lateral low-resistance layer, so that the surge current flows through the floating doping region, that is, the surge current near the body diode is dispersed through the floating doping region, ensuring less current concentration and heat concentration in the cell, thereby ensuring less damage to the device and ensuring better performance of the device.

[0062] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0063] 1) In the semiconductor structure of the present application, the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a floating doping region located in the epitaxial layer, a first doping region, and a gate structure. Among them, the surface of the floating doping region does not contact the surface of the epitaxial layer, the doping type of the floating doping region is the same as that of the epitaxial layer, the doping concentration of the floating doping region is greater than that of the epitaxial layer, the first doping region is located on the side of the floating doping region away from the substrate, the surface of the first doping region close to the substrate does not contact the surface of the floating doping region away from the substrate, the doping type of the first doping region is different from that of the floating doping region, and the gate structure is located on a partial surface of the epitaxial layer away from the substrate. Compared with the problem in the prior art that the current concentration and heat concentration in the cell of the silicon carbide MOSFET device during the occurrence of surge current easily cause device damage, the present application adds a floating doping region with the same doping type as the epitaxial layer in the epitaxial layer to form a lateral low-resistance layer, so that the surge current flows through the floating doping region, that is, the surge current near the body diode is dispersed through the floating doping region, ensuring less current concentration and heat concentration in the cell, thereby ensuring less device damage and better device performance.

[0064] 2) In the semiconductor device of the present application, the semiconductor device includes a semiconductor structure. Among them, the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a floating doping region located in the epitaxial layer, a first doping region, and a gate structure. Among them, the surface of the floating doping region does not contact the surface of the epitaxial layer, the doping type of the floating doping region is the same as that of the epitaxial layer, the doping concentration of the floating doping region is greater than that of the epitaxial layer, the first doping region is located on the side of the floating doping region away from the substrate, the surface of the first doping region close to the substrate does not contact the surface of the floating doping region away from the substrate, the doping type of the first doping region is different from that of the floating doping region, and the gate structure is located on a partial surface of the epitaxial layer away from the substrate. Compared with the problem in the prior art that the current concentration and heat concentration in the cell of the silicon carbide MOSFET device during the occurrence of surge current easily cause device damage, the present application adds a floating doping region with the same doping type as the epitaxial layer in the epitaxial layer to form a lateral low-resistance layer, so that the surge current flows through the floating doping region, that is, the surge current near the body diode is dispersed through the floating doping region, ensuring less current concentration and heat concentration in the cell, thereby ensuring less device damage and better device performance.

[0065] The above are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; An epitaxial layer located on the surface of the substrate; A floating doped region located in the epitaxial layer, the surface of the floating doped region not in contact with the surface of the epitaxial layer, the doping type of the floating doped region being the same as that of the epitaxial layer, the doping concentration of the floating doped region being greater than that of the epitaxial layer, the floating doped region including a first portion, a second portion, and a third portion sequentially connected in a second direction, the extending directions of the side walls of the first portion and the third portion respectively intersecting with the thickness direction of the substrate, and the second direction being perpendicular to the thickness direction of the substrate; At least one first doped region located in the epitaxial layer and on the side of the floating doped region away from the substrate, the surface of the first doped region away from the substrate being a partial surface of the epitaxial layer away from the substrate, the surface of the first doped region close to the substrate not in contact with the surface of the floating doped region away from the substrate, and the doping type of the first doped region being different from that of the floating doped region; A gate structure located on a partial surface of the epitaxial layer away from the substrate; The first doped region includes a stacked first sub-doped region and a second sub-doped region, the first sub-doped region being at least on the surface of the second sub-doped region close to the substrate, and the first sub-doped region being a graded doping, and the doping concentration of the first sub-doped region becoming smaller as it gets closer to the substrate.

2. The semiconductor structure according to claim 1, wherein There are multiple first doped regions, and the semiconductor structure further includes: Multiple second doped regions arranged at intervals, the second doped regions being located in the first doped regions one by one, the surface of the second doped region away from the substrate being a partial surface of the first doped region away from the substrate, and the doping type of the second doped region being the same as that of the first doped region.

3. The semiconductor structure according to claim 2, wherein The semiconductor structure further includes: Multiple third doped regions arranged at intervals, the third doped regions being located in the first doped regions one by one, the third doped regions being on the side of the second doped regions close to the gate structure, the surface of the third doped region away from the substrate being a partial surface of the first doped region away from the substrate, the side walls of the third doped regions in contact with the side walls of the second doped regions, and the doping type of the third doped region being different from that of the first doped region.

4. The semiconductor structure according to claim 3, wherein, The first sub-doped region is on the surfaces of the second doped region, the third doped region, and the second sub-doped region close to the substrate, and the second sub-doped region is on the side wall of the third doped region away from the second doped region.

5. The semiconductor structure according to claim 4, wherein The maximum doping concentration of the first sub-doped region is a first doping concentration, the minimum doping concentration of the first sub-doped region is a second doping concentration, the doping concentration of the second sub-doped region is greater than the second doping concentration and less than the first doping concentration.

6. The semiconductor structure according to claim 3, wherein The semiconductor structure further includes: A first electrode located on the surface of the second doped region away from the substrate, a partial surface of the third doped region away from the substrate, and the surface of the gate structure away from the substrate; A second electrode, located on a surface of the substrate away from the epitaxial layer.

7. The semiconductor structure according to claim 3, wherein A doping concentration of the second doped region is greater than a doping concentration of the first doped region, and a doping concentration of the third doped region is greater than a doping concentration of the epitaxial layer.

8. The semiconductor structure according to claim 1, characterized in that, In a first direction parallel to a thickness direction of the substrate, a distance between a surface of the floating doped region away from the substrate and a surface of the first doped region close to the substrate is less than a distance between a surface of the floating doped region close to the substrate and a surface of the epitaxial layer close to the substrate.

9. The semiconductor structure according to claim 1, wherein The gate structure includes: A gate dielectric layer, located on a partial surface of the epitaxial layer away from the substrate; A gate, located in the gate dielectric layer, and the gate dielectric layer is located around the gate.

10. The semiconductor structure according to claim 1, characterized in that, The floating doped region includes a plurality of floating sub-doped regions spaced apart along a second direction perpendicular to the thickness direction of the substrate.

11. The semiconductor structure according to claim 2, wherein There are two first doped regions, and the semiconductor structure further includes: A fourth doped region, located between the two first doped regions and in contact with sidewalls of the two first doped regions. A surface of the fourth doped region close to the substrate is not in contact with a surface of the floating doped region away from the substrate. A doping type of the fourth doped region is the same as a doping type of the epitaxial layer. A doping concentration of the fourth doped region is greater than a doping concentration of the epitaxial layer and less than a doping concentration of the floating doped region.

12. A semiconductor device, characterized in that, Comprising: The semiconductor structure according to any one of claims 1 to 11.

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