Gallium oxide power device and preparation method thereof

Abstract

The invention provides a gallium oxide power device and a preparation method thereof, and the preparation method achieves the heterogeneous integration of gallium oxide and a device substrate after the bonding processing and annealing processing of a gallium oxide substrate and the device substrate, thereby improving the heat dissipation capability of the gallium oxide power device, and improving the reliability of the gallium oxide power device. The gallium oxide heterostructure is subjected to slotting treatment, part of the surface of the device substrate is exposed, a channel structure is formed, switching of the device can be controlled, a natural enhanced power device can be achieved, and the safety of the gallium oxide device in a module and a circuit is improved; and then field plate structures are prepared on the channel structure and the gallium oxide substrate, so that the breakdown voltage of the device can be improved, the current collapse can be inhibited, the performance during the period can be improved, and the electric field distribution can be optimized, and therefore, the enhanced gallium oxide power device with high thermal conductivity can be obtained based on heterogeneous integration.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a gallium oxide power device and a method for preparing the same. Background Art

[0002] Gallium oxide (Ga 2 O 3 ) As an ultra-wide bandgap semiconductor material, due to its extremely large bandgap width, its maximum critical breakdown field strength reaches 8MV / cm. At the same time, gallium oxide is easy to be n-type doped and easy to prepare good ohmic contacts. Therefore, the power devices prepared based on it not only have high breakdown voltage, but also have low conduction losses, thus greatly improving the power conversion efficiency of the device. The power factor of merit (PFOM) of gallium oxide is 4 times that of gallium nitride (GaN), which is also a wide bandgap semiconductor material, and 10 times that of silicon carbide (SiC). In the future, gallium oxide materials will have very broad application prospects in power devices.

[0003] However, gallium oxide has two key bottlenecks. First, it is difficult to achieve P-type doping in gallium oxide due to the hole self-trapping effect, so gallium oxide power devices are normally-on devices, which results in low device reliability and greatly increased power loss. In addition, due to the extremely low thermal conductivity of gallium oxide, gallium oxide power devices have a very serious self-heating effect, which reduces the power characteristics of gallium oxide devices. Therefore, how to improve the power characteristics and thermal conductivity of gallium oxide devices has become an urgent problem to be solved. Summary of the invention

[0004] In order to solve the above technical problems, the present application proposes a gallium oxide power device and a preparation method thereof.

[0005] On the one hand, an embodiment of the present application provides a method for preparing a gallium oxide power device, the method comprising:

[0006] Providing a gallium oxide substrate and a device substrate;

[0007] Bonding the gallium oxide substrate and the device substrate along the upper surface of the device substrate, and performing annealing treatment to obtain a gallium oxide heterostructure; the gallium oxide heterostructure includes the gallium oxide substrate and the device substrate in order from top to bottom;

[0008] Performing a groove process on the gallium oxide heterostructure to expose a portion of the surface of the device substrate to form a channel structure; the opening direction of the channel structure is located on the gallium oxide substrate;

[0009] Performing drain-source implantation on the gallium oxide substrate to form a source region and a drain region in the gallium oxide substrate;

[0010] Performing gate oxide deposition on the channel structure to obtain a gate oxide layer located on the surface of the channel structure;

[0011] A field plate structure is prepared on the upper surface of the gallium oxide substrate and close to the channel structure to obtain the gallium oxide power device.

[0012] Furthermore, the field plate structure includes a silicon layer and a metal layer; the field plate structure is prepared on the upper surface of the gallium oxide substrate and close to the channel structure to obtain the gallium oxide power device, including:

[0013] Depositing a silicon layer on the upper surface of the gallium oxide substrate and close to the channel structure to obtain the silicon layer on the gallium oxide substrate; the material of the silicon layer includes at least one of silicon oxide and silicon nitride;

[0014] Metal deposition is performed on a partial area of ​​the silicon layer, and metal deposition is performed on the channel structure to prepare the metal layer and obtain the gallium oxide power device; the material of the metal layer includes one of titanium and gold; the sum of the thickness of the metal layer and the silicon layer is 80nm-100nm.

[0015] Further, after providing the gallium oxide substrate and the device substrate, the method further comprises:

[0016] Ion implantation is performed on the gallium oxide substrate to form a defect layer in the gallium oxide substrate; the type of the ion implantation is at least one of hydrogen ions and helium ions; the implantation dose of the ion implantation is 1E16ions / cm2-1E19ions / cm2; the energy of the ion implantation is 20KeV-300KeV.

[0017] Furthermore, the gallium oxide substrate and the device substrate are bonded along the upper surface of the device substrate, and annealed to obtain a gallium oxide heterostructure, including:

[0018] The gallium oxide substrate and the device substrate are bonded along the upper surface of the device substrate to obtain a first bonding structure; the bonding method is hydrophilic bonding or surface activated bonding;

[0019] The first bonding structure is subjected to high temperature annealing treatment so as to peel off the first bonding structure along the defect layer to obtain the gallium oxide heterostructure.

[0020] Furthermore, after performing drain-source implantation on the gallium oxide substrate to form a source region and a drain region in the gallium oxide substrate, the method further comprises:

[0021] The gallium oxide heterostructure is annealed at a temperature of 900° C. to 1200° C. and for a time of 2 min to 60 min.

[0022] Furthermore, the device substrate is one of a P-type diamond and a silicon carbide heterostructure;

[0023] The silicon carbide heterostructure includes P-type silicon carbide and N-type silicon carbide from top to bottom.

[0024] Furthermore, the gallium oxide substrate is unintentionally doped gallium oxide;

[0025] The thickness of the gallium oxide substrate is 500 μm-680 μm;

[0026] The crystalline phase of the gallium oxide substrate is one of (010), (100), (001), and (201).

[0027] Furthermore, in the P-type silicon carbide, the concentration of the P-type dopant is 1E17ions / cm 2 -1E18ions / cm 2 ; The thickness of the P-type silicon carbide is 200nm-1000nm;

[0028] In the N-type silicon carbide, the concentration of the N-type dopant is 1E17ions / cm 2 -1E19ions / cm 2 ; The thickness of the N-type silicon carbide is 350μm-600μm.

[0029] Further, the sum of the thickness of the gallium oxide substrate and the P-type silicon carbide is a first thickness;

[0030] The depth of the channel structure is greater than the thickness of the gallium oxide substrate and less than the first thickness.

[0031] Furthermore, the implanted ions for the drain-source implantation are silicon ions, and the implantation energy is 10-50kev;

[0032] The gate oxide layer is made of at least one of silicon oxide, aluminum oxide and hafnium oxide, and has a thickness of 5nm-50nm.

[0033] On the other hand, an embodiment of the present application further provides a gallium oxide power device, which is prepared by the above-mentioned method for preparing a gallium oxide power device.

[0034] The present application provides a gallium oxide power device and a preparation method thereof. The preparation method realizes heterogeneous integration of gallium oxide and silicon carbide heterostructures after bonding and annealing a gallium oxide substrate and a silicon carbide heterostructure, thereby improving the heat dissipation capacity of the gallium oxide power device. Then, the gallium oxide heterostructure is grooved to expose a portion of the surface of the device substrate to form a channel structure, which can control the switching of the device and realize a natural enhanced power device, thereby improving the safety of the gallium oxide device in modules and circuits. Then, a field plate structure is prepared on the channel structure and the gallium oxide substrate, which can improve the breakdown voltage of the device, suppress current collapse, improve period performance, and optimize electric field distribution, thereby obtaining an enhanced, high-thermal-conductivity gallium oxide power device based on heterogeneous integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions and advantages in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 It is a schematic flow chart of a method for preparing a gallium oxide power device provided in an embodiment of the present application;

[0037] Figure a in Figure 2 is a schematic structural diagram of a device substrate provided in an embodiment of the present application;

[0038] Figure b in Figure 2 is a schematic structural diagram of another device substrate provided in an embodiment of the present application;

[0039] Figure 3 It is a structural schematic diagram of a bonding and annealing process of a gallium oxide substrate and a silicon carbide heterostructure provided in an embodiment of the present application;

[0040] Figure 4 is a structural schematic diagram of a preparation process of a channel structure provided in an embodiment of the present application;

[0041] Figure 5 It is a structural schematic diagram of a drain-source injection processing process provided by an embodiment of the present application;

[0042] Figure 6 It is a structural schematic diagram of a process for preparing a gate oxide layer provided in an embodiment of the present application;

[0043] Figure 7 is a structural schematic diagram of a preparation process of a field plate structure provided in an embodiment of the present application;

[0044] Figure 8This is a schematic diagram of a structure for forming a defective layer by ion implantation into a gallium oxide substrate provided in an embodiment of the present application;

[0045] Fig. 9 It is a structural schematic diagram of another process of bonding and annealing a heterostructure of a gallium oxide substrate and a silicon carbide provided in an embodiment of the present application;

[0046] Figure a in Figure 10 is a schematic structural diagram of a gallium oxide power device provided in an embodiment of the present application;

[0047] FIG. 10 b is a schematic diagram of the structure of another gallium oxide power device provided in an embodiment of the present application; the reference numerals are explained below:

[0048] 100-gallium oxide substrate; 101-defective layer;

[0049] 200-N type silicon carbide;

[0050] 300-P type silicon carbide;

[0051] 400-channel structure;

[0052] 500-drain region or source region;

[0053] 600-gate oxide layer;

[0054] 700-silicon layer;

[0055] 800-metal layer;

[0056] Type 900-P diamond. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0058] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0059] For ease of description, spatial relational terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers. As used herein, "between..." means including the end point values.

[0060] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0061] See also Figure 1 , Figure 1 A schematic flow chart of a method for preparing a gallium oxide power device provided in an embodiment of the present application, the method comprising:

[0062] S10: providing a gallium oxide substrate 100 and a device substrate.

[0063] For example, first, gallium oxide is provided as the gallium oxide substrate 100 ; the size of the gallium oxide can be selected to include 2 inches to 4 inches, etc. as required, and the present application does not impose any specific limitation on this.

[0064] As an optional implementation, the gallium oxide substrate 100 is unintentionally doped gallium oxide; the thickness of the gallium oxide substrate 100 is 500 μm-680 μm; the crystal phase of the gallium oxide substrate 100 is one of (010), (100), (001), and (201).

[0065] Specifically, the crystal phase of the gallium oxide substrate 100 refers to the surface orientation of the crystal plane of gallium oxide, and the gallium oxide is non-intentionally doped gallium oxide.

[0066] Optionally, the gallium oxide includes an α-type gallium oxide single crystal wafer or a β-type gallium oxide single crystal wafer, preferably a β-type gallium oxide single crystal wafer.

[0067] Next, as shown in FIG. 2 a and FIG. 2 b , a silicon carbide heterostructure is provided.

[0068] As an optional embodiment, the device substrate is one of P-type diamond (p-diamond) 900 and a silicon carbide heterostructure; the silicon carbide heterostructure includes P-type silicon carbide and N-type silicon carbide (ie, P-SiC / N-SiC) from top to bottom.

[0069] As shown in FIG. 2 a , the silicon carbide heterostructure may be a silicon carbide heterostructure heterogeneously integrated with a P-type silicon carbide 300 and an N-type silicon carbide 200 .

[0070] As shown in FIG. 2 b , the silicon carbide heterostructure may be P-type diamond 900 .

[0071] As an optional implementation, in the P-type silicon carbide 300, the concentration of the P-type dopant is 1E17 ions / cm 2 -1E18ions / cm 2 ; The thickness of the P-type silicon carbide 300 is 200nm-1000nm;

[0072] In the N-type silicon carbide 200, the concentration of the N-type dopant is 1E17 ions / cm 2 -1E19ions / cm 2 ; The thickness of the N-type silicon carbide 200 is 350μm-600μm.

[0073] Optionally, the N-type dopant may be one of nitrogen, ammonia, acetonitrile, pyrrole, hydrazine, hydrogen cyanide, methylamine, and the like.

[0074] Optionally, the P-type dopant may be one of aluminum (Al), beryllium (Be), and trimethylaluminum (TMA), preferably aluminum (Al).

[0075] Preferably, the thickness of the N-type silicon carbide 200 is 500 μm.

[0076] Optionally, the thickness of the P-type diamond 900 is 200nm-600μm; the P-type dopant can be one of aluminum (Al), beryllium (Be), and trimethylaluminum (TMA), preferably aluminum (Al); in the P-type diamond 900, the concentration of the P-type dopant is 1E17ions / cm 2 -1E18ions / cm 2 .

[0077] S30: bonding the gallium oxide substrate 100 and the device substrate along the upper surface of the device substrate, and performing annealing treatment to obtain a gallium oxide heterostructure; the gallium oxide heterostructure includes the gallium oxide substrate 100 and the device substrate from top to bottom.

[0078] Exemplarily, the drawings in the embodiments of the present application illustrate the device substrate as a silicon carbide heterostructure, but this is only an example, and the silicon carbide heterostructure including the P-type silicon carbide 300 and the N-type silicon carbide 200 can be equivalently replaced by P-type diamond 900.

[0079] like Figure 3 As shown, the device substrate is a silicon carbide heterostructure for illustration, the gallium oxide substrate 100 and the silicon carbide heterostructure are bonded along the upper surface of the silicon carbide heterostructure, that is, the upper surface of the P-type silicon carbide 300, and annealed to obtain a gallium oxide heterostructure which is, from top to bottom, the gallium oxide substrate 100, the P-type silicon carbide 300, and the N-type silicon carbide 200. The purpose of the annealing treatment is to improve the defects of the heterostructure, repair the loss caused by ion implantation, enhance the interface strength between the gallium oxide substrate 100 and the silicon carbide heterostructure, improve the performance of the device finally prepared, and improve the lattice quality and activate the dopant in the silicon carbide, so that it moves from the interstitial position to the alternative position in the lattice, thereby changing the electrical properties of the semiconductor, such as increasing the carrier concentration.

[0080] S50 : performing a groove process on the gallium oxide heterostructure to expose a portion of the surface of the device substrate and form a channel structure 400 ; the opening direction of the channel structure 400 is located on the gallium oxide substrate 100 .

[0081] For example, Figure 4 As shown, taking the device substrate as a silicon carbide heterostructure as an example, a groove is made on the surface of the gallium oxide substrate 100 of the gallium oxide heterostructure to expose the surface of the P-type silicon carbide 300, forming a channel structure 400, so that the P-type silicon carbide 300 can be regulated to form an inversion channel. The inversion channel is the reason why the device is turned on, and it constitutes a conductive channel. On a P-type substrate, by applying a positive voltage to the gate, electrons can be attracted to form an N-type thin layer under the gate, that is, an inversion layer, thereby forming a conductive channel; the generation and elimination of the inversion channel can be controlled by the gate voltage. The threshold voltage (VT) is the gate voltage that causes the inversion layer to appear or disappear. For an enhancement-type device, this voltage is called the turn-on voltage; for a depletion-type device, it is called the pinch-off voltage; the existence of the inversion channel enables the device to control the current between the source and the drain to achieve a switching function. In the inversion channel, the concentration of minority carriers has an exponential relationship with the depth of the surface potential well (proportional to the gate voltage). Therefore, when the gate voltage causes a channel to appear on the semiconductor surface, the concentration of minority carriers in the channel will be very large, which enhances the lateral conduction of the channel.

[0082] As an optional implementation, when the device substrate is a silicon carbide heterostructure, the sum of the thicknesses of the gallium oxide substrate 100 and the P-type silicon carbide 300 is a first thickness; and the depth of the channel structure 400 is greater than the thickness of the gallium oxide substrate 100 and less than the first thickness.

[0083] When the device substrate is P-type diamond, the sum of the thickness of the gallium oxide substrate 100 and the P-type diamond 900 is a second thickness, and the depth of the channel structure 400 is greater than the thickness of the gallium oxide substrate 100 and less than the second thickness.

[0084] Exemplarily, the depth of the groove is greater than the thickness of the gallium oxide substrate 100 and less than the sum of the thicknesses of the gallium oxide substrate 100 and the P-type silicon carbide 300 , so as to ensure that the P-type silicon carbide 300 is exposed after the groove process.

[0085] Optionally, the depth of the groove is preferably equal to the sum of the thickness of the gallium oxide substrate 100 and half of the thickness of the P-type silicon carbide 300 .

[0086] By preparing the channel structure 400, the embodiment of the present application can form an inversion channel by controlling the interface P-type silicon carbide 300 or P-type diamond 900, and control the depth of the groove processing to control the switching of the device, thereby improving the reliability of the gallium oxide device and reducing power loss.

[0087] S70 : performing drain-source implantation on the gallium oxide substrate 100 to form a source region 500 and a drain region 500 located in the gallium oxide substrate 100 .

[0088] For example, Figure 5 As shown, drain-source implantation is performed on a selected region of the gallium oxide substrate 100. Specifically, drain-source implantation is performed on a region of the surface of the gallium oxide substrate 100 where the channel structure 400 is not prepared, so as to form a source region 500 and a drain region 500 located in the gallium oxide substrate 100. Performing drain-source implantation can form the source-drain region 500, thereby improving device performance, reducing costs, and improving reliability.

[0089] It should be noted that the embodiment of the present application does not limit the specific positions of the source region 500 and the drain region 500 .

[0090] As an optional implementation, the implanted ions for the drain-source implantation are silicon ions, and the implantation energy is 10-50kev.

[0091] As an optional implementation, after the above step S80, the above method further includes:

[0092] The gallium oxide heterostructure is annealed at a temperature of 900° C. to 1200° C. and for a time of 2 min to 60 min.

[0093] Exemplarily, after the drain-source implantation, in order to further enhance the structural integrity of the gallium oxide heterostructure and repair defects, the gallium oxide heterostructure is annealed.

[0094] S90 : performing gate oxide deposition on the channel structure 400 to obtain a gate oxide layer 600 located on the surface of the channel structure 400 .

[0095] For example, the schematic diagram of the preparation process of the gate oxide layer 600 is as follows: Figure 6 As shown, the gate oxide layer 600 is also called an isolation layer or an insulating layer. Its purpose is to insulate the gate voltage and prevent current from flowing from the gate to the semiconductor substrate. It also serves as an isolation layer for the conductive channel to ensure that the transistors or different parts of the transistors are electrically isolated to prevent leakage.

[0096] Optionally, the gate oxide deposition method may be thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), high temperature oxidation, using SiH 4 Gas deposition of Si thin films, gate oxide thickening technology at trench corners, etc.

[0097] As an optional implementation, the gate oxide layer 600 is made of at least one of silicon oxide, aluminum oxide, and hafnium oxide, and has a thickness of 5 nm-50 nm.

[0098] For example, in order to further optimize the performance of the gallium oxide power device, specifically, to increase the switching speed and reduce the power consumption, it is necessary to precisely control the thickness and quality of the gate oxide layer 600, so the material of the gate oxide layer 600 is controlled to include at least one of silicon oxide, aluminum oxide, and hafnium oxide, with a thickness of 5nm-50nm.

[0099] S110: preparing a field plate structure on the upper surface of the gallium oxide substrate 100 and at a position close to the channel structure 400 to obtain a gallium oxide power device.

[0100] Exemplarily, in order to improve the terminal efficiency of the gallium oxide structure, reduce the influence of surface charge, and increase device stability, a field plate structure is prepared near the channel structure 400 to obtain a gallium oxide power device. Specifically, the field plate structure is a technology used in semiconductor devices to increase withstand voltage and reduce electric field concentration.

[0101] Optionally, the method for preparing the field plate structure can be a deposition method: a dielectric layer is deposited on the surface of the semiconductor epitaxial wafer by methods such as plasma evaporation (PECVD), quasi-atmospheric pressure vapor deposition (APCVD), low pressure vapor deposition (LPCVD), sputtering evaporation and atomic layer deposition (ALD). These dielectric layers can be silicon oxide (SiO 2) or other insulating materials; plasma dry etching: using the slope photoresist as a mask, the dielectric layer is plasma dry-etched to obtain a slope-shaped dielectric layer, and then a slope field plate is made; metal evaporation: a field plate structure is formed on the surface and at the positioning hole by metal evaporation. The metal evaporation methods include magnetron sputtering, electron beam evaporation, thermal evaporation, electroplating, etc.

[0102] As an optional implementation, in the above step S110, if Figure 7 As shown, the field plate structure includes a silicon layer 700 and a metal layer 800; the field plate structure is prepared on the upper surface of the gallium oxide substrate 100 and close to the channel structure 400 to obtain the gallium oxide power device, including:

[0103] S1101: depositing a silicon layer 700 on the upper surface of the gallium oxide substrate 100 and close to the channel structure 400 to obtain the silicon layer 700 on the gallium oxide substrate 100; the material of the silicon layer 700 includes at least one of silicon oxide and silicon nitride.

[0104] Illustratively, a silicon layer 700 is deposited on the upper surface of the gallium oxide substrate 100 near the channel structure 400 to obtain a silicon layer 700 located on the gallium oxide substrate 100. The noble layer may be silicon oxide or silicon carbide, or a combination of the two. The silicon layer 700 serves as an insulating medium, which helps to change the potential distribution, thereby increasing the breakdown voltage of the device; and can also serve as a protective layer to prevent electric field concentration and instability caused by surface charges, thereby reducing the influence of surface charges on the withstand voltage characteristics of the device.

[0105] S1102: performing metal deposition on a partial area of ​​the silicon layer 700 and performing metal deposition on the channel structure 400 to prepare the metal layer 800 and obtain the gallium oxide power device; the material of the metal layer 800 includes one of titanium and gold; the sum of the thickness of the metal layer 800 and the silicon layer 700 is 80nm-100nm.

[0106] Exemplarily, a metal substrate is formed on a part of the silicon layer 700 and on the channel structure 400 to prepare a metal layer 800, thereby obtaining a gallium oxide power device. The metal layer 800 is usually used as a part of the field plate structure and is used in conjunction with the silicon layer 700 to form a field plate structure. When a negative bias relative to the drain is applied to the field plate, electrons in the N region are attracted to move toward the surface, causing the depletion layer to expand outward, thereby increasing the breakdown voltage; the metal layer 800 helps to reduce the junction electric field peak and improve the withstand voltage of the device.

[0107] Optionally, in order to reduce electric field concentration, lower electric field peak, optimize potential distribution, and improve withstand voltage, the metal layer 800 is controlled not to completely cover the silicon layer 700 .

[0108] The embodiment of the present application prepares a field plate structure including a silicon layer 700 and a metal layer 800 on the surface of gallium oxide, which can not only improve the breakdown voltage of the device and protect the device, but also improve the terminal efficiency of the gallium oxide structure, reduce the influence of surface charge, and increase the stability of the device.

[0109] The present application provides a method for preparing a gallium oxide power device. After bonding and annealing a gallium oxide substrate 100 and a silicon carbide heterostructure, heterogeneous integration of gallium oxide and silicon carbide heterostructure is achieved, thereby improving the heat dissipation capacity of the gallium oxide power device. Then, the gallium oxide heterostructure is grooved to expose a portion of the surface of the device substrate to form a channel structure 400, which can control the switching of the device and realize a natural enhanced power device, thereby improving the safety of the gallium oxide device in the module and the circuit. Then, a field plate structure is prepared on the channel structure 400 and the gallium oxide substrate 100, which can improve the breakdown voltage of the device, suppress current collapse, improve period performance, and optimize electric field distribution, thereby obtaining an enhanced, high-thermal-conductivity gallium oxide power device based on heterogeneous integration.

[0110] As an optional implementation, after the above step S10, the method further includes:

[0111] Ion implantation is performed on the gallium oxide substrate 100 to form a defect layer 101 in the gallium oxide substrate 100; the type of the ion implantation is at least one of hydrogen ions and helium ions; the implantation dose of the ion implantation is 1E16 ions / cm 2 -1E19ions / cm 2 ; The energy of the ion implantation is 20KeV-300KeV.

[0112] For example, Figure 8 As shown, Figure 8 A schematic diagram of a structure for forming a defective layer 101 by ion implantation of a gallium oxide substrate 100 provided in an embodiment of the present application. That is, the gallium oxide substrate 100 provided in the embodiment of the present application may also be a gallium oxide substrate 100 that has been pre-treated with ion implantation, and the gallium oxide substrate 100 that has been treated with ion implantation contains a defective layer 101. The conditions for ion implantation may be: the type of ion implantation is at least one of hydrogen ions and helium ions; the implantation dose of the ion implantation is 1E16ions / cm 2 -1E19ions / cm 2 ; The energy of the ion implantation is 20KeV-300KeV.

[0113] Optionally, the depth of ion implantation is not limited in the present application, and may be less than the thickness of the gallium oxide substrate 100 .

[0114] In the embodiment of the present application, ion implantation is performed on the gallium oxide substrate 100 to form a defect layer 101 in the gallium oxide substrate 100, thereby forming a current blocking layer, which is crucial for the subsequent preparation of the channel structure 400 and can isolate the current path between the source and the drain to achieve current regulation; and can improve the breakdown voltage and power quality factor of the gallium oxide power device.

[0115] As an optional implementation, in the above step S30, if Fig. 9 As shown, in the case where the oxide layer substrate includes a defect layer 101, the gallium oxide substrate 100 is bonded to the silicon carbide heterostructure along the upper surface of the device substrate, and annealed to obtain the gallium oxide heterostructure, including:

[0116] S301: Bonding the gallium oxide substrate 100 and the silicon carbide heterostructure along the upper surface of the device substrate to obtain a first bonding structure; the bonding method is hydrophilic bonding or surface activated bonding.

[0117] Exemplarily, taking the device substrate as a silicon carbide heterostructure as an example, the gallium oxide substrate 100 and the silicon carbide heterostructure are bonded along the upper surface of the silicon carbide heterostructure, that is, the upper surface of the P-type silicon carbide 300 to obtain a first bonding structure. Specifically, the bonding method can adopt hydrophilic bonding or surface activation bonding. If the selected substrate is a P-type diamond 900, the above process is: the gallium oxide substrate 100 and the P-type diamond 900 are bonded along the upper surface of the P-type diamond 900.

[0118] When surface activated bonding is used for bonding, the bonding conditions should be controlled as follows: vacuum degree is less than 5х10 -6 Pa, the activation gas is argon, the time is greater than 10s, the pressure is greater than 1000N, the power is greater than 1000V, and the current is 0.5mA; when hydrophilic bonding is adopted, the activation gas is one of oxygen, nitrogen or argon, the time is greater than 10s, and the power is greater than 100W.

[0119] S302: performing high temperature annealing treatment on the first bonding structure, so that the first bonding structure is peeled off along the defective layer 101 to obtain the gallium oxide heterostructure.

[0120] For example, in order to enhance the interface strength between the gallium oxide substrate 100 and the device substrate, improve the lattice quality, activate the dopants in silicon carbide or diamond, improve the defects of the heterostructure, and repair the loss caused by ion implantation, and improve the performance of the finally prepared device, the first bonding structure is subjected to high temperature annealing treatment so that the first bonding result is peeled off along the defective layer 101 to obtain a gallium oxide heterostructure.

[0121] Optionally, the high temperature annealing treatment may be performed at 900° C.-1200° C. for 2 min-60 min.

[0122] The embodiments of the present application can improve the heat dissipation capability of gallium oxide power devices by heterogeneously integrating gallium oxide and silicon carbide.

[0123] On the other hand, as shown in FIG. 10 , an embodiment of the present application further provides a gallium oxide power device, which is prepared by the above-mentioned method for preparing a gallium oxide power device.

[0124] Specifically, gallium oxide power devices include:

[0125] Device substrate; an unintentionally doped gallium oxide substrate 100, located on the surface of the P-type silicon carbide 300; an active region 500 and a drain region 500 in the unintentionally doped gallium oxide substrate 100 where the channel structure 400 is not prepared;

[0126] The channel structure 400 is formed by trenching the upper surface of the unintentionally doped gallium oxide substrate 100 to expose the surface of the P-type semiconductor layer;

[0127] A gate oxide layer 600 is located on the surface of the channel structure 400;

[0128] The field plate structure includes a metal layer 800 and a silicon layer 700. The silicon layer 700 is located on the surface of the non-intentionally doped gallium oxide substrate 100 and close to the position of the channel result. The metal layer 800 is deposited on the surface of the gate oxide layer 600 and the surface of the silicon layer 700, and the metal layer 800 does not completely cover the silicon layer 700.

[0129] Specifically, as shown in Figure a of Figure 10 , the device substrate is P-type diamond 900;

[0130] Or as shown in FIG. 10 b , the device substrate is a silicon carbide heterostructure; the silicon carbide heterostructure includes P-type silicon carbide 300 and N-type silicon carbide 200 from top to bottom.

[0131] In summary, the gallium oxide power device and its preparation method of the present invention transfer the unintentionally doped gallium oxide substrate 100 to the device substrate by bonding and annealing methods, and the gallium oxide substrate 100 can be ion-implanted to obtain a gallium oxide heterostructure, and the gallium oxide heterostructure is grooved, deposited, and field plate structure is prepared to prepare a gallium oxide power device to solve the problems of low reliability, large power loss, and low power characteristics of gallium oxide devices, improve the reliability and power characteristics of gallium oxide power devices, and reduce power loss. It is of great significance for the future development of enhanced, high thermal conductivity gallium oxide heterogeneous integrated power devices. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0132] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit the scope of protection of the present invention. Although the present invention is described in detail with reference to the preferred embodiments, it is not limited to those listed in the embodiments. Those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the essence and scope of the technical solution of the present invention.

Claims

1. A method for preparing a gallium oxide power device, characterized in that: The preparation method comprises: Providing a gallium oxide substrate and a device substrate; Bonding the gallium oxide substrate and the device substrate along the upper surface of the device substrate, and performing annealing treatment to obtain a gallium oxide heterostructure; the gallium oxide heterostructure includes the gallium oxide substrate and the device substrate in order from top to bottom; Performing a groove process on the gallium oxide heterostructure to expose a portion of the upper surface of the device substrate to form a channel structure; the opening direction of the channel structure is located on the gallium oxide substrate; Performing drain-source implantation on the gallium oxide substrate to form a source region and a drain region in the gallium oxide substrate; Performing gate oxide deposition on the channel structure to obtain a gate oxide layer located on the surface of the channel structure; A field plate structure is prepared on the upper surface of the gallium oxide substrate and close to the channel structure to obtain the gallium oxide power device.

2. The preparation method according to claim 1, characterized in that: The field plate structure includes a silicon layer and a metal layer; the field plate structure is prepared on the upper surface of the gallium oxide substrate and close to the channel structure to obtain the gallium oxide power device, including: Depositing a silicon layer on the upper surface of the gallium oxide substrate and close to the channel structure to obtain the silicon layer on the gallium oxide substrate; the material of the silicon layer includes at least one of silicon oxide and silicon nitride; Metal deposition is performed on a partial area of ​​the silicon layer, and metal deposition is performed on the channel structure to prepare the metal layer and obtain the gallium oxide power device; the material of the metal layer includes one of titanium and gold; the sum of the thickness of the metal layer and the silicon layer is 80nm-100nm.

3. The preparation method according to claim 1, characterized in that: After providing the gallium oxide substrate and the device substrate, the method further comprises: Ion implantation is performed on the gallium oxide substrate to form a defect layer in the gallium oxide substrate; the type of the ion implantation is at least one of hydrogen ions and helium ions; the implantation dose of the ion implantation is 1E16 ions / cm 2 -1E19ions / cm 2 ; The energy of the ion implantation is 20KeV-300KeV.

4. The preparation method according to claim 3, characterized in that: The gallium oxide substrate and the device substrate are bonded along the upper surface of the device substrate, and annealed to obtain a gallium oxide heterostructure, comprising: The gallium oxide substrate and the device substrate are bonded along the upper surface of the device substrate to obtain a first bonding structure; the bonding method is hydrophilic bonding or surface activated bonding; The first bonding structure is subjected to high temperature annealing treatment so as to peel off the first bonding structure along the defect layer to obtain the gallium oxide heterostructure.

5. The preparation method according to claim 1, characterized in that: After performing drain-source implantation on the gallium oxide substrate to form a source region and a drain region in the gallium oxide substrate, the method further comprises: The gallium oxide heterostructure is annealed at a temperature of 900° C. to 1200° C. and for a time of 2 min to 60 min.

6. The preparation method according to claim 1, characterized in that: The device substrate is one of P-type diamond and silicon carbide heterostructure; The silicon carbide heterostructure includes P-type silicon carbide and N-type silicon carbide from top to bottom.

7. The preparation method according to claim 1, characterized in that: The gallium oxide substrate is unintentionally doped gallium oxide; The thickness of the gallium oxide substrate is 500 μm-680 μm; The crystalline phase of the gallium oxide substrate is one of (010), (100), (001), and (201).

8. The preparation method according to claim 6, characterized in that: In the P-type silicon carbide, the concentration of the P-type dopant is 1E17ions / cm 2 -1E18ions / cm 2 ; The thickness of the P-type silicon carbide is 200nm-1000nm; In the N-type silicon carbide, the concentration of the N-type dopant is 1E17ions / cm 2 -1E19ions / cm 2 ; The thickness of the N-type silicon carbide is 350μm-600μm.

9. The preparation method according to claim 1, characterized in that: The implanted ions used in the drain-source implantation are silicon ions, and the implantation energy is 10-50kev; The gate oxide layer is made of at least one of silicon oxide, aluminum oxide and hafnium oxide, and has a thickness of 5nm-50nm.

10. A gallium oxide power device, characterized in that: The gallium oxide power device is prepared by the method for preparing the gallium oxide power device according to any one of claims 1 to 9.

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