Method of manufacturing a semiconductor device

Abstract

The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a manufacturing method of a semiconductor device. The method comprises the following steps: providing a semiconductor substrate; forming a deep trench isolation structure in an isolation region, the upper surface of the deep trench isolation structure being higher than the upper surface of an active region by a specific height; sequentially performing first etching and second etching on the active region of a high-voltage device region and the edge part of the deep trench isolation structure of the high-voltage device region close to the active region; performing etching on the edge part of the deep trench isolation structure of the high-voltage device region close to the active region after the first etching and the second etching, so as to reduce the height difference between the upper surface of the active region of the high-voltage device region and the upper surface of the edge part of the deep trench isolation structure of the high-voltage device region close to the active region; and depositing a high-voltage oxide layer, the high-voltage oxide layer covering the upper surface of the active region of the high-voltage device region and the upper surface of the edge part of the deep trench isolation structure of the high-voltage device region close to the active region.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit manufacturing technology, and more specifically to a method for manufacturing a semiconductor device. Background Technology

[0002] As transistor sizes continue to shrink, metal gates have replaced polysilicon gates as an indispensable part of processes below 28nm.

[0003] The gate oxide process in existing high-voltage MOSFETs involves directly growing the gate oxide layer on the silicon substrate surface. However, since the gate oxide layer thickness of high-voltage and medium-voltage MOSFETs is thicker than that of low-voltage MOSFETs on the same wafer, there are significant step differences in the high-voltage and medium-voltage gate oxide layers grown using the existing process in their respective active and isolation regions.

[0004] During the metal gate fabrication process, because all devices on the same wafer are ground simultaneously, the gate oxide layer at the boundary between the active and isolation regions of the high-voltage MOSFET region and the medium-voltage MOSFET region is unevenly ground due to a large step difference. This results in areas where the metal gate formed in the high-voltage MOSFET region and the medium-voltage MOSFET region is too thin, which makes it easy for subsequent contact holes to penetrate the metal gate of the high-voltage MOSFET region and the medium-voltage MOSFET region, thus leading to device performance failure. Summary of the Invention

[0005] This application provides a method for manufacturing a semiconductor device, which can solve the problem in related technologies that there is a large step difference in the gate oxide layer at the junction of the active region and the isolation region in both high-voltage MOSFET regions and medium-voltage MOSFET regions.

[0006] To address the technical problems in the background art, this application provides a method for manufacturing a semiconductor device, the method comprising the following steps:

[0007] A semiconductor substrate is provided, the semiconductor substrate including a high-voltage device region, a medium-voltage device region and a low-voltage device region, wherein each of the high-voltage device region, the medium-voltage device region and the low-voltage device region includes an active region and an isolation region, respectively;

[0008] A deep trench isolation structure is formed in the isolation area, and the upper surface of the deep trench isolation structure is higher than the upper surface of the active area by a specific height;

[0009] The active region of the high-voltage device region and the edge portion of the deep trench isolation structure of the high-voltage device region near the active region are sequentially etched with a first etching and a second etching; wherein, the etching amount in the first etching accounts for 70% to 85% of the total etching amount, and the total etching amount is the total etching amount of the first etching and the second etching.

[0010] The edge portion of the deep trench isolation structure in the high voltage device region near the active region after the first and second etching is etched to reduce the height difference between the upper surface of the active region of the high voltage device region and the upper surface of the edge portion of the deep trench isolation structure in the high voltage device region near the active region.

[0011] A high-pressure oxide layer is deposited to form a high-pressure oxide layer that covers the upper surface of the active region of the high-pressure device region and the upper surface of the edge portion of the deep trench isolation structure of the high-pressure device region near the active region.

[0012] Optionally, the step of sequentially performing a first etching and a second etching on the active region of the high-voltage device region and the edge portion of the deep trench isolation structure of the high-voltage device region near the active region; wherein the etching amount in the first etching accounts for 70% to 85% of the total etching amount, and the total etching amount is the total amount of etching in the first and second etchings, includes:

[0013] A high-voltage oxide layer mask pattern structure is formed on the semiconductor substrate, wherein the active region of the high-voltage device region and the edge portion of the deep trench isolation structure of the high-voltage device region near the active region are exposed from the high-voltage oxide layer mask pattern structure;

[0014] Based on the high-pressure oxide layer mask pattern structure, the structure exposed from the high-pressure oxide layer mask pattern structure is first etched according to the first etching amount;

[0015] Based on the first etching, and based on the high-pressure oxide layer mask pattern structure, the structure exposed from the high-pressure oxide layer mask pattern structure is etched a second time according to the second etching amount.

[0016] The first etching amount accounts for 70% to 85% of the total etching amount, and the total etching amount is the sum of the first etching amount and the second etching amount.

[0017] Optionally, the step of forming a high-voltage oxide mask pattern structure on the semiconductor substrate, wherein the active region of the high-voltage device region and the edge portion of the deep trench isolation structure of the high-voltage device region near the active region are exposed from the high-voltage oxide mask pattern structure, includes:

[0018] A hard mask layer is deposited on the semiconductor substrate;

[0019] The hard mask layer is etched using a photolithography etching process to form a high-voltage oxide layer mask pattern structure, which includes a high-voltage oxide layer forming window; the active region of the high-voltage device region and the edge portion of the deep trench isolation structure of the high-voltage device region near the active region are exposed from the high-voltage oxide layer forming window.

[0020] Optionally, the step of performing a first etching on the structure exposed from the high-pressure oxide layer mask pattern structure according to a first etching amount includes:

[0021] In an atmosphere containing any one or more of nitrogen tetrafluoride, nitrogen trifluoride, and chlorine, a dry etching plasma is generated, which bombards the device with the high-pressure oxide layer mask pattern structure, and the structure exposed from the high-pressure oxide layer mask pattern structure is etched according to a first etching amount.

[0022] Optionally, the step of performing a second etching on the structure exposed from the high-pressure oxide layer mask pattern structure according to a second etching amount based on the first etching, on the basis of the high-pressure oxide layer mask pattern structure, includes:

[0023] Based on the first etching, a dry etching plasma is generated in a gas atmosphere containing any one or more combinations of nitrogen tetrafluoride, nitrogen trifluoride, and chlorine. The dry etching plasma bombards the device with the high-pressure oxide layer mask pattern structure, and the structure exposed from the high-pressure oxide layer mask pattern structure is etched a second time according to the second etching amount.

[0024] Optionally, the following steps are also included:

[0025] The edge portion of the deep trench isolation structure in the medium-voltage device region near the active region is etched to reduce the height difference between the upper surface of the active region of the medium-voltage device region and the upper surface of the edge portion of the deep trench isolation structure in the medium-voltage device region near the active region.

[0026] A medium-pressure oxide layer is deposited to form a medium-pressure oxide layer that covers the upper surface of the active region of the medium-pressure device region and the upper surface of the edge portion of the deep trench isolation structure of the medium-pressure device region near the active region.

[0027] The technical solution of this application includes at least the following advantages: By improving the high uniformity of the high-pressure oxide layer or medium-pressure oxide layer and the upper surface of the isolation structure, this application ensures that the thickness uniformity of the metal gate is stronger in the subsequent manufacturing process of the metal gate, avoiding the occurrence of excessively thin areas in the manufactured metal gate, thereby laying the groundwork for improving the reliability of the device. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0029] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application is shown;

[0030] Figure 2 A schematic diagram of the longitudinal cross-sectional structure of the semiconductor substrate provided in step S1 is shown;

[0031] Figure 3 A longitudinal cross-sectional view of the device after step S2 is shown.

[0032] Figure 4 This shows a longitudinal cross-sectional view of the high-voltage device area after step S31 is completed;

[0033] Figure 5 This shows a schematic diagram of the device's longitudinal cross-sectional structure after step S32 is completed;

[0034] Figure 6 This shows a schematic diagram of the device's longitudinal cross-sectional structure after step S33 is completed;

[0035] Figure 7 A schematic diagram of the cross-sectional structure of the device after step S4 is shown;

[0036] Figure 8 A schematic diagram of the cross-sectional structure of the device after step S5 is shown;

[0037] Figure 9 A schematic diagram of the cross-sectional structure of the device after step S7 is shown. Detailed Implementation

[0038] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0040] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0041] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0042] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application is shown. Figure 1 As can be seen from this, the manufacturing method of this semiconductor device includes the following steps:

[0043] Step S1: Provide a semiconductor substrate, the semiconductor substrate including a high voltage device region, a medium voltage device region and a low voltage device region, the high voltage device region, the medium voltage device region and the low voltage device region each including an active region and an isolation region.

[0044] The substrate includes a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. An SOI substrate includes an insulating layer beneath a thin semiconductor layer that serves as the active layer. The active layer and bulk semiconductor typically comprise the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0045] Figure 2 This diagram shows a longitudinal cross-sectional view of the semiconductor substrate provided in step S1. Figure 2 As can be seen, the semiconductor substrate includes a high-voltage device region 300, a medium-voltage device region 200, and a low-voltage device region 100 in the lateral direction. The high-voltage device region 300 includes a high-voltage device active region 310 and high-voltage device isolation regions 320 located on both sides of the high-voltage device active region 310. The high-voltage device active region 310 is used to form a high-voltage device in subsequent processes, and the high-voltage device isolation regions 320 are used to isolate the high-voltage device active region 310 from other regions. The medium-voltage device region 200 includes a medium-voltage device active region 210 and medium-voltage device isolation regions 220 located on both sides of the medium-voltage device active region 210. The medium-voltage device active region 210 is used to form a medium-voltage device in subsequent processes, and the medium-voltage device isolation regions 220 are used to isolate the medium-voltage device active region 210 from other regions. The low-voltage device region 100 includes a low-voltage device active region 110 and low-voltage device isolation regions 120 located on both sides of the low-voltage device active region 110. The active region 110 of the low-voltage device is used to form the low-voltage device in subsequent processes, and the isolation region 120 of the low-voltage device is used to isolate the active region 110 of the low-voltage device from other regions.

[0046] Step S2: A deep trench isolation structure is formed in the isolation area, wherein the upper surface of the deep trench isolation structure is higher than the upper surface of the active area by a specific height.

[0047] Reference Figure 3 It shows a longitudinal cross-sectional view of the device after step S2, from Figure 3 As can be seen, the deep trench isolation structures for various device regions are located at the isolation areas of the corresponding device regions. These include the high-voltage device isolation structure 321 located at the high-voltage device isolation area 320, the medium-voltage device isolation structure 221 located at the medium-voltage device isolation area 220, and the low-voltage device isolation structure 121 located at the low-voltage device isolation area 120.

[0048] The upper surface of the high-voltage device isolation structure 321 is higher than the upper surface of the high-voltage device active region 310 by a first height, the upper surface of the medium-voltage device isolation structure 221 is higher than the upper surface of the medium-voltage device active region 210 by a second height, and the upper surface of the low-voltage device isolation structure 121 is higher than the upper surface of the low-voltage device active region 110 by a third height.

[0049] Step S3: Sequentially perform first etching and second etching on the active region of the high voltage device region and the edge portion of the deep trench isolation structure of the high voltage device region near the active region; wherein, the etching amount in the first etching accounts for 70% to 85% of the total etching amount, and the total etching amount is the total etching amount of the first etching and the second etching.

[0050] For example, step S3 can be implemented by the following steps S31 to S33:

[0051] Step S31: A high-voltage oxide mask pattern structure is formed on the semiconductor substrate, wherein the active region of the high-voltage device region and the edge portion of the deep trench isolation structure of the high-voltage device region near the active region are exposed from the high-voltage oxide mask pattern structure.

[0052] Reference Figure 4 It shows a longitudinal cross-sectional view of the high-voltage device region after step S31 is completed. From Figure 1 As can be seen, a high-voltage oxide layer mask pattern structure 400 is formed on the semiconductor substrate, the high-voltage device active region 310, and the edge portion of the high-voltage device isolation structure 321 near the high-voltage device active region 310 (part A in the figure) are exposed from the high-voltage oxide layer mask pattern structure 400.

[0053] For example, step S31 can be implemented by the following steps S311 to S312 performed sequentially:

[0054] Step S311: Deposit a hard mask layer on the semiconductor substrate.

[0055] Step S312: The hard mask layer is etched by photolithography to form a high-voltage oxide layer mask pattern structure, the high-voltage oxide layer mask pattern structure includes a high-voltage oxide layer forming window; the active region of the high-voltage device region and the edge portion of the deep trench isolation structure of the high-voltage device region near the active region are exposed from the high-voltage oxide layer forming window.

[0056] Step S32: Based on the high-pressure oxide layer mask pattern structure, perform a first etching on the structure exposed from the high-pressure oxide layer mask pattern structure according to a first etching amount.

[0057] Reference Figure 5 It shows a schematic diagram of the device's longitudinal cross-sectional structure after step S32 is completed. From Figure 5 As can be seen, after the first etching is completed, the substrate of the active region 310 of the high voltage device and the edge portion of the isolation structure 321 of the high voltage device near the active region 310 of the high voltage device (part A in the figure) are etched away from their respective upper surfaces downward according to the first etching amount OE1.

[0058] For example, the first etching can be performed using dry etching. For instance, a dry etching plasma is generated in an atmosphere of one or more gases, such as nitrogen tetrafluoride, nitrogen trifluoride, and chlorine, to perform a first etching on the structure exposed from the high-pressure oxide mask pattern structure according to a first etching amount.

[0059] Step S33: Based on the first etching, the exposed structure from the high-pressure oxide layer mask pattern structure is etched a second time according to the second etching amount, based on the high-pressure oxide layer mask pattern structure.

[0060] The first etching amount accounts for 70% to 85% of the total etching amount. The total etching amount is the sum of the first etching amount and the second etching amount.

[0061] Reference Figure 6 It shows a schematic longitudinal cross-sectional view of the device after step S33 is completed. From Figure 6 As can be seen, after the second etching is completed, based on the first etching, the substrate of the active region 310 of the high voltage device and the edge portion of the isolation structure 321 of the high voltage device near the active region 310 of the high voltage device (part A in the figure) are etched and removed from their respective upper surfaces downward according to the second etching amount OE2.

[0062] For example, the second etching can be performed using dry etching. For instance, a dry etching plasma is generated in an atmosphere of one or more gases, such as nitrogen tetrafluoride, nitrogen trifluoride, and chlorine, to perform a second etching on the structure exposed from the high-pressure oxide mask pattern structure according to the second etching amount.

[0063] This embodiment etches the exposed structure from the high-voltage oxide layer mask pattern structure through two etching processes. The total etching amount is the sum of the first etching amount and the second etching amount, with the first etching being the main etching step. The proportion of the etching amount in the first etching is increased, while the proportion of the etching amount in the second etching is decreased. This reduces the height difference between the upper surface of the active region of the high-voltage device region and the upper surface of the edge portion of the deep trench isolation structure near the active region of the high-voltage device region, thereby reducing the height difference between the metal gate in the active region of the high-voltage device region and the deep trench isolation structure.

[0064] Step S4: Etch the edge portion of the deep trench isolation structure of the high voltage device region near the active region after the first and second etching to reduce the height difference between the upper surface of the active region of the high voltage device region and the upper surface of the edge portion of the deep trench isolation structure of the high voltage device region near the active region.

[0065] Reference Figure 7 It shows a schematic cross-sectional view of the device after step S4 is completed. From Figure 7As can be seen, after step S4 is completed, the high-voltage device isolation structure 321 exposed in the high-voltage oxide layer mask pattern structure 400 continues to be etched downwards from the edge portion (part A in the figure) near the active region 310 of the high-voltage device, while the substrate of the active region 310 of the high-voltage device is not etched. This reduces the step between the upper surface of the edge portion (part A in the figure) of the high-voltage device isolation structure 321 near the active region 310 of the high-voltage device and the upper surface of the active region 310 of the high-voltage device. As a result, after the high-voltage oxide layer is fabricated on the active region of the high-voltage device in the subsequent process, the surface morphology of the high-voltage device region can be flatter.

[0066] For example, wet etching solutions can be used to achieve different etching selectivity for different materials. By employing a wet etching process that has a higher etching selectivity for etching deep trench isolation structures than for etching the active region substrate of high voltage device regions, the edge portion of the deep trench isolation structure near the active region in the high voltage device region can be etched to reduce the height difference between the upper surface of the active region of the high voltage device region and the upper surface of the edge portion of the deep trench isolation structure near the active region in the high voltage device region.

[0067] This step S4 can be performed using a wet etching solution with a hydrogen-fluorine concentration ratio of (100:1 to 200:1) to etch the edge portion of the deep trench isolation structure of the high voltage device region near the active region after the first and second etching, thereby reducing the height difference between the upper surface of the active region of the high voltage device region and the upper surface of the edge portion of the deep trench isolation structure of the high voltage device region near the active region.

[0068] Step S5: Deposit to form a high-voltage oxide layer, which covers the upper surface of the active region of the high-voltage device region and the upper surface of the edge portion of the deep trench isolation structure of the high-voltage device region near the active region.

[0069] Reference Figure 8 It shows a schematic cross-sectional view of the device after step S5 is completed. From Figure 8 As can be seen, the formed high-voltage oxide layer 500 covers the upper surface of the high-voltage device isolation structure 321 near the edge of the high-voltage device active region 310 (part A in the figure) and the upper surface of the high-voltage device active region 310. Furthermore, the high-voltage oxide layer 500 covers the step between the high-voltage device active region 310 and the high-voltage device isolation structure 321, and is connected to the high-voltage device isolation structure 321. Because the above steps reduce the step height, the height uniformity between the upper surface of the high-voltage oxide layer 500 and the upper surface of the high-voltage device isolation structure 321 is relatively strong.

[0070] In other embodiments, the following steps may be performed after step S5:

[0071] Step S6: Etch the edge portion of the deep trench isolation structure in the medium-voltage device region near the active region to reduce the height difference between the upper surface of the active region of the medium-voltage device region and the upper surface of the edge portion of the deep trench isolation structure in the medium-voltage device region near the active region.

[0072] For example, wet etching solutions can be used to achieve different etching selectivity for different materials. By employing a wet etching process that has a higher etching selectivity for etching deep trench isolation structures than for etching the active region substrate of medium-voltage device regions, the edge portion of the deep trench isolation structure near the active region in the medium-voltage device region can be etched to reduce the height difference between the upper surface of the active region of the medium-voltage device region and the upper surface of the edge portion of the deep trench isolation structure near the active region in the medium-voltage device region.

[0073] This step S6 can be performed using a wet etching solution with a hydrogen-fluorine concentration ratio of (100:1 to 200:1) to etch the edge portion of the deep trench isolation structure in the medium-voltage device region near the active region, thereby reducing the height difference between the upper surface of the active region of the medium-voltage device region and the upper surface of the edge portion of the deep trench isolation structure in the medium-voltage device region near the active region.

[0074] Step S7: Deposit to form a medium-pressure oxide layer, which covers the upper surface of the active region of the medium-pressure device region and the upper surface of the edge portion of the deep trench isolation structure of the medium-pressure device region near the active region.

[0075] Reference Figure 9 It shows a schematic cross-sectional view of the device after step S7 is completed. From Figure 9 As can be seen, the formed medium-pressure oxide layer covers the upper surface of the medium-pressure device isolation structure 221 near the edge of the medium-pressure device active region 210 (part B in the figure) and the upper surface of the medium-pressure device active region 210. Furthermore, this medium-pressure oxide layer 600 covers the step between the medium-pressure device active region 210 and the medium-pressure device isolation structure 221, and is connected to the medium-pressure device isolation structure 221. Because the above steps reduce the step height, the height uniformity between the upper surface of the medium-pressure oxide layer 600 and the upper surface of the medium-pressure device isolation structure 221 is relatively strong.

[0076] This embodiment improves the uniformity of the high-pressure oxide layer or medium-pressure oxide layer with the upper surface of the isolation structure, so that the thickness uniformity of the metal gate is stronger in the subsequent manufacturing process of the metal gate, avoiding the occurrence of excessively thin areas in the manufactured metal gate, thereby laying the foundation for improving the reliability of the device.

[0077] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method for manufacturing the semiconductor device comprises the following steps: providing a semiconductor substrate comprising a high-voltage device region, a medium-voltage device region and a low-voltage device region, each of the high-voltage device region, the medium-voltage device region and the low-voltage device region comprising an active region and an isolation region; forming a deep trench isolation structure in the isolation region, wherein the upper surface of the deep trench isolation structure in the high-voltage device region is higher than the upper surface of the active region in the high-voltage device region by a first height, the upper surface of the deep trench isolation structure in the medium-voltage device region is higher than the upper surface of the active region in the medium-voltage device region by a second height, and the upper surface of the deep trench isolation structure in the low-voltage device region is higher than the upper surface of the active region in the low-voltage device region by a third height; sequentially performing first etching and second etching on the active region in the high-voltage device region and the edge portion of the deep trench isolation structure in the high-voltage device region close to the active region, wherein the proportion of the etching amount in the first etching to the total etching amount is 70% to 85%, and the total etching amount is the total amount of etching in the first etching and the second etching; performing etching on the edge portion of the deep trench isolation structure in the high-voltage device region close to the active region after the first etching and the second etching, so as to reduce the height difference between the upper surface of the active region in the high-voltage device region and the upper surface of the edge portion of the deep trench isolation structure in the high-voltage device region close to the active region; depositing a high-voltage oxide layer covering the upper surface of the active region in the high-voltage device region and the upper surface of the edge portion of the deep trench isolation structure in the high-voltage device region close to the active region; wherein the step of sequentially performing first etching and second etching on the active region in the high-voltage device region and the edge portion of the deep trench isolation structure in the high-voltage device region close to the active region, wherein the proportion of the etching amount in the first etching to the total etching amount is 70% to 85%, and the total etching amount is the total amount of etching in the first etching and the second etching, comprises: forming a high-voltage oxide layer mask pattern structure on the semiconductor substrate, and the active region in the high-voltage device region and the edge portion of the deep trench isolation structure in the high-voltage device region close to the active region are exposed from the high-voltage oxide layer mask pattern structure; performing first etching on the structure exposed from the high-voltage oxide layer mask pattern structure according to a first etching amount based on the high-voltage oxide layer mask pattern structure; on the basis of the first etching, performing second etching on the structure exposed from the high-voltage oxide layer mask pattern structure according to a second etching amount based on the high-voltage oxide layer mask pattern structure again; the proportion of the first etching amount to the total etching amount is 70% to 85%, and the total etching amount is the sum of the first etching amount and the second etching amount.

2. The method of manufacturing a semiconductor device according to Claim 1, wherein the step of forming a high-voltage oxide layer mask pattern structure on the semiconductor substrate, and the active region in the high-voltage device region and the edge portion of the deep trench isolation structure in the high-voltage device region close to the active region are exposed from the high-voltage oxide layer mask pattern structure, comprises: depositing a hard mask layer on the semiconductor substrate; The hard mask layer is etched by a lithography etching process to form a high-pressure oxidation layer mask pattern structure, which includes a high-pressure oxidation layer forming window, an active region of the high-pressure device region, and an edge portion of a deep trench isolation structure of the high-pressure device region close to the active region exposed from the high-pressure oxidation layer forming window.

3. The method of manufacturing a semiconductor device according to Claim 1, wherein The step of etching the structure exposed from the high-pressure oxidation layer mask pattern structure according to a first etching amount based on the high-pressure oxidation layer mask pattern structure includes: In an atmosphere containing any one or more of nitrogen tetrafluoride, nitrogen trifluoride, and chlorine gas, dry etching plasma is generated, so that the dry etching plasma bombards the device with the high-pressure oxidation layer mask pattern structure, and etches the structure exposed from the high-pressure oxidation layer mask pattern structure according to a first etching amount.

4. The method of manufacturing a semiconductor device according to Claim 1, wherein The step of etching the structure exposed from the high-pressure oxidation layer mask pattern structure according to a second etching amount based on the high-pressure oxidation layer mask pattern structure on the basis of the first etching includes: In the atmosphere containing any one or more of nitrogen tetrafluoride, nitrogen trifluoride, and chlorine gas, dry etching plasma is generated, so that the dry etching plasma bombards the device with the high-pressure oxidation layer mask pattern structure, and etches the structure exposed from the high-pressure oxidation layer mask pattern structure according to a second etching amount.

5. The method of manufacturing a semiconductor device according to Claim 1, wherein The steps further include: The edge portion of the deep trench isolation structure of the medium-pressure device region close to the active region is etched to reduce the height difference between the upper surface of the active region of the medium-pressure device region and the upper surface of the edge portion of the deep trench isolation structure of the medium-pressure device region close to the active region; A medium-pressure oxidation layer is deposited to cover the upper surface of the active region of the medium-pressure device region and the upper surface of the edge portion of the deep trench isolation structure of the medium-pressure device region close to the active region.

Images