Method for etching logic area of nord flash memory device

Abstract

The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a NORD flash memory device logic area etching method. The method comprises the following steps: providing a substrate layer, wherein the substrate layer comprises a storage area and a logic area; sequentially growing a connection oxide layer, a floating gate polysilicon layer, a polysilicon interlayer and a control gate polysilicon layer on the substrate layer; defining the logic area, etching and removing the control gate polysilicon layer located at the position of the logic area; sequentially depositing a high-temperature oxide layer and a silicon nitride layer, wherein the high-temperature oxide layer and the silicon nitride layer cover the storage area and the logic area; manufacturing storage units of the flash memory device in the storage area; defining the logic area, removing the silicon nitride layer located at the position of the logic area through dry etching, so that the polysilicon interlayer is exposed; removing the remaining polysilicon interlayer located at the position of the logic area; etching and removing the floating gate polysilicon layer located in the logic area.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit manufacturing technology, specifically to a method for etching the logic area of ​​a NORD flash memory device. Background Technology

[0002] NORD flash memory devices include a storage area for storing data and a logic area for performing logic operations. In related technologies, after the memory device is fabricated in the storage area, the logic area needs to be etched to remove the polysilicon layer and some dielectric layers that were applied to the logic area during the fabrication process.

[0003] However, in the etching process of removing the dielectric layer in the logic region, especially when removing a thick silicon nitride layer, related technologies typically employ a combination of dry and wet etching processes. First, the upper part of the silicon nitride layer is removed using dry etching, followed by wet etching to remove the remaining silicon nitride layer. Because the remaining silicon nitride layer is still relatively thick after dry etching, a large amount of phosphoric acid cleaning solution is required for subsequent wet etching. However, the extensive use of this acid cleaning solution can cause damage to the sidewalls of the memory device during the etching process of removing the dielectric layer in the logic region. Figure 3 The problem shown is over-etching, which forms over-etched depressions 410 on the sidewalls of the memory device. These depressions 410 are at risk of peeling off in subsequent processes, which is detrimental to the performance of the logic area devices. Summary of the Invention

[0004] This application provides a method for etching the logic area of ​​a NORD flash memory device, which can solve the problem in related technologies that over-etching can cause etching depressions on the sidewalls of the memory device during the logic area etching process.

[0005] To address the technical problems described in the background art, this application provides a method for etching the logic region of a NORD flash memory device, the method comprising the following sequential steps:

[0006] A substrate layer is provided, the substrate layer including a memory area and a logic area;

[0007] A connecting oxide layer, a floating gate polysilicon layer, a polysilicon inter-dielectric layer, and a control gate polysilicon layer are sequentially grown on the substrate layer.

[0008] Define the logic region and etch away the control gate polysilicon layer located at the logic region location;

[0009] A high-temperature oxide layer and a silicon nitride layer are deposited sequentially, wherein the high-temperature oxide layer and the silicon nitride layer cover the memory area and the logic area;

[0010] The storage cells of the flash memory device are fabricated in the storage area;

[0011] The logic region is defined, and the silicon nitride layer located at the logic region is removed by dry etching, so that the polysilicon inter-dielectric layer is exposed.

[0012] Remove the remaining polysilicon inter-dielectric layer located at the logic region position;

[0013] The floating gate polysilicon layer located in the logic region is removed by etching.

[0014] Optionally, when fabricating the polysilicon inter-dielectric layer, a lower oxide dielectric layer, a silicon nitride dielectric layer, and an upper oxide dielectric layer are sequentially deposited on the floating gate polysilicon layer.

[0015] Optionally, the step of defining the logic region and etching away the control gate polysilicon layer located in the logic region includes:

[0016] The logic region is defined, and the control gate polysilicon layer located in the logic region is etched away using the silicon nitride dielectric layer as the etch stop layer.

[0017] Optionally, the step of defining the logic region and removing the silicon nitride layer located at the logic region by dry etching to expose the polysilicon inter-dielectric layer includes:

[0018] The logic region is defined, and the silicon nitride dielectric layer is used as the etching stop layer. The silicon nitride layer located at the logic region is removed by dry etching, so that the silicon nitride dielectric layer of the polysilicon inter-dielectric layer is exposed.

[0019] Optionally, the step of removing the remaining polysilicon inter-dielectric layer located at the logic region location includes:

[0020] The remaining silicon nitride dielectric layer in the polysilicon inter-dielectric layer is removed by phosphoric acid cleaning.

[0021] Hydrofluoric acid cleaning was used to remove the lower oxide dielectric layer from the remaining polysilicon inter-dielectric layer.

[0022] Optionally, after the steps of defining the logic region and removing the silicon nitride layer located at the logic region location by dry etching to expose the polysilicon inter-dielectric layer are completed, before the step of removing the remaining polysilicon inter-dielectric layer located at the logic region location is performed, the NORD flash memory device logic region etching method further includes:

[0023] Acid stripping solution is used to remove the photoresist used to define the logic region. During the photoresist removal process, the acid stripping solution is used to remove the high-temperature oxide layer remaining at the location of the logic region.

[0024] Optionally, the step of etching away the floating gate polysilicon layer located in the logic region includes:

[0025] The floating gate polysilicon layer located in the logic region is removed by dry etching.

[0026] The technical solution of this application includes at least the following advantages: By sequentially growing a connecting oxide layer, a floating gate polysilicon layer, a polysilicon interlayer dielectric layer, and a control gate polysilicon layer on the substrate, the logic region is defined. The control gate polysilicon layer located in the logic region is etched away. A high-temperature oxide layer and a silicon nitride layer are sequentially deposited, covering the memory region and the logic region. The memory cells of the flash memory device are fabricated in the memory region. The logic region is defined. The silicon nitride layer located in the logic region is removed by dry etching, exposing the polysilicon interlayer dielectric layer. The remaining polysilicon interlayer dielectric layer located in the logic region is removed. The floating gate polysilicon layer in the logic region is removed by dry etching. This avoids the problem of over-etching the sidewalls of the memory region due to wet etching of the silicon nitride layer in the logic region, thus improving device performance. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0028] Figure 1 A flowchart of a NORD flash memory device logic area etching method according to an embodiment of this application is shown;

[0029] Figure 2a A schematic diagram of the cross-sectional structure of the substrate layer provided in step S11 is shown;

[0030] Figure 2b A schematic diagram of the cross-sectional structure of the device after step S12 is shown;

[0031] Figure 2c A partial structural schematic of the polysilicon inter-dielectric layer is shown;

[0032] Figure 2d A schematic diagram of the cross-sectional structure of the device after step S13 is shown;

[0033] Figure 2e A schematic diagram of the cross-sectional structure of the device after step S15 is shown;

[0034] Figure 2f A schematic diagram of the cross-sectional structure of the device after step S16 is shown;

[0035] Figure 2g A schematic diagram of the cross-sectional structure of the device after step S17 is shown;

[0036] Figure 2h A schematic diagram of the cross-sectional structure of the device after step S18 is shown;

[0037] Figure 3 A schematic diagram of the NORD flash memory device structure fabricated using related technologies is shown. Detailed Implementation

[0038] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0040] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0041] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0042] Figure 1 This application illustrates a flowchart of a NORD flash memory device logic region etching method according to an embodiment of the present application. Figure 1 As can be seen from this, the NORD flash memory device logic area etching method provided in this embodiment includes the following steps S11 to S18 executed sequentially, wherein:

[0043] Step S11: Provide a substrate layer, the substrate layer including a storage area and a logic area.

[0044] Reference Figure 2a It shows a schematic diagram of the cross-sectional structure of the substrate layer provided in step S11, from Figure 2a As can be seen, the substrate 210 includes a storage region 211 and a logic region 212. The storage region 211 can form the storage cell of the flash memory device after subsequent steps, and the logic region 212 can form the logic cell of the flash memory device after subsequent steps.

[0045] Step S12: A connecting oxide layer, a floating gate polysilicon layer, a polysilicon interlayer dielectric layer, and a control gate polysilicon layer are sequentially grown on the substrate.

[0046] Reference Figure 2b It shows a schematic cross-sectional view of the device after step S12 is completed, from Figure 2b As can be seen, after step S12 is completed, a connecting oxide layer 220, a floating gate polysilicon layer 230, a polysilicon inter-dielectric layer 240 and a control gate polysilicon layer 250 are sequentially grown on the substrate layer 210. The above layers sequentially cover the memory region 211 and the logic region 212.

[0047] Among them, reference Figure 2c It shows a partial structural schematic of the polysilicon inter-dielectric layer, from Figure 2c As can be seen, the polysilicon inter-dielectric layer 240 may include a lower oxide dielectric layer 241, a silicon nitride dielectric layer 242, and an upper oxide dielectric layer 243 stacked sequentially from bottom to top. When fabricating the polysilicon inter-dielectric layer 240, the lower oxide dielectric layer 241, silicon nitride dielectric layer 242, and upper oxide dielectric layer 243 can be sequentially deposited on the floating gate polysilicon layer 230.

[0048] Step S13: Define the logic region and etch away the control gate polysilicon layer in the logic region.

[0049] When defining the logic region in step S13, a first photoresist can be first coated on the control gate polysilicon layer 250 after step S12 is completed. Then, the first photoresist is exposed under the mask of the first mask to pattern the first photoresist. The patterned first photoresist is then developed to expose the control gate polysilicon layer 250 at the location of the logic region 212. The remaining first photoresist covers the control gate polysilicon layer 250 at the location of the memory region 211, thereby completing the definition of the logic region 212 pattern in step S13.

[0050] During the etching process in step S13 to remove the control gate polysilicon layer in the logic region, the control gate polysilicon layer 250 located in the logic region 212 can be etched away based on the logic region pattern defined by the above process, using the silicon nitride dielectric layer 242 of the inter-polysilicon dielectric layer 240 as the etch stop layer. It is understood that, to ensure the complete etching away of the control gate polysilicon layer 250, the silicon nitride dielectric layer 242 of the inter-polysilicon dielectric layer 240 is used as the etch stop layer during step S13. This causes the upper oxide dielectric layer 243 in the inter-polysilicon dielectric layer 240 to be etched away during the etching of the control gate polysilicon layer 250 in the logic region 212, exposing the silicon nitride dielectric layer 242 of the inter-polysilicon dielectric layer 240 in the logic region 212.

[0051] Reference Figure 2d It shows a schematic cross-sectional view of the device after step S13 is completed. Figure 2d As can be seen, after development, the remaining first photoresist 310 covers the control gate polysilicon layer 250 at the location of memory region 211, and the patterned first photoresist 310 defines the logic region 212 pattern. Based on the logic region 212 pattern, the control gate polysilicon layer 250 at the location of logic region 212 is completely etched away, and the silicon nitride dielectric layer 242 of the polysilicon inter-dielectric layer 240 in the logic region 212 is exposed.

[0052] After completing step S13, the first photoresist 310 is removed before proceeding to subsequent steps.

[0053] Step S14: Sequentially deposit a high-temperature oxide layer and a silicon nitride layer, wherein the high-temperature oxide layer and the silicon nitride layer cover the storage area and the logic area.

[0054] The step S14, which involves sequentially depositing a high-temperature oxide layer and a silicon nitride layer, is... Figure 2dBased on the device structure shown, the high-temperature oxide layer and silicon nitride layer deposited after step S14 are sequentially covered on the control gate polysilicon layer 250 at the storage region 211 and the exposed polysilicon inter-dielectric layer 240 at the logic region 212.

[0055] Step S15: Fabricate the storage cells of the flash memory device in the storage area.

[0056] Reference Figure 2e It shows a schematic cross-sectional view of the device after step S15 is completed. Figure 2e As can be seen, a memory cell for a flash memory device is formed at location 211 in this memory area.

[0057] Step S15 can be fabricated using conventional techniques. For example, the main steps for fabricating the memory cell of the flash memory device in the memory area include: first, etching the silicon nitride layer 260 and the high-temperature oxide layer 270 at the location of the memory area 211 to form a window in the silicon nitride layer 260 and the high-temperature oxide layer 270 at the location of the memory area 211; then forming sidewall structures 300 on both sides opposite the window; then etching the control gate polysilicon layer 250, the inter-polysilicon dielectric layer 240, and the floating gate polysilicon layer 230 at the location of the window layer to form a word line filling area; after forming a dielectric layer on the sidewall of the word line filling area, filling the word line filling area with polysilicon to form a word line structure 301, thereby completing the fabrication of the memory cell of the flash memory device.

[0058] After the process of fabricating the memory cells of the flash memory device in the memory area is completed, a protective silicon nitride layer 280 can be deposited. This protective silicon nitride layer 280 covers both the logic area 212 and the memory area 211, and also covers the exposed word line structure 301, forming a layer such as... Figure 2c The diagram shows a cross-sectional view of the device.

[0059] Step S16: Define the logic region, and remove the silicon nitride layer located at the logic region by dry etching, so that the polysilicon inter-dielectric layer is exposed.

[0060] When defining the logic region in step S16, a second photoresist can be first coated on the protective silicon nitride 280 after step S15. Then, the second photoresist is exposed under the mask of the second mask to pattern the second photoresist. The patterned second photoresist is then developed to expose the protective silicon nitride 280 at the location of the logic region 212. The remaining second photoresist covers the protective silicon nitride 280 at the location of the storage region 211, thereby completing the definition of the logic region 212 pattern in step S16.

[0061] When performing the process of removing the silicon nitride layer located at the logic region position by dry etching in step S16, the silicon nitride dielectric layer 242 of the polysilicon inter-dielectric layer 240 can be used as an etching stop layer based on the logic region pattern defined by the above process to etch away the protective silicon nitride 280 and silicon nitride layer 260 located at the logic region 212. It is understood that, in order to ensure that the silicon nitride layer is completely etched away, the silicon nitride dielectric layer 242 of the polysilicon inter-dielectric layer 240 is used as an etching stop layer during step S16, thereby ensuring that the high-temperature oxide layer 270 is also etched away during the etching of the silicon nitride layer at the logic region 212, exposing the silicon nitride dielectric layer 242 at the logic region 212.

[0062] Reference Figure 2f It shows a schematic cross-sectional view of the device after step S16 is completed. Figure 2f As can be seen, after development, the remaining second photoresist 320 covers the protective silicon nitride 280 at the location of storage region 211, and the patterned second photoresist 320 defines the logic region 212 pattern. Based on the logic region 212 pattern, with the silicon nitride dielectric layer 242 as the etch stop layer, the protective silicon nitride 280 and silicon nitride layer 260 at the location of logic region 212 are completely etched away, exposing the silicon nitride dielectric layer 242 of the polysilicon inter-dielectric layer 240 in the logic region 212.

[0063] Before proceeding with subsequent steps, an acid pickling solution can be used to remove the second photoresist 320 used to define the logic area pattern. During the photoresist removal process, the acid pickling solution will also remove the high-temperature oxide layer 270 remaining on the silicon nitride dielectric layer 242.

[0064] Step S17: Remove the remaining polysilicon inter-dielectric layer located in the logic region.

[0065] During step S17, a small amount of phosphoric acid can be used to clean and remove the silicon nitride dielectric layer 242 in the remaining polysilicon inter-dielectric layer 240 in the logic region 212, and a small amount of hydrofluoric acid can be used to clean and remove the lower oxide dielectric layer 241 in the remaining polysilicon inter-dielectric layer 240 in the logic region 212.

[0066] Reference Figure 2g It shows a schematic cross-sectional view of the device after step S17 is completed. Figure 2g As can be seen, the polysilicon inter-dielectric layer 240 located in the logic region 212 was removed by cleaning, and the upper surface of the floating gate polysilicon layer 230 at the location of the logic region 212 was exposed.

[0067] Step S18: Remove the floating gate polysilicon layer located in the logic region by dry etching.

[0068] Since only the upper surface of the floating gate polysilicon layer 230 located at the logic region 212 is exposed after step S17, while the surface including the storage region 211 is a silicon nitride layer, the floating gate polysilicon layer 230 in the logic region 212 can be dry etched away using the silicon nitride layer as a mask layer.

[0069] Reference Figure 2h It shows a schematic cross-sectional view of the device after step S18 is completed, from Figure 2h As can be seen, the floating gate polysilicon layer 230 at the logic region 212 is etched away, and the upper surface of the connecting oxide layer 220 at the logic region 212 is exposed.

[0070] This embodiment defines the logic region by sequentially growing a connecting oxide layer, a floating gate polysilicon layer, an inter-polysilicon dielectric layer, and a control gate polysilicon layer on the substrate. The control gate polysilicon layer located within the logic region is etched away. A high-temperature oxide layer and a silicon nitride layer are then sequentially deposited, covering the memory region and the logic region. The memory cells of the flash memory device are fabricated within the memory region. The logic region is then defined, and the silicon nitride layer located within the logic region is removed using dry etching, exposing the inter-polysilicon dielectric layer. The remaining inter-polysilicon dielectric layer located within the logic region is removed, and the floating gate polysilicon layer within the logic region is removed using dry etching. This avoids the problem of over-etching the sidewalls of the memory region due to wet etching of the silicon nitride layer in the logic region, thus improving device performance.

[0071] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for etching the logic region of a NORD flash memory device, characterized in that, The NORD flash memory device logic area etching method comprises the following steps in sequence: providing a substrate layer comprising a storage area and a logic area; forming a connection oxide layer, a floating gate polysilicon layer, a polysilicon interlayer and a control gate polysilicon layer in sequence on the substrate layer, the polysilicon interlayer comprising a lower oxide dielectric layer, a silicon nitride dielectric layer and an upper oxide dielectric layer deposited in sequence from bottom to top; defining the logic area and etching away the control gate polysilicon layer at the position of the logic area; depositing a high-temperature oxide layer and a silicon nitride layer in sequence, the high-temperature oxide layer and the silicon nitride layer covering the storage area and the logic area; making a storage unit of the flash memory device in the storage area; defining the logic area, taking the silicon nitride dielectric layer as an etching stop layer, and etching away the silicon nitride layer at the position of the logic area by dry etching so that the silicon nitride dielectric layer of the polysilicon interlayer is exposed; removing the remaining polysilicon interlayer at the position of the logic area; etching away the floating gate polysilicon layer in the logic area.

2. The method of claim 1, wherein the NORD flash device logic area etch is characterized by: The step of defining the logic area and etching away the control gate polysilicon layer in the logic area comprises: defining the logic area and etching away the control gate polysilicon layer in the logic area by taking the silicon nitride dielectric layer as an etching stop layer.

3. The method of claim 1, wherein the NORD flash device logic area etch is characterized by, The step of removing the remaining polysilicon interlayer at the position of the logic area comprises: using phosphoric acid cleaning to remove the silicon nitride dielectric layer in the remaining polysilicon interlayer; using hydrofluoric acid cleaning to remove the lower oxide dielectric layer in the remaining polysilicon interlayer.

4. The method of claim 1, wherein the NORD flash device logic area etch is characterized by, After the step of defining the logic area and etching away the silicon nitride layer at the position of the logic area by dry etching so that the polysilicon interlayer is exposed is completed, before the step of removing the remaining polysilicon interlayer at the position of the logic area is performed, the NORD flash memory device logic area etching method further comprises: using an acid cleaning solution to remove the photoresist used to define the logic area, and in the photoresist removing process, the high-temperature oxide layer remaining at the position of the logic area is removed by the acid cleaning solution.

5. The method of claim 1, wherein the NORD flash device logic area etch is characterized by, The step of etching away the floating gate polysilicon layer in the logic area comprises: etching away the floating gate polysilicon layer in the logic area by dry etching.

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