Semiconductor structure and preparation method thereof

Abstract

The present invention relates to the field of semiconductors, and in particular to a semiconductor structure and a method for preparing the same. The method for preparing the semiconductor structure provided by the present invention comprises the following steps: providing a first-type substrate, the first-type substrate comprising a first sub-substrate, a buried oxide layer, and a second sub-substrate stacked in sequence; performing back doping on the first sub-substrate to form a second-type deep injection region, and forming a second-type heavily doped region on one side of the second-type deep injection region; forming a transistor device and a dielectric layer on the surface of the second sub-substrate, the transistor device comprising a first-type epitaxial layer formed on the surface of the second sub-substrate, a second-type well region formed in the first-type epitaxial layer, and a dielectric layer formed on the surface of the first-type epitaxial layer; etching the dielectric layer, the first-type epitaxial layer, the second sub-substrate, and the buried oxide layer to form a second deep trench located outside the second-type well region, the bottom of the second deep trench exposing the second-type heavily doped region; and forming a first conductive column in the second deep trench. The above technical solution can enhance the device's resistance to ionizing radiation.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] With the advancement of space technology, the demand for higher levels of integration in electronic systems is increasing, but this also requires devices to be radiation-hardened. In the field of complementary metal-oxide semiconductor (CMOS), silicon-on-insulator (SOI) devices have been widely studied due to their excellent radiation resistance. However, there are relatively few reports on the radiation resistance of SOI-based smart power integrated circuits (Smart Power ICs), which can simultaneously integrate bipolar, CMOS, and laterally diffused metal-oxide semiconductor (LDMOS).

[0003] Therefore, how to improve the total ionizing dose (TID) protection capability of SOI devices and enhance the reliability of chips in harsh environments is a problem that needs to be solved at present. Summary of the Invention

[0004] The technical problem to be solved by the present invention is how to improve the total ionizing dose (TID) protection capability of SOI devices and enhance the reliability of chips in harsh environments, and provide a semiconductor structure and a preparation method thereof.

[0005] In order to solve the above problems, the present invention provides a method for preparing a semiconductor structure, comprising the following steps: providing a first-type substrate, the first-type substrate comprising a first sub-substrate, a buried oxide layer and a second sub-substrate stacked in sequence; performing back-doping on the first sub-substrate to form a second-type deep injection region, and forming a second-type heavily doped region on one side of the second-type deep injection region; forming a transistor device and a dielectric layer on the surface of the second sub-substrate, the transistor device comprising a first-type epitaxial layer formed on the surface of the second sub-substrate, a second-type well region formed in the first-type epitaxial layer, and the dielectric layer formed on the surface of the first-type epitaxial layer; etching the dielectric layer, the first-type epitaxial layer, the second sub-substrate and the buried oxide layer to form a second deep trench located outside the second-type well region, and the bottom of the second deep trench exposes the second-type heavily doped region; forming a first conductive column in the second deep trench.

[0006] In some embodiments, the first type is P-type and the second type is N-type.

[0007] In some embodiments, the transistor device also includes a drain formed on the surface of the second-type well region, a first-type body region formed in the first-type epitaxial layer and spaced apart from the second-type well region, a source and a transistor substrate formed on the surface of the first-type body region, a gate formed between the source and the drain, a first deep trench isolation structure that passes through the first-type epitaxial layer and the second sub-substrate and contacts the buried oxide layer, and the first deep trench isolation structure is located outside the second-type well region; wherein, the first conductive column is located outside the first deep trench isolation structure.

[0008] In some embodiments, the step of forming a transistor device on the surface of the second sub-substrate specifically includes: forming the first type epitaxial layer on the surface of the second sub-substrate; performing ion implantation on the first type epitaxial layer to form two second type deep well regions spaced apart, and performing ion implantation on the second type deep well region to form the second type well region; etching the first type epitaxial layer and the second sub-substrate to form two first deep trenches spaced apart, the bottom of the first deep trench exposing the buried oxide layer, and the first deep trench being located outside the second type deep well region; forming the first deep trench isolation structure in the first deep trench; forming the first type body region in the first type epitaxial layer between the two second type deep well regions; heavily doping the surface of the first type body region to form the source and the transistor substrate, and heavily doping the surface of the second type well region to form the drain; forming a gate between the source and the drain to form the transistor device.

[0009] In some embodiments, before the step of ion implanting the first type epitaxial layer to form two spaced-apart second type deep well regions, the step also includes: forming two shallow trench isolation structures on the surface of the first type epitaxial layer to define the active area; the step of etching the first type epitaxial layer and the second sub-substrate to form two spaced-apart first deep trenches also includes: etching along the position of the shallow trench isolation structure to form the first deep trench, and the two shallow trench isolation structures are removed.

[0010] In some embodiments, the step of etching the first type epitaxial layer and the second sub-substrate to form two first deep trenches spaced apart from each other further includes: performing first type ion implantation with an inclined angle on the sidewalls of the first deep trench to form a first type doped region in the first type epitaxial layer and the second sub-substrate on the sidewalls of the first deep trench.

[0011] In some embodiments, the step of etching the dielectric layer, the first type epitaxial layer, the second sub-substrate and the buried oxide layer to form a second deep trench located outside the second type well region also includes: simultaneously etching the dielectric layer above the transistor device to form multiple third deep trenches, and the bottoms of the multiple third deep trenches respectively expose the transistor substrate surface, the drain surface, the source surface, and the gate surface of the transistor device; the step of forming a first conductive column in the second deep trench also includes: simultaneously forming a second conductive column in all the third deep trenches, and the multiple second conductive columns are respectively electrically connected to the transistor substrate, the drain, the source and the gate of the transistor device.

[0012] In some embodiments, the first conductive pillar is a tungsten plug.

[0013] In order to solve the above problems, the present invention provides a semiconductor structure, comprising: a first-type substrate, the first-type substrate comprising a first sub-substrate, a buried oxide layer and a second sub-substrate stacked in sequence; a second-type deep injection region formed in the first sub-substrate, and a second-type heavily doped region formed on one side of the second-type deep injection region; a transistor device formed on the surface of the second sub-substrate, the transistor device comprising a first-type epitaxial layer formed on the surface of the second sub-substrate, and a second-type well region formed in the first-type epitaxial layer; a dielectric layer formed on the surface of the first-type epitaxial layer; and a first conductive column penetrating the dielectric layer, the first-type epitaxial layer, the second sub-substrate and the buried oxide layer, and electrically connected to the second-type heavily doped region at the bottom.

[0014] In some embodiments, the transistor device also includes a drain formed on the surface of the second-type well region, a first-type body region formed in the first-type epitaxial layer and spaced apart from the second-type well region, a source and a transistor substrate formed on the surface of the first-type body region, a gate formed between the source and the drain, a first deep trench isolation structure that passes through the first-type epitaxial layer and the second sub-substrate and contacts the buried oxide layer, and the first deep trench isolation structure is located outside the second-type well region; wherein, the first conductive column is located outside the first deep trench isolation structure.

[0015] In some embodiments, a plurality of second conductive pillars are further included, formed in the dielectric layer, and the plurality of second conductive pillars are electrically connected to the transistor substrate, the source, the drain, and the gate of the transistor device, respectively.

[0016] This technical solution forms a first conductive pillar in the first-type substrate, extending through the buried oxide layer and electrically connecting it to the second-type heavily doped region beneath the buried oxide layer. This leads the first-type substrate out from beneath the buried oxide layer. Charge generated by ionizing radiation can be smoothly conducted through the first conductive pillar, preventing charge accumulation in the buried oxide layer and fundamentally eliminating the unintended inversion layer phenomenon caused by charging of the oxide layer due to the Bragg effect. This invention opens up a new approach to improving the reliability and stability of electronic devices based on SOI substrates in ionizing radiation environments. It is expected to play a key role in high-radiation applications such as aerospace and the nuclear industry, significantly improving the radiation resistance of related electronic systems and extending their operating life. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for describing the specific embodiments. Obviously, the drawings described below are only some specific embodiments of the present invention. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0018] Figure 1 The figure is a flow chart of the steps of an embodiment of the method for preparing a semiconductor structure according to the present invention.

[0019] Figure 2 This is a process structure diagram of a first type substrate provided in one embodiment of the present invention.

[0020] Figure 3 This is a process structure diagram after forming the second type deep implantation region according to one embodiment of the present invention.

[0021] Figure 4 This is a process structure diagram after forming the second-type well region according to one embodiment of the present invention.

[0022] Figure 5 This is a process structure diagram after forming the first deep trench according to an embodiment of the present invention.

[0023] Figure 6 This is a process structure diagram after forming a transistor device according to an embodiment of the present invention.

[0024] Figure 7 This is a process structure diagram after forming the second deep trench according to an embodiment of the present invention.

[0025] Figure 8 FIG. 1 is a structural diagram of a process after forming a first conductive pillar according to an embodiment of the present invention.

[0026] Description of Reference Numerals

[0027] 21. First type substrate;

[0028] 210. First sub-substrate;

[0029] 211, buried oxygen layer;

[0030] 212. Second sub-substrate;

[0031] 213, Type II deep injection region;

[0032] 214, Type II heavily doped region;

[0033] 22. Type I epitaxial layer;

[0034] 221, second type well region;

[0035] 222, first type body area;

[0036] 223, Type II deep well region;

[0037] 220. Shallow trench isolation structure;

[0038] 500, mask layer;

[0039] 23. Dielectric layer;

[0040] 240, first deep trench;

[0041] 241, first type doped region;

[0042] 24. A first deep trench isolation structure;

[0043] 251, drain;

[0044] 252, source;

[0045] 253. Transistor substrate;

[0046] 254, gate;

[0047] 255,LOCOS;

[0048] 260, second deep groove;

[0049] 270, the third deep groove;

[0050] 26. a first conductive column;

[0051] 27. A second conductive column. DETAILED DESCRIPTION

[0052] The following is a clear and complete description of the technical solutions in the embodiments of the present invention, with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present invention.

[0053] To improve the total ionizing dose (TID) protection capability of SOI devices and enhance the reliability of chips in harsh environments, the present invention is based on the expansion of deep trench isolation technology. A deep trench is fabricated through the buried oxide layer in the silicon-on-insulator (SOI) substrate, and the substrate is led out through a tungsten plug (Tungsten Plug In) to prevent the appearance of an unexpected inversion layer caused by the Bragg effect when ionizing radiation charges the oxide layer.

[0054] See also Figure 1 , which is a flow chart of steps of an embodiment of the method for preparing the semiconductor structure of the present invention. Figure 1 As shown, the preparation method of the semiconductor structure includes the following steps: step S11, providing a first type substrate, the first type substrate including a first sub-substrate, a buried oxide layer and a second sub-substrate stacked in sequence; step S12, back-doping the first sub-substrate to form a second type deep injection region, and a second type heavily doped region is formed on one side of the second type deep injection region; step S13, forming a transistor device and a dielectric layer on the surface of the second sub-substrate, the transistor device including a first type epitaxial layer formed on the surface of the second sub-substrate, a second type well region formed in the first type epitaxial layer, and the dielectric layer formed on the surface of the first type epitaxial layer; step S14, etching the dielectric layer, the first type epitaxial layer, the second sub-substrate and the buried oxide layer to form a second deep trench located outside the second type well region, and the bottom of the second deep trench exposes the second type heavily doped region; step S15, forming a first conductive column in the second deep trench.

[0055] See also Figures 2 to 8 ,in, Figure 2 A process structure diagram of a first type substrate provided in one embodiment of the present invention; Figure 3 This is a process structure diagram after forming the second type deep implantation region according to one embodiment of the present invention; Figure 4 This is a process structure diagram after forming the second-type well region according to one embodiment of the present invention; Figure 5 This is a process structure diagram after forming the first deep trench according to an embodiment of the present invention; Figure 6 A diagram showing a process structure after forming a transistor device according to an embodiment of the present invention; Figure 7 This is a process structure diagram after forming the second deep trench according to an embodiment of the present invention; Figure 8FIG. 1 is a structural diagram of a process after forming a first conductive pillar according to an embodiment of the present invention.

[0056] See also Figure 2 And step S11 , providing a first type substrate 21 , wherein the first type substrate 21 includes a first sub-substrate 210 , a buried oxide layer 211 and a second sub-substrate 212 stacked in sequence.

[0057] In some embodiments, the first type is a P-type. In this embodiment, the first type substrate 21 is a P-type silicon-on-insulator (SOI) substrate.

[0058] See also Figure 3 And step S12 , performing ion implantation on the first sub-substrate 210 to form a second type deep implantation region 213 , and forming a second type heavily doped region 214 on one side of the second type deep implantation region 213 .

[0059] In some embodiments, the second type is N-type. In this embodiment, the second type deep implantation region 213 is an N-type deep implantation region, and the second type heavily doped region 214 is an N-type heavily doped region.

[0060] In the step of back-doping the first sub-substrate 210 to form a second-type deep injection region 213, a specific type of ions is introduced into a specific area of ​​the first sub-substrate 210 through a back-doping process to change the electrical properties of the area, thereby adjusting the conductive properties of the first-type substrate 21, laying the foundation for subsequent device performance optimization.

[0061] See also Figures 4 to 6 And step S13, forming a transistor device and a dielectric layer 23 on the surface of the second sub-substrate 212, the transistor device includes a first type epitaxial layer 22 formed on the surface of the second sub-substrate 212, a second type well region 221 formed in the first type epitaxial layer 22, and the dielectric layer 23 is formed on the surface of the first type epitaxial layer 22.

[0062] like Figure 6 As shown, in some embodiments, the transistor device further includes a drain 251 formed on the surface of the second-type well region 221, a first-type body region 222 formed in the first-type epitaxial layer 22 and spaced apart from the second-type well region 221, a source 252 and a transistor substrate 253 formed on the surface of the first-type body region 222, a gate 254 formed between the source 252 and the drain 251, a first deep trench isolation structure 24 penetrating the first-type epitaxial layer 22 and the second sub-substrate 212 and in contact with the buried oxide layer 211, and the first deep trench isolation structure 24 is located outside the second-type well region 221; wherein the first conductive pillar 26 (see Figure 8) is located outside the first deep trench isolation structure 24.

[0063] Specifically, see Figures 4 to 6 In some embodiments, the step of forming a transistor device on the surface of the second sub-substrate 212 specifically includes:

[0064] like Figure 4 As shown, the first type epitaxial layer 22 is formed on the surface of the second sub-substrate 212; ion implantation is performed on the first type epitaxial layer 22 to form two second type deep well regions 223 spaced apart, and ion implantation is performed on the second type deep well regions 223 to form the second type well region 221.

[0065] In some embodiments, before the step of performing ion implantation on the first type epitaxial layer 22 to form two spaced-apart second type deep well regions 223, the step further includes: forming two spaced-apart shallow trench isolation structures 220 on the surface of the first type epitaxial layer 22 to define an active area. The step of performing ion implantation on the first type epitaxial layer 22 to form two spaced-apart second type deep well regions 223 specifically includes: performing ion implantation in the active area to form two spaced-apart second type deep well regions 223.

[0066] In some embodiments, after ion implanting the first-type epitaxial layer 22 to form the second-type deep well region 223 and ion implanting the second-type deep well region 223 to form the second-type well region 221, a rapid thermal annealing (RTA) process is also included. The rapid thermal annealing process utilizes rapid heating equipment (such as a rapid thermal annealing furnace) to heat the material to a high temperature (typically between several hundred degrees Celsius and over a thousand degrees Celsius) within a short period of time, followed by rapid cooling. Through this rapid heating and cooling process, the implanted dopant ions are activated and diffused to appropriate locations, repairing lattice damage caused by the ion implantation, optimizing the distribution of the dopant ions, and improving the electrical properties of the semiconductor material.

[0067] like Figure 5 As shown, the first-type epitaxial layer 22 and the second sub-substrate 212 are etched to form two first deep trenches 240 spaced apart from each other. The bottoms of the first deep trenches 240 expose the buried oxide layer 211, and the first deep trenches 240 are located outside the second-type deep well region 223. Specifically, a mask layer 500 is formed and patterned on the surface of the first-type epitaxial layer 22. The patterned mask layer 500 is used as a mask to etch the first-type epitaxial layer 22 and the second sub-substrate 212 to form the two first deep trenches 240 spaced apart from each other.

[0068] In some embodiments, the step of etching the first epitaxial layer 22 and the second sub-substrate 212 to form two first deep trenches 240 spaced apart from each other further includes etching along the locations of the shallow trench isolation structures 220 to form the first deep trenches 240, and then removing the two shallow trench isolation structures 220. In other embodiments, the width of the first deep trenches 240 is smaller than that of the shallow trench isolation structures 220, so that residues remain on both sides of the shallow trench isolation structures 220.

[0069] In some embodiments, after the step of etching the first type epitaxial layer 22 and the second sub-substrate 212 to form two first deep trenches 240 spaced apart, the step also includes: performing first type ion implantation with an inclined angle on the sidewalls of the first deep trench 240 to form first type doped regions 241 on the sidewalls of the first deep trench 240 in the first type epitaxial layer 22 and the second sub-substrate 212.

[0070] The first type doping region 241 is implanted with heavy ions, forming only a very thin doping region at the interface. When performing ion implantation to form the first type doping region 241, care should be taken to prevent ions from diffusing too far. Concentrating them at the interface can achieve a better effect in preventing inversion.

[0071] The doping concentration of the first-type doping region 241 is close to the doping concentration of the well region and is lower than the doping concentration of the heavily doped region.

[0072] P-type ions are implanted into the sidewalls of the first deep trench 240 to further adjust the electrical properties of the sidewalls of the first deep trench 240 , which may be used to improve isolation performance, prevent sidewall leakage, or achieve specific electrical functions, thereby reducing leakage and crosstalk.

[0073] After completing the above steps, the process further includes removing the mask layer 500 .

[0074] like Figure 6 As shown, a first deep trench isolation structure 24 is formed in the first deep trench 240 .

[0075] In some embodiments, the first deep trench isolation structure 24 is made of TEOS and is used to achieve electrical isolation between different devices or regions, prevent signal interference and leakage, and improve device integration and performance.

[0076] It is worth noting that in this embodiment, since the first type ion implantation with an inclined angle is performed on the sidewall of the first deep trench 240 in the aforementioned process, a first type doping region 241 is formed at the interface between the first deep trench isolation structure 24 and the first type epitaxial layer 22 and the second sub-substrate 212. Under normal circumstances, due to the material characteristics of the first deep trench isolation structure 24, it will be positively charged after being ionized by radiation, thereby causing the silicon at the interface to be inverted, thereby forming a conductive channel, affecting the performance of the device. Therefore, the presence of the first type doping region 241 increases the P-type doping concentration at the interface between the first type epitaxial layer 22 and the second sub-substrate 212, making it difficult for the silicon at the interface to be inverted, avoiding the formation of a conductive channel at the interface, and thus improving the device's resistance to ionizing radiation.

[0077] Please continue reading Figure 6 , forming the first type body region 222 in the first type epitaxial layer 22 between the two second type well regions 221; heavily doping the surface of the first type body region 222 to form the source 252 and the transistor substrate 253, and heavily doping the surface of the second type well region 221 to form the drain 251; forming a gate 254 between the source 252 and the drain 251 to form the transistor device.

[0078] In this embodiment, the drain 251 and the source 252 are both N-type heavily doped regions, and the transistor substrate 253 is a P-type heavily doped region.

[0079] In this embodiment, the transistor device includes two LDMOS devices, and the two LDMOS devices share a first-type body region 222. The first-type body region 222 includes a transistor substrate 253 and two source electrodes 252 located on either side of the transistor substrate 253. The drain electrodes 251 are respectively formed on the surfaces of the two second-type well regions 221.

[0080] In this embodiment, before forming the gate 254 , a step of forming a LOCOS 255 on the surface of the second-type deep well region 223 is further included.

[0081] Please continue reading Figure 6 After forming the transistor device, the dielectric layer 23 is formed on the surface of the first-type epitaxial layer 22 .

[0082] See also Figure 7And step S14, etching the dielectric layer 23, the first-type epitaxial layer 22, the second sub-substrate 212, and the buried oxide layer 211 to form a second deep trench 260 located outside the second-type well region 221, with the bottom of the second deep trench 260 exposing the second-type heavily doped region 214. The second deep trench 260 is located outside the first deep trench isolation structure 24.

[0083] In some embodiments, the step of etching the dielectric layer 23, the first type epitaxial layer, the second sub-substrate 212 and the buried oxide layer 211 to form a second deep trench 260 located outside the second type well region 221 also includes: simultaneously etching the dielectric layer 23 above the transistor device to form a plurality of third deep trenches 270, the bottoms of the plurality of third deep trenches 270 respectively exposing the surface of the transistor substrate 253, the surface of the drain 251, the surface of the source 252, and the surface of the gate 254 of the transistor device.

[0084] See also Figure 8 And step S15, forming a first conductive pillar 26 in the second deep trench 260, wherein the first conductive pillar 26 is electrically connected to the second-type heavily doped region 214. The first conductive pillar 26 is located outside the first deep trench isolation structure 24.

[0085] In some embodiments, the step of forming the first conductive pillar 26 in the second deep trench 260 also includes: simultaneously forming a second conductive pillar 27 in all the third deep trenches 270, and the plurality of second conductive pillars 27 are respectively electrically connected to the transistor substrate 253, the drain 251, the source 252 and the gate 254 of the transistor device.

[0086] In some embodiments, the first conductive pillar 26 is a tungsten plug. In this embodiment, the second conductive pillar 27 is also made of metallic tungsten. Using methods such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), metallic tungsten is simultaneously deposited within the second deep trench 260 and all of the third deep trenches 270 to form the first conductive pillar 26 and multiple second conductive pillars 27. The first conductive pillar 26 serves as an effective charge removal path from the first substrate 21, preventing the buried oxide layer 211 from charging and causing an inversion layer to form, thereby improving the reliability and stability of the device in ionizing radiation environments. During use, a bias voltage is applied to the first conductive pillar 26 to prevent the formation of an inversion layer on the first substrate 21.

[0087] In conventional silicon-on-insulator (SiO) substrate structures, the buried oxide layer provides a certain degree of isolation, but it can present a significant challenge when exposed to high-intensity ionizing radiation due to the Bragg effect. As ionizing radiation particles penetrate material, the Bragg effect deposits a significant amount of energy at specific locations. This makes the buried oxide layer a key area for energy accumulation in SiO substrates. As energy accumulates, the buried oxide layer charges, leading to an unintended inversion layer. Once this unintended inversion layer appears, it can severely disrupt the device's normal electrical signal transmission, causing unstable performance or even failure.

[0088] The above technical solution forms a first conductive pillar in the first-type substrate, extending through the buried oxide layer and electrically connecting it to the second-type heavily doped region beneath the buried oxide layer. This leads the first-type substrate out from beneath the buried oxide layer. Charge generated by ionizing radiation can be smoothly conducted through the first conductive pillar, preventing charge accumulation in the buried oxide layer. This fundamentally eliminates the unintended inversion layer phenomenon caused by the Bragg effect-induced charging of the oxide layer, thereby enhancing the device's resistance to ionizing radiation. This invention opens up a new approach to improving the reliability and stability of electronic devices based on SOI substrates in ionizing radiation environments. It is expected to play a key role in high-radiation applications such as aerospace and the nuclear industry, significantly improving the radiation resistance of related electronic systems and extending their operating life.

[0089] Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor structure.

[0090] See also Figure 8 The semiconductor structure of the present invention is fabricated using the method for fabricating a semiconductor structure of the present invention and includes: a first-type substrate 21, a second-type deep implant region 213, a transistor device, and a first conductive pillar 26. The first-type substrate 21 includes a first sub-substrate 210, a buried oxide layer 211, and a second sub-substrate 212 stacked in sequence. The second-type deep implant region 213 is formed in the first sub-substrate 210, and a second-type heavily doped region 214 is formed on one side of the second-type deep implant region 213. The transistor device is formed on the surface of the second sub-substrate 212 and includes a first-type epitaxial layer 22 formed on the surface of the second sub-substrate 212, a second-type well region 221 formed within the first-type epitaxial layer 22, and a dielectric layer 23 formed on the surface of the first-type epitaxial layer 22. The first conductive pillar 26 penetrates the dielectric layer 23, the first-type epitaxial layer 22, the second sub-substrate 212, and the buried oxide layer 211, and is electrically connected at its bottom to the second-type heavily doped region 214.

[0091] The above technical solution forms the first conductive pillar in the first type substrate, passing through the buried oxide layer, and electrically connects it to the second type heavily doped region below the buried oxide layer, thereby leading out the first type substrate below the buried oxide layer. The charge generated by ionizing radiation can be smoothly conducted out through the first conductive pillar, thus avoiding the accumulation of charge in the buried oxide layer and fundamentally eliminating the accidental inversion layer phenomenon caused by the charging of the oxide layer due to the Bragg effect. During use, a bias voltage is applied to the first conductive pillar to avoid the formation of an inversion layer in the first type substrate, thereby enhancing the device's resistance to ionizing radiation. The present invention opens up a new way to improve the reliability and stability of electronic devices based on SOI substrates in ionizing radiation environments, and is expected to play a key role in high-radiation application fields such as aerospace and nuclear industry, significantly improving the radiation resistance of related electronic systems and extending their service life.

[0092] In some embodiments, the transistor device also includes a drain 251 formed on the surface of the second-type well region 221, a first-type body region 222 formed in the first-type epitaxial layer 22 and spaced apart from the second-type well region 221, a source 252 and a transistor substrate 253 formed on the surface of the first-type body region 222, a gate 254 formed between the source 252 and the drain 251, a first deep trench isolation structure 24 that penetrates the first-type epitaxial layer 22 and the second sub-substrate 212 and contacts the buried oxide layer 211, and the first deep trench isolation structure 24 is located outside the second-type well region 221; wherein, the first conductive column 26 is located outside the first deep trench isolation structure 24.

[0093] In this embodiment, the drain 251 and the source 252 are both N-type heavily doped regions, and the transistor substrate 253 is a P-type heavily doped region.

[0094] In this embodiment, the transistor device includes two LDMOS devices, and the two LDMOS devices share a first-type body region 222. The first-type body region 222 includes a transistor substrate 253 and two source electrodes 252 located on either side of the transistor substrate 253. The drain electrodes 251 are respectively formed on the surfaces of the two second-type well regions 221.

[0095] In this embodiment, the semiconductor structure further includes a LOCOS 255 formed on the surface of the second-type deep well region 223 .

[0096] In some embodiments, a plurality of second conductive pillars 27 are further included, formed in the dielectric layer 23 , and the plurality of second conductive pillars 27 are electrically connected to the transistor substrate 253 , the drain 251 , the source 252 and the gate 254 of the transistor device, respectively.

[0097] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0098] Typically, a term can be understood at least in part from its usage in the context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a feature, structure or combination of features in a plural sense. Similarly, depending at least in part on the context, terms such as "one", "a" or "the" can also be understood to express singular usage or to express plural usage. In addition, the term "based on" can be understood as not necessarily intended to express an exclusive set of factors, but can alternatively, also depending at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connected / coupled" refers not only to the direct coupling of one component to another component, but also to the indirect coupling of one component to another component through an intermediate component.

[0099] It should be noted that the terms "including" and "having" and their variations involved in the documents of the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies has been omitted to avoid unnecessary confusion of the concepts of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0100] The above description is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises the following steps: providing a first-type substrate, wherein the first-type substrate comprises a first sub-substrate, a buried oxide layer and a second sub-substrate stacked in sequence; performing back doping on the first sub-substrate to form a second-type deep injection region, and forming a second-type heavily doped region on one side of the second-type deep injection region; forming a transistor device and a dielectric layer on the surface of the second sub-substrate, wherein the transistor device comprises a first-type epitaxial layer formed on the surface of the second sub-substrate, a second-type well region formed in the first-type epitaxial layer, and the dielectric layer is formed on the surface of the first-type epitaxial layer; etching the dielectric layer, the first-type epitaxial layer, the second sub-substrate and the buried oxide layer to form a second well region located outside the second-type well region. A deep trench is formed, and the bottom of the second deep trench exposes the second-type heavily doped region; a first conductive pillar is formed in the second deep trench; the transistor device also includes a drain formed on the surface of the second-type well region, a first-type body region formed in the first-type epitaxial layer and spaced apart from the second-type well region, a source and a transistor substrate formed on the surface of the first-type body region, a gate formed between the source and the drain, a first deep trench isolation structure that penetrates the first-type epitaxial layer and the second sub-substrate and contacts the buried oxide layer, and the first deep trench isolation structure is located outside the second-type well region, wherein the first conductive pillar is located outside the first deep trench isolation structure.

2. The preparation method according to claim 1, characterized in that The first type is P type, and the second type is N type.

3. The preparation method according to claim 1, characterized in that The steps of forming a transistor device on the surface of the second sub-substrate specifically include: forming the first-type epitaxial layer on the surface of the second sub-substrate; performing ion implantation on the first-type epitaxial layer to form two second-type deep well regions spaced apart, and performing ion implantation on the second-type deep well region to form the second-type well region; etching the first-type epitaxial layer and the second sub-substrate to form two first deep trenches spaced apart, the bottom of the first deep trench exposing the buried oxide layer, and the first deep trench being located outside the second-type deep well region; forming the first deep trench isolation structure in the first deep trench; forming the first-type body region in the first-type epitaxial layer between the two second-type deep well regions; heavily doping the surface of the first-type body region to form the source and the transistor substrate, and heavily doping the surface of the second-type well region to form the drain; forming a gate between the source and the drain to form the transistor device.

4. The preparation method according to claim 3, characterized in that Before the step of ion implanting the first type epitaxial layer to form two spaced second type deep well regions, the step also includes: forming two shallow trench isolation structures on the surface of the first type epitaxial layer to define the active area; the step of etching the first type epitaxial layer and the second sub-substrate to form two spaced first deep trenches also includes: etching along the position of the shallow trench isolation structure to form the first deep trench, and the two shallow trench isolation structures are removed.

5. The preparation method according to claim 3, characterized in that After the step of etching the first type epitaxial layer and the second sub-substrate to form two first deep trenches spaced apart, the step also includes: performing first type ion implantation with an inclined angle on the sidewalls of the first deep trench to form first type doped regions in the first type epitaxial layer and the second sub-substrate on the sidewalls of the first deep trench.

6. The preparation method according to claim 1, characterized in that The step of etching the dielectric layer, the first-type epitaxial layer, the second sub-substrate and the buried oxide layer to form a second deep trench located outside the second-type well region also includes: simultaneously etching the dielectric layer above the transistor device to form multiple third deep trenches, the bottoms of the multiple third deep trenches respectively exposing the transistor substrate surface, the drain surface, the source surface, and the gate surface of the transistor device; the step of forming a first conductive pillar in the second deep trench also includes: simultaneously forming a second conductive pillar in all the third deep trenches, and the multiple second conductive pillars are respectively electrically connected to the transistor substrate, the drain, the source and the gate of the transistor device.

7. The preparation method according to claim 1, characterized in that The first conductive column is a tungsten plug.

8. A semiconductor structure, characterized in that include: A first type substrate, wherein the first type substrate comprises a first sub-substrate, a buried oxide layer, and a second sub-substrate stacked in sequence; A second-type deep implant region is formed in the first sub-substrate, and a second-type heavily doped region is formed on one side of the second-type deep implant region; a transistor device is formed on the surface of the second sub-substrate, the transistor device comprising a first-type epitaxial layer formed on the surface of the second sub-substrate, a second-type well region formed in the first-type epitaxial layer; a dielectric layer is formed on the surface of the first-type epitaxial layer; and a first conductive pillar penetrates the dielectric layer, the first-type epitaxial layer, the second sub-substrate and the buried oxide layer, and the bottom of the first conductive pillar is electrically connected to the second-type heavily doped region; the transistor device also includes a drain formed on the surface of the second-type well region, a first-type body region formed in the first-type epitaxial layer and spaced apart from the second-type well region, a source and a transistor substrate formed on the surface of the first-type body region, a gate formed between the source and the drain, and a first deep trench isolation structure penetrates the first-type epitaxial layer and the second sub-substrate and contacts the buried oxide layer, and the first deep trench isolation structure is located outside the second-type well region, wherein the first conductive pillar is located outside the first deep trench isolation structure.

9. The semiconductor structure according to claim 8, wherein: It also includes a plurality of second conductive pillars formed in the dielectric layer, and the plurality of second conductive pillars are respectively electrically connected to the transistor substrate, the source, the drain and the gate of the transistor device.

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