Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a channel structure; a gate structure on the channel structure; a first source / drain region on the channel structure; a substrate layer under the gate structure; a first etch stop layer under the substrate layer; a backside spacer on side surfaces of the substrate layer and the first etch stop layer; and a backside contact structure on a bottom surface of the first source / drain region and a side surface of the backside spacer.

Description

Technical Field

[0001] Apparatus and methods related to the present disclosure relate to a semiconductor device in which a backside contact structure is formed in a self-aligned manner. Background Art

[0002] Backside power distribution network (BSPDN) for semiconductor devices has been introduced to address the heavy traffic of signal lines at the front side of semiconductor devices. BSPDN includes connection structures formed on the back side of semiconductor devices. Here, the front side refers to the side where transistors are formed with respect to the top surface of the substrate, and the back side refers to the side opposite to the front side.

[0003] A BSPDN formed on the back side of a semiconductor device includes a backside contact structure connected to the bottom surface of the source / drain region of a field effect transistor, such as a nanosheet transistor or a fin field effect transistor (FinFET). The backside contact structure connects the source / drain region to a voltage source or another circuit element for signal routing through a backside metal line. A FinFET has one or more fin structures as the channel structure of the transistor. The fin structure protrudes vertically from the substrate and extends horizontally, and at least three surfaces of the fin structure are surrounded by a gate structure. In some embodiments of the FinFET, various numbers of surfaces of the FinFET are surrounded by a gate structure. A nanosheet transistor is characterized by one or more nanosheet channel layers as the channel structure of the transistor. The nanosheet channel layers are vertically stacked and extend horizontally based on the substrate, and all four surfaces of each nanosheet channel layer are surrounded by a gate structure. Nanosheet transistors are referred to as all-around gate (GAA) transistors or multi-bridge channel field effect transistors (MBCFETs).

[0004] However, forming a backside contact structure at the backside of a semiconductor device including multiple field effect transistors is a challenging process due to various risks including possible misalignment of the backside contact structure with source / drain regions and short circuits between the backside contact structure and adjacent elements of the semiconductor device.

[0005] The information disclosed in this background technology section may be known to the inventors before or during the process of implementing the embodiments of the present application or derived by the inventors, or may be technical information acquired during the process of implementing the embodiments. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the invention

[0006] The present disclosure provides a semiconductor device in which a backside contact structure is formed in a self-aligned manner based on a pair of etch stop layers. The semiconductor device may include a substrate layer that performs the role of a BDI layer together with one of the etch stop layers. In addition, the semiconductor device does not have a placeholder structure in the backside isolation structure.

[0007] According to an embodiment, a semiconductor device is provided, which may include: a channel structure; a gate structure on the channel structure; a first source / drain region on the channel structure; a substrate layer below the gate structure; a first etch stop layer below the substrate layer; a back side spacer on the side surfaces of the substrate layer and the first etch stop layer; and a back side contact structure on the bottom surface of the first source / drain region and the side surface of the back side spacer.

[0008] According to an embodiment, a semiconductor device is provided, which may include: a channel structure; a gate structure on the channel structure; a first source / drain region and a second source / drain region connected by the channel structure; a back side contact structure on the bottom surface of the first source / drain region; a front side contact structure on the top surface of the second source / drain region; and a first etch stop layer on the bottom surface of the second source / drain region.

[0009] According to an embodiment, a method for manufacturing a semiconductor device is provided. The method may include: forming a channel structure on a substrate and forming a gate structure on the channel structure; forming a placeholder recess in the substrate; forming a backside spacer on a side surface of the placeholder recess; forming a first source / drain region on the channel structure; forming a substrate layer from the substrate below the first gate structure, so that the substrate layer is disposed on a first side of the backside spacer; forming a first etch stop layer below the substrate layer on the first side of the backside spacer; and forming a backside contact structure in the placeholder recess, so that the backside contact structure is isolated from the substrate layer by the backside spacer and the first etch stop layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1A and Figure 1B A semiconductor device including a backside contact structure according to one or more embodiments is shown;

[0012] Figure 2 A semiconductor device including a self-aligned backside contact structure and an etch stop layer according to one or more embodiments is shown;

[0013] Figures 3A-3Sshows an intermediate semiconductor device obtained after respective steps of manufacturing a semiconductor device including a self-aligned backside contact structure and an etch stop layer according to one or more embodiments;

[0014] Figure 4A and Figure 4B A method of manufacturing a system according to one or more embodiments is shown and described, including reference Figures 3A-3S A flowchart of a method for a semiconductor device with a self-aligned backside contact structure and an etch stop layer; and

[0015] Figure 5 is a diagram showing a method according to one or more embodiments including Figure 2 Schematic block diagram of an electronic device with a self-aligned backside contact structure and an etch stop layer is shown. DETAILED DESCRIPTION

[0016] The embodiments of the present disclosure described here are example embodiments, and therefore, the present disclosure is not limited thereto, but can be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment that is also provided here or not provided here but consistent with the present disclosure. For example, even if the matter described in a specific example or embodiment is not described in an example or embodiment different from it, the matter can also be understood as being related to or combined with different examples or embodiments, unless otherwise mentioned in its description. In addition, it should be understood that all descriptions of the principles, aspects, examples and embodiments of the present disclosure are intended to cover their structural and functional equivalents. In addition, these equivalents should be understood to include not only currently known equivalents, but also equivalents to be developed in the future, that is, all devices invented to perform the same function, regardless of their structure. For example, the channel layer, sacrificial layer and isolation layer described here can be of different types or forms, as long as the present disclosure can be applied thereto.

[0017] It will be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as an "element") of a semiconductor device is referred to as being "on" another element of the semiconductor device, "above" another element of the semiconductor device, "on" another element of the semiconductor device, "below" another element of the semiconductor device, "below" another element of the semiconductor device, "under" another element of the semiconductor device, "connected to" another element of the semiconductor device, or "coupled to" another element of the semiconductor device, it may be directly on, directly above, directly on, directly below, directly below, directly below, directly connected to, or directly coupled to another element, or intervening elements may be present. In contrast, when an element of a semiconductor device is referred to as being “directly on”, “directly over”, “directly on”, “directly below”, “directly under”, “directly connected to”, or “directly coupled to” another element of the semiconductor device, there are no intervening elements. Like reference numerals refer to like elements throughout this disclosure.

[0018] For ease of description, spatial relationship terms, such as "above", "above", "on", "below", "below", "below", "under", "under", "left", "right", "lower left", "lower right", "upper left", "upper right", "center", "middle", etc., may be used here to describe the relationship of one element to another element as shown in the figure. It will be understood that the spatial relationship terms are intended to cover different orientations of the semiconductor device in use or operation other than the orientation depicted in the figure. For example, if the semiconductor device in the figure is turned over, the element described as "below" or "below" another element will be oriented as "above" another element. Therefore, the term "below" can cover both orientations including above and below. The semiconductor device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used here are interpreted accordingly. As another example, elements referred to as "left" elements and "right" elements can be "right" elements and "left" elements when the device or structure including these elements is oriented differently. Therefore, in the following description, the "left" element and the "right" element may also be referred to as the "first" element or the "second" element, respectively, as long as their structural relationship is clearly understood in the context of the description. Similarly, the terms "lower" element and "upper" element may be referred to as the "first" element and the "second" element, respectively, with the necessary description to distinguish the two elements.

[0019] It will be understood that although the terms "1st", "2nd", "3rd", "4th", "5th", "6th", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element described in the description of the embodiments may be referred to as a second element in one set of claims and as a first element in another set of claims without departing from the teachings of the present disclosure.

[0020] As used herein, expressions such as "at least one of...", when preceding a list of elements, modify the entire list of elements without modifying the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. Here, when the terms "same" or "equal" are used to compare the dimensions of two or more elements, the terms may encompass "substantially the same" or "substantially equal" dimensions. In addition, when the terms "coplanar" or "aligned" are used to compare the positional relationship between two or more elements, the terms may also encompass "substantially coplanar" or "substantially aligned" dimensions.

[0021] It will also be understood that even if a certain step or operation of manufacturing a device or structure is described as being performed later than another step or operation, the step or operation may be performed later than the other step or operation unless the other step or operation is described as being performed after the step or operation.

[0022] Many embodiments are described here with reference to cross-sectional views, which are schematic illustrations of embodiments (and intermediate structures). As such, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments should not be interpreted as being limited to the specific shapes of the regions shown here, but rather include shape deviations, for example, caused by manufacturing. The various regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the present disclosure. In addition, in the accompanying drawings, the sizes and relative sizes of the layers and regions may be exaggerated for clarity. Therefore, it will be understood that when any of the structures described herein is examined by a scanning electron microscope (SEM), a transmission electron microscope (TEM), a focused ion beam (FIB) microscope, etc., such schematic illustrations may not reflect actual images.

[0023] For the sake of brevity, conventional elements, structures or layers of semiconductor devices including nanosheet transistors or fin field effect transistors and the materials forming them may be described in detail or not in detail here. For example, when the layer or structure is irrelevant to the novel features of the implementation, a certain isolation layer, buffer layer or silicide layer of the semiconductor device and the materials forming them may be omitted here. In addition, when the materials forming the known structural elements of the semiconductor device are irrelevant to the novel features of the implementation, the description of these materials may be omitted here.

[0024] Figure 1A and Figure 1B A semiconductor device including a backside contact structure according to one or more embodiments is shown.

[0025] Figure 1A is a simplified plan view of a semiconductor device 10 according to one or more embodiments, Figure 1B Shows Figure 1A 1 is a cross-sectional view of a semiconductor device 10 in the D1 direction along the line II' shown therein. It will be understood that the D1 direction is a channel length direction intersecting the D2 direction, the D2 direction is a channel width direction or a cell height direction, and the D3 direction is a vertical direction intersecting the D1 direction and the D2 direction.

[0026] refer to Figure 1A and Figure 1B, the semiconductor device 10 may include first to third channel stacks 11A-11C, each of which includes a plurality of channel layers 112 vertically stacked on the front side of the semiconductor device 10 and surrounded by a gate structure 115. Each of the channel layers 112 may be referred to as a nanosheet or nanoribbon extending in the D1 direction.

[0027] The channel layer 112 of each of the channel stacks 11A-11C surrounded by the gate structure 115 can form a channel structure that connects the source / drain regions formed on both sides of the channel structure to each other to form a field effect nanosheet transistor. For example, a field effect nanosheet transistor can be formed by a channel structure that includes a channel layer 112, a gate structure 115 surrounding the channel structure, and a first source / drain region 130L and a second source / drain region 130R connected to each other through the channel layer 112 of the second channel stack 11B.

[0028] The one or more materials forming the channel layer 112 may include, for example, silicon (Si), silicon germanium (SiGe). The gate structure 115 may be formed of one or more materials, including, for example, copper (Cu), aluminum (Al), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), or a combination thereof. Each of the source / drain regions 130L and 130R may include one or more materials, for example, silicon (Si), silicon germanium (SiGe) doped with impurities. The source / drain regions 130L and 130R may be p-type or n-type.

[0029] Each of the channel stacks 11A-11C may further include an inner spacer 131 formed at a side surface of a lower portion of the gate structure 115 below the channel layer 112 in the D3 direction. A gate spacer 116 may be formed at a side surface of an upper portion of the gate structure 115 in each of the channel stacks 11A-11C. The inner spacer 131 may isolate a lower portion of the gate structure 115 from the source / drain regions 130L and 130R, and the gate spacer 116 may isolate an upper portion of the gate structure 115 from the source / drain regions 130L and 130R. The one or more materials forming the inner spacer 131 and the gate spacer 116 may include, for example, silicon nitride (e.g., SiN, Si 3 N 4 ) or silicon oxide (such as SiO 2 ), but not limited to this.

[0030] The semiconductor device 10 may further include a plurality of contact structures, including a front side contact structure 170, a gate contact structure 180, and a back side contact structure 150. The front side contact structure 170 may be formed on the top surface of the second source / drain region 130R to connect the second source / drain region 130R to a voltage source or another circuit element through a back end of line (BEOL) structure 190 including one or more metal lines and vias. The gate contact structure 180 may be formed on the top surface of the gate structure 115 to receive a gate input signal for the gate structure 115 through the BEOL structure 190. The front side contact structure 170 and the gate contact structure 180 may be isolated from each other by a front side isolation structure 162. The back side contact structure 150 may be formed on the bottom surface of the first source / drain region 130L to connect the first source / drain region to a voltage source or another circuit element. The back side contact structure 150 may be isolated from other circuit elements by a back side isolation structure 161. The contact structures 170, 180, and 150 may each be formed of one or more materials such as copper (Cu), aluminum (Al), tungsten (W), ruthenium (Ru), molybdenum (Mo), etc. The front side isolation structure 162 and the back side isolation structure 161 may each be formed of a silicon oxide (e.g., SiO 2 The low-k dielectric material is formed.

[0031] Meanwhile, the semiconductor device 10 may include a placeholder structure 140 formed below the second source / drain region 130R. The placeholder structure 140 may have been formed to provide a space for forming another backside contact structure therein during the process of manufacturing the semiconductor device 10. There may also be another placeholder structure below the first source / drain region 130L, which is removed and replaced by the backside contact structure 150. Unlike the removed placeholder structure, the placeholder structure 140 below the second source / drain region 130R may remain there without being replaced by another backside contact structure because the front side contact structure 170 is formed on the second source / drain region 130R to connect the second source / drain region 130R to a voltage source or another circuit element through the BEOL structure 190. The placeholder structure 140 may be formed of a material such as silicon germanium (SiGe), but is not limited thereto.

[0032] The placeholder structure 140 and the backside contact structure 150 may be formed in and surrounded by the backside isolation structure 161. In the process of manufacturing the semiconductor device 10, the backside isolation structure 161 may replace the substrate 101 formed of silicon (Si), but is not limited thereto (see Figures 3A-3S ).

[0033] A bottom diffusion isolation (BDI) layer 102 may be formed to prevent current from leaking from the gate structure 115 and the source / drain regions 130L and 130R to the backside isolation structure 161. The BDI layer 102 may also protect the gate structure 115 and the inner spacer 131 in a backside process of forming the backside isolation structure 161 by removing the substrate 101 and replacing the substrate 101 with the backside isolation structure 161. The BDI layer 102 may include silicon nitride, silicon carbon nitride (SiCN), or silicon boron carbon nitride (SiBCN), without limitation. However, the formation of the BDI layer 102 is a challenging step in the process of manufacturing the semiconductor device 10, at least because the BDI layer 102 is formed by replacing a certain sacrificial layer formed under the channel layer 112 while other sacrificial layers are removed and replaced by a lower portion of the gate structure 115 in a complex frontside process when manufacturing the semiconductor device 10.

[0034] Forming the back contact structure 150 through the back isolation structure 161 during the manufacturing process of the semiconductor device 10 also has the risk of misalignment between the back contact structure 150 and the first source / drain region 130L, and the risk of short circuit with the placeholder structure 140 formed of silicon germanium (SiGe), such as Figure 1B shown.

[0035] Therefore, one or more other embodiments are provided below to address the aforementioned difficulties in forming the BDI layer 102 and the backside contact structure 150 .

[0036] Figure 2 A semiconductor device including a self-aligned backside contact structure and an etch stop layer according to one or more embodiments is shown.

[0037] refer to Figure 2 , the semiconductor device 20 may include Figure 1A and Figure 1B The semiconductor device 20 does not have the BDI layer 102 and the placeholder structure 140 included in the semiconductor device 10, but instead, an additional structural element is formed under each of the first to third channel stacks 21A-21C in the backside isolation structure 161. In addition, the backside contact structure 250 may be formed in the backside isolation structure 161 in a manner different from that of the backside contact structure 150 of the semiconductor device 10.

[0038] Hereinafter, when describing different aspects of the semiconductor device 20 , repeated descriptions regarding structural elements common to the semiconductor devices 10 and 20 may be omitted.

[0039] In the semiconductor device 20, in each of the channel stacks 21A-21C, the substrate layer 101 may be formed on the bottom surfaces of the gate structure 115 and the lowermost inner spacer 131, and the bottom surfaces of the gate structure 115 and the lowermost inner spacer 131 may be horizontally coplanar and aligned. A first etch stop layer 103 may be formed on the bottom surface of the substrate layer 101, and a second etch stop layer 104 may be formed on the bottom surface of the first etch stop layer. The side surface of the first etch stop layer 103 may be vertically aligned or coplanar with the side surfaces of the substrate layer 101, the channel layer 112, the inner spacer 131, and the gate spacer 116 thereover. A backside spacer 105 may be formed on the side surfaces of the first etch stop layer 103 and the substrate layer 101.

[0040] In addition, a second etch stop layer 104 may be formed on the bottom surface of the first etch stop layer 103 in each channel stack 21A-21C. The second etch stop layer 104 formed on the bottom surface of the first etch stop layer 103 in the second channel stack 21B may extend continuously to the bottom surface of the first etch stop layer 103 in the third channel stack 21C along the bottom surface and side surfaces of the backside spacer 105 between the two channel stacks 21B and 21C and the bottom surface of the second source / drain region 130R. However, the second etch stop layer 104 on the bottom surface of the first etch stop layer 103 in the second channel stack 21B may not extend to the bottom surface of the first etch stop layer 103 in the first channel stack 21A because the backside contact structure 250 is formed to contact the bottom surface of the first source / drain region 130L through the backside isolation structure 161. Therefore, a disconnected portion of the second etch stop layer 104 may be formed on the bottom surface of the first etch stop layer 103 in the first channel stack 21A.

[0041] In the semiconductor device 20, the backside contact structure 250 can be self-aligned to the first source / drain region 130L based on the substrate layer 101, the first etch stop layer 103, the second etch stop layer 104, and the backside spacer 105 in each of the first channel stack 21A and the second channel stack 21B through the backside isolation structure 161. In the case where the backside contact structure 250 is self-aligned based on these layers, the risk of misalignment of the backside contact structure 250 with the first source / drain region 130L can be prevented or reduced.

[0042] In addition, the semiconductor device 20 does not include the BDI layer 102, which is formed in the semiconductor device 10 to protect and support the lower portion of the inner spacer 131 and the gate structure 115 and prevent current from leaking from the gate structure 115 into the backside isolation structure 161 in the backside process of forming the backside contact structure 150. In contrast, the substrate layer 101 may protect and support the lower portion of the inner spacer 131 and the gate structure 115 in the backside process of forming the backside contact structure 250. The substrate layer 101 is a structure remaining after the substrate 101 is partially removed in the backside process and replaced by the backside isolation structure 161. However, since the substrate layer 101 may not suppress current leakage from the gate structure 115 in each of the channel stacks 21A-21C, the first etch stop layer 103 may be formed under the substrate layer 101 as a dielectric passivation layer. Therefore, the substrate layer 101 and the first etch stop layer 103 may be formed in each of the channel stacks 21A-21C of the semiconductor device 20 to form the function of the BDI layer 102 of the semiconductor device 10. Since the BDI layer 102 in the semiconductor device 10 is not necessary in the semiconductor device 20, manufacturing simplicity may be achieved when manufacturing the semiconductor device 20.

[0043] In addition, the first etch stop layer 103 together with the back side spacer 105 can isolate the back side contact structure 250 from the substrate layer 101. Therefore, the substrate layer 101 can have a thickness TH3 that is smaller than the thickness TH2 of the back side spacer 105 in the D3 direction. The first etch stop layer 103 can have a thickness TH4 that is also smaller than the thickness TH2 of the back side spacer 105 in the D3 direction. The top surfaces of the substrate layer 101, the back side spacer 105, and the back side contact structure 250 can be horizontally aligned or coplanar with each other. Here, the D3 direction can refer to the direction in which the gate structure 115, the substrate layer 101, the first etch stop layer 103, and the second etch stop layer 104 are arranged to form the semiconductor device 20.

[0044] Therefore, the substrate layer 101 and the first etch stop layer 103 in each of the first and second channel stacks 21A and 21B may be formed on one side of the backside spacer 105 , and an upper portion of the backside contact structure 250 may be on the other side of the backside spacer 105 .

[0045] The second etch stop layer 104 can be used to guide the patterning of the back contact recess leading to the bottom surface of the first source / drain region 130L in the back isolation structure 161, so that the back contact structure 250 can be formed in the back contact recess formed based on the second etch stop layer 104 without relying on the placeholder structure. Therefore, the back contact structure 250 can take the form of a structure that penetrates the second etch stop layer 104 to contact the bottom surface of the first source / drain region 130L.

[0046] Since the BDI layer 102 in the semiconductor device 10 is not necessary in the semiconductor device 20 , manufacturing simplicity can be achieved when manufacturing the semiconductor device 20 .

[0047] The semiconductor device 20 may also be characterized in that the placeholder structure 140 in the backside isolation structure 161 may be removed in a backside process, thereby eliminating the risk of a short circuit between the removed placeholder structure 140 and the backside contact structure 250 .

[0048] The back side spacer 105 may be made of silicon nitride or a composite thereof (eg SiN, Si 3 N 4 , SiBCN, SiCN, etc.), but not limited thereto. The first etching stop layer 103 may also be made of silicon nitride or silicon oxide (e.g. SiN, Si 3 N 4 、SiO 2 The second etch stop layer 104 may be formed of aluminum nitride or aluminum oxide (AlN, AlO x The first etching stop layer 103 is formed by, but not limited to, a silicon nitride or silicon oxide having an etching selectivity to the first etching stop layer 103.

[0049] Hereinafter, a method of manufacturing a semiconductor device 20 including a self-aligned backside contact structure 250 is described.

[0050] Figures 3A-3S An intermediate semiconductor device obtained after corresponding steps of manufacturing a semiconductor device including a self-aligned backside contact structure and an etch stop layer according to one or more embodiments is shown. Figure 2 The semiconductor devices 20 shown are the same or correspond, so repeated descriptions thereof may be omitted and the same reference numerals may be used in the following description.

[0051] refer to Figure 3A , the intermediate semiconductor device 20 ′ may include a substrate 101 on which an initial channel stack 110 ′, a dummy gate structure 115 ′, and three hard mask patterns 160 are formed in this order.

[0052] The initial channel stack 110' may include a sacrificial layer 111 and a channel layer 112 which are epitaxially grown one after another to be stacked on the substrate 101. The sacrificial layers 111 may each be formed of silicon germanium (SiGe), and the channel layer 112 may include silicon (Si) or SiGe. The sacrificial layer 111 is referred to as such that these layers are formed therein to support the semiconductor device 20 ( Figure 2) and will be formed in a later step ( Figure 3K ) is removed and replaced by the gate structure.

[0053] The dummy gate structure 115' may be formed on the uppermost channel layer 112 and planarized by, for example, chemical mechanical polishing (CMP), but is not limited thereto. The hard mask pattern 160 may be formed at a position on the dummy gate structure 115' at which the hard mask pattern 160 is used to Figure 1A and Figure 1B The dummy gate structure 115′ of each of the first to third channel stacks 11A-11C shown in FIG. 1 will be used in the next step ( Figure 3B ) is patterned and remains under the hard mask pattern 160. The dummy gate structure 115' may be formed of a material such as polysilicon or amorphous silicon, and the hard mask pattern 160 may be formed of a material such as silicon nitride or a composite thereof (eg, SiN, Si 3 N 4 , SiBCN, SiNC, SiNOC, etc.) materials.

[0054] refer to Figure 3B , the dummy gate structure 115 ′ may be patterned to form three dummy gate structures 115 ′ based on the hard mask pattern 160 .

[0055] The formation of the three dummy gate structures 115' may be performed by, for example, dry etching such as reactive ion etching (RIE) based on the hard mask pattern 160. When the dummy gate structures 115' are formed based on the hard mask pattern 160, the top surface of the initial channel stack 110', for example, the top surface of the uppermost channel layer 112 may be exposed through the first recess R1 and the second recess R2.

[0056] refer to Figure 3C , a gate spacer 116 may be formed on a side surface of each of the dummy gate structures 115 ′ having the hard mask pattern 160 thereon.

[0057] The gate spacer 116 may be formed by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), or a combination thereof, but is not limited thereto. The gate spacer 116 may be formed of a material such as silicon nitride (e.g., SiN, Si 3 N 4 ) or silicon oxide (such as SiO 2 ) of the material (not limited thereto) may be deposited in the previous step ( Figure 3B), and is etched back to leave the gate spacer material only on the side surface of each dummy gate structure 115' having the hard mask pattern 160 thereon.

[0058] refer to Figure 3D The initial channel stack 110 ′ may be etched downward through the recesses R1 and R2 based on the hard mask pattern 160 and the gate spacers 116 to form first to third channel stacks 21A- 21C exposing the top surface of the substrate 101 therebetween.

[0059] By etching back the initial channel stack 110', the first recess R1 and the second recess R2 can extend downward to expose the top surface of the substrate 101 and the side surfaces of the channel layer 112 and the sacrificial layer 111, thereby forming three channel stacks 21A-21C separated by the recesses R1 and R2. The etching back operation in this step can be performed by, for example, dry etching, but is not limited thereto.

[0060] refer to Figure 3E , the side surface of each sacrificial layer 111 in each of the channel stacks 21A-21C may be recessed to provide a substrate for the next step ( Figure 3F ) in which a space of the internal spacer 131 is formed.

[0061] The etching operation in this step may be performed by, for example, selective wet etching or dry etching, but is not limited thereto, and only silicon germanium (SiGe) included in the sacrificial layer 111 is removed relative to silicon (Si) included in the channel layer 112 and the substrate 101. For example, hydrofluoric acid (HF) and nitric acid (HNO 3 ) can be used for selective etching in this step.

[0062] refer to Figure 3F , the inner spacer 131 may be formed at the side surface of the recessed sacrificial layer 111 .

[0063] Each inner spacer 131 may be formed such that a side surface of the inner spacer 131 exposed to the recesses R1 and R2 is vertically aligned or coplanar with a side surface of the channel layer 112, and the gate spacer 116 is also exposed to the recesses R1 and R2. The formation of the inner spacer 131 may be performed, for example, by atomic layer deposition (ALD) or any other suitable deposition process or electroplating.

[0064] The inner spacer 131 may be made of silicon nitride (eg, SiN, Si 3 N 4 ) or silicon oxide (such as SiO 2 ) is formed of a material, but is not limited thereto, and may be the same as or different from the material forming the gate spacer 116.

[0065] refer to Figure 3G , the substrate 101 , the top surface of which is exposed by the recesses R1 and R2 , may be patterned to extend the recesses R1 and R2 to below the level of the top surface of the substrate 101 .

[0066] In this step, the substrate 101 exposed by the first recess R1 and the second recess R2 may be patterned by, for example, dry etching (not limited thereto) based on the hard mask pattern 160 and the gate spacer 116, so that a first placeholder recess PR1 and a second placeholder recess PR2 each having a first depth DT1 in the D3 direction are obtained in the substrate 101 below the level of the top surface of the substrate 101. The top surface of the substrate 101 may be horizontally coplanar or aligned with the bottom surface of the lowermost inner spacer 131 and the bottom surface of the lowermost sacrificial layer 111.

[0067] The first placeholder recess PR1 and the second placeholder recess PR2 may be connected to the first recess R1 and the second recess R2, respectively. In a later step, in the recesses R1 and R2, source / drain regions will be formed, and placeholder structures will be formed in the placeholder recesses PR1 and PR2.

[0068] refer to Figure 3H , the backside spacer 105 may be formed along the entire surfaces of the recesses R1 and R2 and the placeholder recesses PR1 and PR2 , and may be partially removed below a second depth DT2 from the level of the top surface of the substrate 101 in each of the placeholder recesses PR1 and PR2 .

[0069] The backside spacer 105 may be formed by, for example, depositing a material such as silicon nitride or a composite thereof (e.g., SiN, SiBCN, SiOCN, SiOC, etc.) on the entire surfaces of the recesses R1 and R2 and the placeholder recesses PR1 and PR2 by, for example, atomic layer deposition (ALD), and partially removing the deposited material below a second depth DT2 from the level of the top surface of the substrate 101 in each of the placeholder recesses PR1 and PR2. Here, the entire surface of each of the recesses R1 and R2 may include side surfaces of the gate spacer 116, the channel layer 112, and the sacrificial layer 111 exposed by the recesses R1 and R2.

[0070] The partial removal of the backside spacer 105 in this step may include dry etching except for the portion below the second depth DT2 of the backside spacer 105 based on masking in each of the placeholder recesses PR1 and PR2 for inspection.

[0071] refer to Fig. 3I, the backside spacer 105 may be further partially removed above the level of the top surface of the substrate 101, leaving only a portion of the second thickness TH2 in the D3 direction below the level of the top surface of the substrate 101 in each of the placeholder recesses PR1 and PR2, and a placeholder structure 140 may be formed in each of the placeholder recesses PR1 and PR2 to have the first thickness TH1 in the D3 direction.

[0072] The partial removal of the backside spacer 105 in this step may also be performed by, for example, dry etching based on masking the portion of the backside spacer 105 below the level of the top surface of the substrate 101 in each of the placeholder recesses PR1 and PR2. Therefore, the backside spacer 105 may remain only by the masked portion, and the side surfaces of the channel layer 112, the sacrificial layer 111, and the gate spacer 115 may be exposed again in the recesses R1 and R2 over the remaining portion of the backside spacer 105, which has a second thickness TH2 equal to the second depth DT2 in the direction D3.

[0073] Before or after partially removing the backside spacer 105 in this step, a placeholder structure 140 may be formed in each of the placeholder recesses PR1 and PR2 below the level of the top surface of the substrate 101 by, for example, PVD, CVD, PECVD, etc. (not limited thereto) of a material such as silicon germanium (SiGe). Alternatively or additionally, the placeholder structure 140 may be epitaxially grown from the substrate 101 exposed by each of the placeholder recesses PR1 and PR2.

[0074] The placeholder structure 140 may fill each placeholder recess PR1 and PR2 in which the backside spacer 105 is formed below the level of the top surface of the substrate 101. Therefore, the placeholder structure 140 may have a first thickness TH1 equal to a first depth DT1 of each placeholder recess PR1 and PR2 in the D3 direction.

[0075] After the backside spacers 105 and the placeholder structures 140 are formed in each of the placeholder recesses PR1 and PR2 , the top surfaces of the backside spacers 105 , the placeholder structures 140 , and the substrate 101 may be horizontally aligned or coplanar with each other.

[0076] refer to Figure 3J , a first source / drain region 130L and a second source / drain region 130R may be formed based on the channel layer 112 .

[0077] The first source / drain region 130L can be epitaxially grown from the channel layer 112 of the first channel stack 21A and the second channel stack 21B in the first recess R1, and the second source / drain region 130R can be epitaxially grown from the channel layer 112 of the second channel stack 21B and the third channel stack 21C in the second recess R2, and the sacrificial layer 111 in each of the channel stacks 21A-21C is blocked by the internal spacer 131 to prevent or inhibit the epitaxy of the sacrificial layer 111 from silicon germanium (SiGe).

[0078] The source / drain regions 130L and 130R may be in-situ doped with p-type impurities (e.g., boron, gallium, or indium) or n-type impurities (e.g., phosphorus, arsenic, or antimony). Alternatively or additionally, impurities may be implanted into the source / drain regions 130L and 130R after epitaxial growth of the source / drain regions 130L and 130R.

[0079] After forming the source / drain regions 130L and 130R, bottom surfaces of the source / drain regions 130L and 130R may contact top surfaces of the backside spacers 105 and the placeholder structures 140 .

[0080] refer to Figure 3K , the hard mask pattern 160 may be removed, and the dummy gate structure 115 ′ and the sacrificial layer 111 may be removed and replaced by the gate structure 115 .

[0081] After forming the source / drain regions 130L and 130R, the hard mask pattern 160 and portions of the gate spacers 116 at side surfaces of the hard mask pattern 160 on the dummy gate structure 115 ′ may be removed by, for example, dry etching including stripping or ashing (not limited thereto).

[0082] The dummy gate structure 115' and the sacrificial layer 111 may be removed by, for example, wet etching and / or dry etching to form a void or space in each channel stack 21A-21C, and the gate structure 115 may be formed in these voids or spaces by, for example, CVD, PVD, PECVD, ALD, or a combination thereof (not limited thereto).

[0083] refer to Figure 3L , can be done in the previous step ( Figure 3K ) a front side isolation structure 162, a front side contact structure 170, a gate contact structure 180 and a BEOL structure 190 are formed on the intermediate semiconductor device 20' obtained in the process.

[0084] The front side isolation structure 162 may be formed in the previous step ( Figure 3K) is formed on the intermediate semiconductor device 20' including the source / drain regions 130L and 130R, so that the source / drain regions 130L and 130R are isolated from each other and from other circuit elements. The front side isolation structure 162 may include silicon oxide (e.g., SiO 2 The formation of the front side isolation structure 162 may be performed by, for example, PVD, CVD, PECVD, or a combination thereof (not limited thereto).

[0085] Subsequently, a front side contact structure 170 and a gate contact structure 180 including a metal or a metal compound may be formed on the top surfaces of the gate structure 115 and the second source / drain region 130R, respectively, through the front side isolation structure 162. The front side contact structure 170 may connect the second source / drain region 130R to a voltage source or another circuit element. The gate contact structure 180 may receive a gate input signal for the gate structure 115. Here, the front side contact structure may not be formed on the top surface of the first source / drain region 130L because it may be formed in a later step ( Figure 3S ) is formed in the back side contact structure 250 instead of the front side contact structure for connecting the first source / drain region 130L to a voltage source or another circuit element.

[0086] Additionally, BEOL structures 190 may be formed on front side isolation structures 162 to connect front side contact structures 170 and gate contact structures 180 to voltage sources or other circuit elements through a plurality of metal lines and / or vias formed therein. Formation of BEOL structures 190 may include one or more damascene processes.

[0087] refer to Figure 3M , the substrate 101 may be removed to leave only its top portion at the sides of the backside spacers 105 .

[0088] As previously referenced Figure 2 As described above, the semiconductor device 20' manufactured from the intermediate semiconductor device 20' here can omit the BDI layer 102 that requires a complex process to form. Therefore, at least in order to take over the function of the BDI layer 102 of protecting and supporting the inner spacer 131 and the gate structure 115 in the subsequent backside process, the top portion of the substrate 101 may not be removed, but may be retained as the substrate layer 101 below the bottom surface of the lowermost inner spacer 131 and the lowermost portion of the gate structure 115.

[0089] Partial removal of the substrate 101 in this step may be performed by, for example, dry etching (not limited thereto) to a predetermined thickness to leave only the top portion of the substrate 101 as the substrate layer 101 below each of the channel stacks 21A- 21C.

[0090] The substrate layers 101 may each be formed to have a third thickness TH3 in the direction D3 that is less than the second thickness TH2 of the backside spacers 105 , so that current leakage from the gate structure 115 may be minimized and may not reach over the backside spacers 105 .

[0091] The removal operation in this step and the subsequent operation in manufacturing the semiconductor device can be performed by replacing the Figure 3L ) is performed by turning the intermediate semiconductor device 20' obtained in the process upside down.

[0092] refer to Figure 3N , a first etch stop layer 103 may be formed under the substrate layer 101 as a dielectric passivation layer.

[0093] The first etch stop layer 103 formed in this step can prevent current from leaking from the lower portion of the gate structure 115 through the substrate layer 101 to the backside isolation structure to be formed in a later step. Figure 1A and Figure 1B The function of the BDI layer 102 in the semiconductor device 10 is described below.

[0094] The formation of the first etch stop layer 103 may be performed by depositing a material such as silicon nitride or a composite thereof (e.g., SiN, SiCN, SiBCN, etc.) on the bottom surface of the intermediate semiconductor device 20′ obtained in the previous step by, for example, CVD, PVD, PECVD, ALD, or a combination thereof, and then partially etching the deposited material from the bottom surface of the placeholder structure 140.

[0095] Therefore, the first etch stop layer 103 may remain only on the bottom surface of the first substrate layer 101 in each channel stack 21A-21C. The first etch stop layer 103 may be formed to have a fourth thickness TH4 in the D3 direction under the first substrate layer 101, and the fourth thickness TH4 is less than the second thickness TH2 of the backside spacer 105.

[0096] refer to Fig.3O , the placeholder structure 140 formed under the first source / drain region 130L and the second source / drain region 130R can be removed based on the first etch stop layer 103 and the backside spacer 105 to reopen the placeholder recesses PR1 and PR2, and the bottom surfaces of the first source / drain region 130L and the second source / drain region 130R are exposed through the placeholder recesses PR1 and PR2, respectively.

[0097] When the placeholder structure 140 under the source / drain regions 130L and 130R is removed to reopen the placeholder recesses PR1 and PR2 with the backside spacers 105 on their side surfaces, bottom surfaces of the source / drain regions 130L and 130R and side surfaces of the backside spacers 105 may be exposed in the placeholder recesses PR1 and PR2.

[0098] The etching may be performed by, for example, dry etching or etching with, for example, hot phosphoric acid (H 3 PO 4 The removal of the placeholder structure 140 is performed by wet etching with an etchant of (not limited to) MgSO4 or potassium hydroxide (KOH), which selectively etches the placeholder structure 140 of silicon germanium (SiGe) relative to the first etch stop layer 103 of silicon nitride or silicon oxide and the backside spacer 105 of silicon nitride.

[0099] When the placeholder structure 140 is removed from the intermediate semiconductor device 20' in this step, a possible risk of a short circuit between the backside contact structure formed in a later step and any one of the placeholder structures 140 can be avoided when the semiconductor device including the backside contact structure is completed. At the same time, even if the placeholder structure 140 is removed, the placeholder recesses PR1 and PR2 can also help identify the backside contact structure formed in the later step ( Figure 3S ) where a backside contact structure will be formed through the backside isolation structure.

[0100] refer to Figure 3P , can be done in the previous step ( Fig.3O ) a second etch stop layer 104 is formed on the bottom surface of the intermediate semiconductor device 20' obtained in the process.

[0101] In this step, the second etch stop layer 104 can be continuously and conformally formed on the bottom surface of the intermediate semiconductor device 20', which includes the first etch stop layer 103, the backside spacer 105 and the bottom surface of the source / drain regions 130L and 130R and the side surface of the backside spacer 105, by, for example, atomic layer deposition (ALD).

[0102] Therefore, the placeholder recesses PR1 and PR2 are now defined by portions of the second etch stop layer 104 formed on the side surfaces of the backside spacers 105 and the bottom surfaces of the source / drain regions 130L and 130R.

[0103] The material forming the second etch stop layer 104 may include aluminum nitride or aluminum oxide (AlN, AlO x The first etch stop layer 103 may be made of silicon nitride or silicon oxide, but is not limited thereto.

[0104] refer to Figure 3Q , can be done in the previous step ( Figure 3P ) is formed on the bottom surface of the intermediate semiconductor device 20', and the backside isolation structure 161 is patterned based on the second etch stop layer 104 to be used in a later step ( Figure 3S ) is formed at a position where the back side contact structure 250 is to be formed, and a back side contact recess BR connected to the first place holder recess PR1 is formed.

[0105] The backside isolation structure 161 may be formed on the backside of the intermediate semiconductor device 20′ where the second etch stop layer 104 is formed, and patterned by, for example, photolithography, masking, and etching operations until the etching operation passes through the backside contact recess BR formed under the first source / drain region 130L and the backside contact recess BR formed in the previous step ( Fig.3O ) is stopped at the second etch stop layer 104. Here, the first source / drain region 130L is to be formed in a later step ( Figure 3S ) is connected to a target source / drain region of the backside contact structure, and the first placeholder recess PR1 is a target placeholder recess formed below the target source / drain region.

[0106] The back side isolation structure 161 is made of silicon oxide (e.g. SiO 2 The second etching stop layer 104 is formed of aluminum nitride or aluminum oxide (AlN, AlO x In the case where the backside isolation structure 161 is formed by wet etching, an etchant such as hydrofluoric acid (HF) may be used to selectively remove the backside isolation structure 161 relative to the second etch stop layer 104 by wet etching.

[0107] In this step, the etching operation can start from the bottom surface of the back side isolation structure 161 at the position where the first source / drain region 130L is formed above it, and continue until the back side contact recess BR is formed and the first placeholder recess PR1 is reopened in a self-aligned manner to expose the second etch stop layer 104 formed on the bottom surface of the first source / drain region 130L and at least a portion of the bottom surface and side surface of the back side spacer 105.

[0108] Subject to the etching process margin, a portion of the second etch stop layer 104 formed on a bottom surface of a portion of the first etch stop layer 103 may also be exposed.

[0109] refer to Figure 3R , a portion of the second etch stop layer 104 exposed by the backside contact recess BR and the first placeholder recess PR1 may be removed by patterning the second etch stop layer 104 to expose a bottom surface of the first source / drain region 130L and a bottom surface and side surfaces of the backside spacer 105 .

[0110] In this step, the patterning operation of the second etch stop layer 104 can be performed by, for example, dry etching or using a solvent such as phosphoric acid (H 3 PO 4 ) is performed by wet etching with an etchant of , which selectively etches the aluminum nitride or aluminum oxide forming the second etch stop layer 104 relative to the silicon or silicon germanium forming the first source / drain region 120L, the silicon nitride or their composites forming the first etch stop layer 103 and the backside spacer 105.

[0111] Therefore, the bottom surface of the first source / drain region 130L defining the first placeholder recess PR1 and the side surface of the back spacer 105 are exposed through the first placeholder recess PR1 and the back contact recess BR. In addition, the bottom surface of the back spacer 105 and the bottom surface of a portion of the first etch stop layer 103 adjacent to the back spacer 105 may also be exposed through the back contact recess BR.

[0112] refer to Figure 3S A backside contact structure 250 may be formed in the backside contact recess BR and the first placeholder recess PR1 to contact a bottom surface of the first source / drain region 130L while being isolated from the substrate layer 101 by the backside spacer 105 and the first etch stop layer 103 .

[0113] The back side contact structure 250 can be formed by depositing metal or metal compound in the back side contact recess BR and the first placeholder recess PR1 by, for example, CVD, PVD, PECVD or a combination thereof (not limited to these), so that the back side contact structure 250 contacts the bottom surface of the first source / drain region 130L in a self-aligned manner based on the first etch stop layer 103, the second etch stop layer 104 and the back side spacer 105 exposed in the back side contact recess BR.

[0114] Therefore, forming the backside contact structure 250 in the above method can avoid the complicated process of forming the BDI layer and can prevent the risk of misalignment between the backside contact structure 250 and the first source / drain region 130L and the risk of short circuit between the backside contact structure 250 and the placeholder structure.

[0115] Figure 4A and Figure 4B A method of manufacturing a system according to one or more embodiments is shown and described, including reference Figures 3A-3S A flow chart of a method for a semiconductor device having a self-aligned backside contact structure and an etch stop layer.

[0116] In S10, the initial channel stack including the plurality of semiconductor layers and the dummy gate structure thereon may be patterned to form a plurality of channel stacks on the substrate with corresponding recesses ( Figures 3A-3D). The semiconductor layers of the initial channel stack may include a plurality of sacrificial layers and channel layers alternately stacked one after another on the substrate. These semiconductor layers may be epitaxially grown from the substrate.

[0117] In S20, the substrate exposed by the recess may be patterned from the top to form a placeholder recess having a first depth in the substrate ( Figure 3E-3G ). At this time, the sacrificial layer in each channel stack may be recessed at a side surface thereof to form an inner spacer thereon.

[0118] In S30, a backside spacer having a second thickness below the level of the top surface of the substrate is formed at the side surface of the placeholder recess, and a placeholder structure ( Figures 3H-3I ).

[0119] In S40, source / drain regions ( Figure 3J ). The source / drain regions may be epitaxially grown from the channel layer.

[0120] In S50, the substrate may be patterned from the bottom so that only a top portion thereof having a third thickness less than the second thickness of the backside spacer may remain as a substrate layer ( Figure 3K-3M ). At this point, the front side process of forming the front side contact structure and the gate contact structure may have been performed.

[0121] In S60, a first etch stop layer may be formed on the bottom surface of each substrate layer, and the placeholder structure may be removed based on the first etch stop layer and the backside spacer, thereby reopening the placeholder recess having the backside spacer on its side surface ( Figure 3N-3O ).

[0122] In S70, a second etch stop layer may be formed on the bottom surface of the intermediate semiconductor device obtained in the previous step (S60), such that the second etch stop layer is conformally formed on the bottom surface of the source / drain region in each placeholder recess and the side surface of the backside spacer and on the bottom surface of the first etch stop layer and the backside spacer ( Figure 3P ).

[0123] In S80, a backside isolation structure may be formed on the second etch stop layer, and the backside isolation structure may be patterned to form a backside contact recess in the backside isolation structure, the backside contact recess exposing the second etch stop layer ( Figure 3Q ).

[0124] In S90, the second etch stop layer on the target placeholder recess is removed to expose the bottom surface of the target source / drain region, and a backside contact structure is formed through the backside contact recess and the target placeholder recess to contact the bottom surface of the target source / drain region ( Figure 3S ).

[0125] Figure 5 is a diagram showing a method according to one or more embodiments including Figure 2 Schematic block diagram of an electronic device with a self-aligned backside contact structure and an etch stop layer is shown.

[0126] refer to Figure 5 , the electronic device 1000 may include at least one processor 1100, a communication module 1200, an I / O module 1300, a memory 1400, and a buffer RAM module 1500. According to an embodiment, the electronic device 1000 may be a mobile device such as a smart phone or a tablet computer, but is not limited thereto.

[0127] The processor 1100 may control the operation of the electronic device 1000. The communication module 1200 is implemented to perform wireless or wired communication with an external device. The I / O module 1300 is implemented to display data processed by the processor 1100 and / or receive data through a touch panel. The memory 1400 is implemented to store user data. The memory 1400 may be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash memory (UFS) device, etc. The memory 1400 may perform caching of mapping data and user data, as described above.

[0128] The buffer RAM module 1500 may temporarily store data for processing operations of the electronic device 1000. For example, the buffer RAM module 1500 may be a volatile memory such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc.

[0129] At least one component in the electronic device 1000 may include one or more components including Figure 2 A semiconductor device with a backside contact structure is shown.

[0130] The foregoing is a description of exemplary embodiments and should not be construed as limiting the present disclosure. Although several exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the above embodiments without substantially departing from the present disclosure.

[0131] CROSS-REFERENCE TO RELATED APPLICATIONS

[0132] This application is based on U.S. Provisional Application No. 63 / 547,450 filed in the United States Patent and Trademark Office on November 6, 2023, and claims priority to the U.S. Provisional Application, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: Channel structure; a gate structure on the channel structure; a first source / drain region on the channel structure; a substrate layer below the gate structure; a first etch stop layer below the substrate layer; a backside spacer on side surfaces of the substrate layer and the first etch stop layer; as well as A backside contact structure is on a bottom surface of the first source / drain region and a side surface of the backside spacer.

2. The semiconductor device according to claim 1, wherein In a direction in which the gate structure, the substrate layer, and the first etch stop layer are arranged, the substrate layer has a smaller thickness than the backside spacer. 3 . The semiconductor device according to claim 1 , wherein the substrate layer comprises silicon, and each of the backside spacer and the first etch stop layer comprises silicon nitride or a composite thereof.

4. The semiconductor device according to claim 1, further comprising: a second etch stop layer below the first etch stop layer; as well as A backside isolation structure is on the backside contact structure and the second etch stop layer.

5. The semiconductor device according to claim 4, wherein: The backside contact structure penetrates the second etch stop layer to be formed on the bottom surface of the first source / drain region.

6. The semiconductor device according to claim 4, wherein: The substrate layer includes silicon, and each of the backside spacer and the first etch stop layer includes silicon nitride or a composite thereof.

7. The semiconductor device according to claim 4, wherein: The second etch stop layer includes a material having an etch selectivity with respect to the backside spacer and the first etch stop layer.

8. The semiconductor device according to claim 7, wherein: The material of the second etch stop layer includes aluminum oxide or aluminum nitride.

9. The semiconductor device according to claim 1, wherein: The backside contact structure is formed on side surfaces and a bottom surface of the backside spacer and a bottom surface of a portion of the first etch stop layer.

10. The semiconductor device according to claim 4, further comprising: a second source / drain region on the channel structure; as well as A front side contact structure is provided on a top surface of the second source / drain region.

11. The semiconductor device according to claim 10, wherein: The second etch stop layer is formed on a bottom surface of the second source / drain region.

12. The semiconductor device according to claim 11, further comprising a backside isolation structure on the backside contact structure and the second etch stop layer, in, No placeholder structure is formed in the backside isolation structure below the second source / drain region.

13. A semiconductor device comprising: Channel structure; a gate structure on the channel structure; a first source / drain region and a second source / drain region connected by the channel structure; a backside contact structure on a bottom surface of the first source / drain region; a front side contact structure on a top surface of the second source / drain region; as well as A second etch stop layer is on a bottom surface of the second source / drain region.

14. The semiconductor device according to claim 13, further comprising a backside isolation structure on the backside contact structure and the second etch stop layer, in, No placeholder structure is formed in the backside isolation structure below the second source / drain region.

15. The semiconductor device according to claim 13, further comprising: a substrate layer on a bottom surface of the gate structure; a first etch stop layer on a bottom surface of the substrate layer; as well as A backside spacer is between an upper portion of the backside contact structure and the substrate layer.

16. The semiconductor device according to claim 15, wherein: In a direction in which the gate structure, the substrate layer, the first etch stop layer, and the second etch stop layer are arranged, the substrate layer has a smaller thickness than the backside spacer.

17. A method for manufacturing a semiconductor device; forming a channel structure on a substrate and forming a gate structure on the channel structure; forming a placeholder recess in the substrate; forming a backside spacer on a side surface of the placeholder recess; forming a first source / drain region on the channel structure; forming a substrate layer from the substrate below the gate structure, such that the substrate layer is disposed on a first side of the backside spacer; forming a first etch stop layer below the substrate layer on the first side of the backside spacer; as well as A backside contact structure is formed in the placeholder recess such that the backside contact structure is isolated from the substrate layer by the backside spacer and the first etch stop layer.

18. The method according to claim 17, wherein: Forming the backside contact structure is performed such that an upper portion of the backside contact structure is formed on a second side of the backside spacer opposite the first side.

19. The method according to claim 17, further comprising: forming a second etch stop layer on a bottom surface of the first etch stop layer, a bottom surface of the backside spacer, a bottom surface of the first source / drain region, and a side surface of the backside spacer; forming a backside isolation structure on the second etch stop layer; as well as The backside isolation structure is patterned based on the second etch stop layer to expose the bottom surface of the first source / drain region and the side surface of the backside spacer.

20. The method according to claim 17, wherein: The substrate layer is formed to have a thickness smaller than that of the backside spacer in a direction in which the gate structure, the substrate layer, and the first etch stop layer are arranged.

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