Array substrate and display panel

Abstract

The application provides an array substrate and a display panel. The array substrate comprises a substrate, a first transistor and a second transistor arranged on the substrate. The mobility of a first active layer of the first transistor is different from the mobility of a second active layer of the second transistor. At most one gate insulating layer is arranged between the first active layer and the second active layer. The first active layer is located in a non-perpendicular direction of the second active layer. One of a first gate, the first active layer and a first source of the first transistor is arranged in the same layer as a second gate of the second transistor. The first source and a first drain of the first transistor are arranged in the same layer as a second source and a second drain of the second transistor. Thus, by sharing part of the film layers of the first transistor and the second transistor, the film layer structure can be simplified, the stability of the device can be improved, and the yield can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND

[0002] Hybrid device technology is a new type of backplane technology, which has high research and application value. With the continuous development and maturity of technology, Hybrid device technology is expected to become one of the mainstream display technologies in the future. However, the array substrate using Hybrid device technology is provided with a plurality of TFTs of different types, resulting in a complex film layer structure, poor device stability and high difficulty in mass production. SUMMARY

[0003] The present application provides an array substrate and a display panel to alleviate the technical problem of complex film layer structure when a plurality of transistors of different types are provided on the array substrate.

[0004] To solve the above problems, the technical scheme provided by the present application is as follows:

[0005] The array substrate provided by the present application comprises a substrate and a first transistor and a second transistor provided on the substrate.

[0006] The first transistor comprises a first active layer, a first gate, a first source and a first drain.

[0007] The second transistor comprises a second active layer, a second gate, a second source and a second drain.

[0008] The mobility of the first active layer is different from the mobility of the second active layer, at most one gate insulating layer is provided between the first active layer and the second active layer, the first active layer is located in a non-perpendicular direction of the second active layer, one of the first gate, the first active layer and the first source is provided in the same layer as the second gate, and the first source, the first drain, the second source and the second drain are provided in the same layer.

[0009] In the array substrate provided by the present application, the materials of the first active layer and the second active layer both comprise metal oxide semiconductor material.

[0010] In the array substrate provided by the present application, the second active layer is located on the side of the first active layer away from the substrate, a first gate insulating layer is provided between the first active layer and the second active layer, and the second source and the second drain are located on the side of the second active layer away from the first active layer.

[0011] In the array substrate provided by the embodiment of the present application, the first gate and the first source are arranged in the same layer, the second gate and the first active layer are arranged in the same layer, and the first source and the first drain are located on the side of the first gate insulating layer away from the first active layer.

[0012] In the array substrate provided by the embodiment of the present application, the first source includes a source part and a first bridging part connected with the source part, the first drain includes a drain part and a second bridging part connected with the drain part, the source part connects the first bridging part and the first active layer, and the drain part connects the second bridging part and the first active layer.

[0013] The first bridging part and the second bridging part are arranged in the same layer as the second source, and the second gate is arranged in the same layer as the source part and the drain part.

[0014] In the array substrate provided by the embodiment of the present application, the array substrate further includes a second gate insulating layer, the second gate insulating layer is located on the side of the second active layer away from the first active layer, the first gate is located between the first gate insulating layer and the second gate insulating layer, the second gate is located on the side of the second gate insulating layer away from the second active layer, and the second gate is arranged in the same layer as the second source.

[0015] In the array substrate provided by the embodiment of the present application, the first source includes a source part and a first bridging part connected with the source part, the first drain includes a drain part and a second bridging part connected with the drain part, the source part, the drain part and the first gate are arranged in the same layer, and the first bridging part and the second bridging part are arranged in the same layer as the second gate.

[0016] In the array substrate provided by the embodiment of the present application, the array substrate further includes a first light shielding part and a second light shielding part, the first light shielding part is located on the side of the first active layer close to the substrate and is arranged correspondingly to the first active layer, and the second light shielding part is arranged in the same layer as the first active layer and is arranged correspondingly to the second active layer.

[0017] In the array substrate provided by the embodiment of the present application, the array substrate further includes a second gate insulating layer, the second gate insulating layer is located on the side of the first active layer away from the second active layer, the first gate is located on the side of the second gate insulating layer away from the first active layer, the second gate is located between the first gate insulating layer and the second gate insulating layer, and the second gate is arranged in the same layer as the first active layer.

[0018] In the array substrate provided in the embodiments of the present application, the array substrate further comprises a second gate insulating layer, the second gate insulating layer is located on a side of the first active layer away from the second active layer, the first gate electrode is located on a side of the second gate insulating layer away from the first active layer, and the second gate electrode is located between the first gate insulating layer and the second gate insulating layer.

[0019] The first source electrode comprises a source electrode part and a first bridge part connected to the source electrode part, the first drain electrode comprises a drain electrode part and a second bridge part connected to the drain electrode part, the source electrode part and the drain electrode part are disposed in the same layer as the second gate electrode, and the first bridge part and the second bridge part are disposed in the same layer as the second source electrode.

[0020] In the array substrate provided in the embodiments of the present application, the first active layer and the second active layer are disposed in the same layer, a first gate insulating layer is disposed between the first gate electrode and the first active layer, the first gate electrode is disposed in the same layer as the second gate electrode, the second gate electrode is disposed in the same layer as the second source electrode, and the second source electrode is located on a side of the first gate insulating layer away from the second active layer.

[0021] In the array substrate provided in the embodiments of the present application, the first active layer and the second active layer are disposed in the same layer, a first gate insulating layer is disposed between the first gate electrode and the first active layer, the first gate electrode is disposed in the same layer as the second gate electrode, and the first source electrode is located on a side of the first active layer away from the first gate electrode.

[0022] The embodiments of the present application further provide a display panel comprising the array substrate of any one of the foregoing embodiments.

[0023] The array substrate and the display panel provided in the present application have the following beneficial effects: the array substrate comprises a substrate and a first transistor and a second transistor disposed on the substrate, the mobility of a first active layer of the first transistor is different from the mobility of a second active layer of the second transistor, at most one gate insulating layer is disposed between the first active layer and the second active layer, the first active layer is located in a non-perpendicular direction of the second active layer, one of a first gate electrode, the first active layer and a first source electrode of the first transistor is disposed in the same layer as a second gate electrode of the second transistor, and a first source electrode and a first drain electrode of the first transistor are disposed in the same layer as a second source electrode and a second drain electrode of the second transistor; in this way, by sharing part of the film layers of the first transistor and the second transistor, the film layer structure can be simplified, the stability of the device can be improved, and the yield can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following will briefly introduce the drawings needed to be used in the description of the embodiments or the prior art. Obviously, the drawings described below only show some of the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative effort.

[0025] Figure 1 The first cross-sectional structure schematic diagram of the array substrate provided by the embodiment of the present application.

[0026] Figure 2 The second cross-sectional structure schematic diagram of the array substrate provided by the embodiment of the present application.

[0027] Figure 3 The third cross-sectional structure schematic diagram of the array substrate provided by the embodiment of the present application.

[0028] Figure 4 The fourth cross-sectional structure schematic diagram of the array substrate provided by the embodiment of the present application.

[0029] Figure 5 The fifth cross-sectional structure schematic diagram of the array substrate provided by the embodiment of the present application.

[0030] Figure 6 The sixth cross-sectional structure schematic diagram of the array substrate provided by the embodiment of the present application.

[0031] Figure 7 The seventh cross-sectional structure schematic diagram of the array substrate provided by the embodiment of the present application. DETAILED DESCRIPTION

[0032] The following description of the embodiments is with reference to the drawings, which illustrate specific embodiments to which the present application can be put into practice. The directional terms mentioned in the present application, such as [up], [down], [front], [back], [left], [right], [inward], [outward], [lateral] and the like, are only the directions of the drawings for reference. Therefore, the directional terms used are used to illustrate and understand the present application, but not to limit the present application. In the drawings, similar elements are denoted by the same reference numerals. In the drawings, in order to clearly understand and facilitate the description, the thickness of some layers and regions is exaggerated. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited thereto.

[0033] Please refer to Figures 1 to 7 , Figures 1 to 7A partial cross-sectional structure diagram of an array substrate is provided in the embodiments of the present application. The array substrate 100 includes a substrate 10, a first transistor 20 and a second transistor 30 disposed on the substrate 10. The first transistor 20 includes a first active layer 21, a first gate 22, a first source 23 and a first drain 24. The second transistor 30 includes a second active layer 31, a second gate 32, a second source 33 and a second drain 34.

[0034] The mobility of the first active layer 21 is different from the mobility of the second active layer 31, for example, the mobility of the first active layer 21 is greater than the mobility of the second active layer 31, so that the types of the first transistor 20 and the second transistor 30 are different. At most one gate insulating layer is disposed between the first active layer 21 and the second active layer 31, and the first active layer 21 is located in a non-perpendicular direction of the second active layer 31. One of the first gate 22, the first active layer 21 and the first source 23 is disposed in the same layer as the second gate 32, and the first source 23, the first drain 24, the second source 33 and the second drain 34 are disposed in the same layer. In this way, by sharing some film layers of the first transistor 20 and the second transistor 30, the film layer structure can be simplified, the stability of the device can be improved, and the yield can be improved.

[0035] In some embodiments, referring to Figure 1 , Figure 1 A first cross-sectional structure diagram of an array substrate 100 is provided in the embodiments of the present application. The array substrate 100 includes a substrate 10, a first transistor 20 and a second transistor 30 disposed on the substrate 10. The types of the first transistor 20 and the second transistor 30 are different, for example, the first transistor 20 includes a first active layer 21, the second transistor 30 includes a second active layer 31, and the mobility of the first active layer 21 is greater than the mobility of the second active layer 31.

[0036] The materials of the first active layer 21 and the second active layer 31 both include metal oxide semiconductor materials, for example, the materials of the first active layer 21 and the second active layer 31 are the same metal oxide semiconductor material, and doping different elements in the metal oxide semiconductor material can change the mobility of the metal oxide semiconductor material, for example, doping tin elements in the metal oxide semiconductor material of the first active layer 21 can improve the mobility of the first active layer 21.

[0037] The first transistor 20 and the second transistor 30 can be located in the same sub-pixel circuit, or in different sub-pixel circuits, or one of the first transistor 20 and the second transistor 30 is located in a sub-pixel circuit, and the other is located in another circuit, such as a GOA circuit, and the application is not limited thereto, for example, the first transistor 20 and the second transistor 30 are both located in a GOA circuit.

[0038] With reference to Figure 1 The first transistor 20 further includes a first source 23, a first drain 24 and a first gate 22 located on the side of the first active layer 21 away from the substrate 10, and the first gate 22 is provided in the same layer as the first source 23 and the first drain 24. It should be noted that the "same layer" in the present application refers to that in the preparation process, a film layer formed of the same material is patterned to obtain at least two different structures, and the at least two different structures are provided in the same layer. For example, in the present embodiment, the first gate 22, the first source 23 and the first drain 24 are obtained by patterning a same conductive film layer, and the first gate 22 is provided in the same layer as the first source 23 and the first drain 24.

[0039] The second transistor 30 includes a second source 33 and a second drain 34 located on the side of the second active layer 31 away from the substrate 10, and a second gate 32 located on the side of the second active layer 31 close to the substrate 10. The second active layer 31 is located on the side of the first active layer 21 away from the substrate 10. The second source 33 and the second drain 34 are provided in the same layer as the first source 23 and the first drain 24. The second gate 32 is provided in the same layer as the first active layer 21.

[0040] Specifically, a first gate insulating layer 40 is provided between the first active layer 21 and the second active layer 31. The material of the first gate insulating layer 40 includes inorganic materials such as silicon oxide and silicon nitride. The first gate insulating layer 40 covers the first active layer 21 and the second gate 32.

[0041] The second active layer 31, the first source electrode 23, the first drain electrode 24 and the first gate electrode 22 are located on the side of the first gate insulating layer 40 away from the first active layer 21, i.e. on the first gate insulating layer 40. The first source electrode 23 and the first drain electrode 24 are connected to the first active layer 21 through vias on the first gate insulating layer 40. The first gate electrode 22 is arranged corresponding to the channel portion of the first active layer 21. The second gate electrode 32 is arranged corresponding to at least the channel portion of the second active layer 31. The second source electrode 33 and the second drain electrode 34 are located on the side of the second active layer 31 away from the first active layer 21. The second source electrode 33 and the second drain electrode 34 are directly overlapped with the second active layer 31.

[0042] In some embodiments, the array substrate 100 further comprises a first light shielding portion 25 located on the side of the first active layer 21 close to the substrate 10, i.e. between the first active layer 21 and the substrate 10. The first light shielding portion 25 is arranged corresponding to the first active layer 21 for shielding light from the first active layer 21. The material of the first light shielding portion 25 comprises a metal material with light shielding function or a non-metal material with light shielding performance, such as a black matrix.

[0043] The first light shielding portion 25 is arranged on the substrate 10. The array substrate 100 further comprises a buffer layer 11 covering the first light shielding portion 25 and the substrate 10. The first active layer 21 is located on the side of the buffer layer 11 away from the first light shielding portion 25, i.e. on the buffer layer 11.

[0044] Optionally, the substrate 10 can be a rigid substrate or a flexible substrate. When the substrate 10 is a rigid substrate, it can comprise a glass substrate, a quartz substrate or a silicon wafer, etc. When the substrate 10 is a flexible substrate, it can comprise a polyimide (PI) film, an ultra-thin glass film, etc.

[0045] The buffer layer 11 can prevent the diffusion of undesired impurities or contaminants (e.g. moisture, oxygen, etc.) from the substrate 10 to devices that can be damaged by these impurities or contaminants, and can also provide a flat top surface. The buffer layer 11 can be silicon nitride (SiNx), silicon oxide (SiOx) or a stack of silicon nitride and silicon oxide.

[0046] The array substrate 100 further includes a passivation layer 12 covering the first transistor 20 and the second transistor 30. Specifically, the passivation layer 12 covers the first source electrode 23, the first drain electrode 24, the first gate electrode 22, the second source electrode 33, the second drain electrode 34, a portion of the second active layer 31, and a portion of the second gate insulation layer 50. The passivation layer 12 is used to protect the first transistor 20 and the second transistor 30 and to help smooth out any uneven topography on the top surfaces of the first transistor 20 and the second transistor 30.

[0047] Of course, the array substrate 100 may further include a planarization layer, an electrode layer, etc., located on a side of the passivation layer 12 away from the first transistor 20 and the second transistor 30. The planarization layer covers the passivation layer 12 to flatten the undulating topography of the top surfaces of the first transistor 20 and the second transistor 30. The electrode layer is disposed on the planarization layer and is connected to the first transistor 20 or the second transistor 30 through vias in the planarization layer.

[0048] In this embodiment, the first transistor 20 and the second transistor 30 share a first gate insulating layer 40, which not only simplifies the film layer structure, but also facilitates device debugging and improves yield. Moreover, the second gate 32 of the second transistor 30 is arranged on the same layer as the first active layer 21 of the first transistor 20, and the second source 33 and the second drain 34 of the second transistor 30 are arranged on the same layer as the first source 23, the first drain 24 and the first gate 22 of the first transistor 20, thereby further simplifying the film layer structure of the array substrate 100, improving the stability of the device and improving the yield.

[0049] In some embodiments, reference Figure 2 , Figure 2 This is a schematic diagram of a second cross-sectional structure of the array substrate 100 provided in an embodiment of the present application. Figure 1 The difference of the exemplary array substrate 100 is that the first source electrode 23 includes a source portion 231 and a first bridge portion 232 connected to the source portion 231, and the first drain electrode 24 includes a drain portion 241 and a second bridge portion 242 connected to the drain portion 241. The source portion 231 connects the first bridge portion 232 and the first active layer 21, and the drain portion 241 connects the second bridge portion 242 and the first active layer 21. The first bridge portion 232 and the second bridge portion 242 are provided on the same layer as the second source electrode 33, and the second gate electrode 32 is provided on the same layer as the source portion 231 and the drain portion 241.

[0050] Specifically, the source portion 231 and the drain portion 241 are directly overlapped on the first active layer 21. The first gate insulating layer 40 covers the source portion 231, the drain portion 241, a portion of the first active layer 21, and a portion of the buffer layer 11. The first bridge portion 232 and the second bridge portion 242 are both located on a side of the first gate insulating layer 40 away from the first active layer 21. The first bridge portion 232 is connected to the source portion 231 through a via hole in the first gate insulating layer 40, and the second bridge portion 242 is connected to the drain portion 241 through a via hole in the first gate insulating layer 40.

[0051] The second gate 32 is provided in the same layer as the source portion 231 and the drain portion 241. In this case, the second gate 32 not only serves as the gate of the second transistor 30, but also shields the second active layer 31 of the second transistor 30 from light. The second source 33 and the second drain 34 are provided in the same layer as the first bridge portion 232, the second bridge portion 242, and the first gate 22.

[0052] In some embodiments, reference Figure 3 , Figure 3 This is a schematic diagram of a third cross-sectional structure of the array substrate 100 provided in an embodiment of the present application. Figure 1 The difference of the exemplary array substrate 100 is that the array substrate 100 further includes a second gate insulating layer 50, which is located on a side of the second active layer 31 away from the first active layer 21. The first gate electrode 22 is located between the first gate insulating layer 40 and the second gate insulating layer 50. The second gate electrode 32 is located on a side of the second gate insulating layer 50 away from the second active layer 31. The second gate electrode 32 is provided on the same layer as the second source electrode 33. The second gate insulating layer 50 covers the second active layer 31, and the second source electrode 33 and the second drain electrode 34 are respectively connected to the second active layer 31 through vias in the second gate insulating layer 50.

[0053] The first source 23 includes a source portion 231 and a first bridge portion 232 connected to the source portion 231. The first drain 24 includes a drain portion 241 and a second bridge portion 242 connected to the drain portion 241. The source portion 231 and the drain portion 241 are arranged on the same layer as the first gate 22. The first bridge portion 232 and the second bridge portion 242 are arranged on the same layer as the second gate 32.

[0054] The source electrode portion 231 and the drain electrode portion 241 are located on a side of the first gate insulating layer 40 away from the first active layer 21. The source electrode portion 231 and the drain electrode portion 241 are respectively connected to the first active layer 21 through via holes in the first gate insulating layer 40. The second gate insulating layer 50 also covers the source electrode portion 231 and the drain electrode portion 241.

[0055] The first bridge portion 232 and the second bridge portion 242 are located on a side of the second gate insulating layer 50 away from the first gate insulating layer 40. The first bridge portion 232 and the second bridge portion 242 are respectively connected to the source portion 231 and the drain portion 241 through via holes in the second gate insulating layer 50, such that the source portion 231 is connected between the first bridge portion 232 and the first active layer 21, and the drain portion 241 is connected between the second bridge portion 242 and the first active layer 21.

[0056] Optionally, the array substrate 100 further includes a first light-shielding portion 25 and a second light-shielding portion 35, wherein the first light-shielding portion 25 is located on a side of the first active layer 21 close to the substrate 10 and is arranged corresponding to the first active layer 21, and the second light-shielding portion 35 is arranged on the same layer as the first active layer 21 and is arranged corresponding to the second active layer 31.

[0057] In some embodiments, reference Figure 4 , Figure 4 This is a schematic diagram of a fourth cross-sectional structure of the array substrate 100 provided in an embodiment of the present application. Figure 1 The difference of the exemplary array substrate 100 is that the array substrate 100 further includes a second gate insulating layer 50, the second gate insulating layer 50 is located on the side of the first active layer 21 away from the second active layer 31, the first gate 22 is located on the side of the second gate insulating layer 50 away from the first active layer 21, the second gate 32 is located between the first gate insulating layer 40 and the second gate insulating layer 50, and the second gate 32 is arranged on the same layer as the first active layer 21.

[0058] In some embodiments, reference Figure 5 , Figure 5 This is a schematic diagram of the fifth cross-sectional structure of the array substrate 100 provided in an embodiment of the present application. Figure 1 The difference of the exemplary array substrate 100 is that the array substrate 100 further includes a second gate insulating layer 50, the second gate insulating layer 50 is located on the side of the first active layer 21 away from the second active layer 31, the first gate 22 is located on the side of the second gate insulating layer 50 away from the first active layer 21, and the second gate 32 is located between the first gate insulating layer 40 and the second gate insulating layer 50.

[0059] The first source 23 includes a source portion 231 and a first bridge portion 232 connected to the source portion 231. The first drain 24 includes a drain portion 241 and a second bridge portion 242 connected to the drain portion 241. The source portion 231, the drain portion 241 and the second gate 32 are arranged on the same layer, and the first bridge portion 232 and the second bridge portion 242 are arranged on the same layer as the second source 33.

[0060] In some embodiments, reference Figure 6 , Figure 6 This is a sixth cross-sectional structural diagram of the array substrate 100 provided in an embodiment of the present application. Figure 1 The difference of the exemplary array substrate 100 is that the first active layer 21 and the second active layer 31 are arranged in the same layer, a first gate insulation layer 40 is arranged between the first gate 22 and the first active layer 21, the first gate 22 and the second gate 32 are arranged in the same layer, the second gate 32 and the second source 33 are arranged in the same layer, and the second source 33 is located on the side of the first gate insulation layer 40 away from the second active layer 31.

[0061] In some embodiments, reference Figure 7 , Figure 7 This is a seventh cross-sectional structural diagram of the array substrate 100 provided in an embodiment of the present application. Figure 1 The difference of the exemplary array substrate 100 is that the first active layer 21 and the second active layer 31 are arranged in the same layer, a first gate insulation layer 40 is arranged between the first gate 22 and the first active layer 21, the first gate 22 and the second gate 32 are arranged in the same layer, and the first source 23 is located on the side of the first active layer 21 away from the first gate 22.

[0062] Based on the same inventive concept, an embodiment of the present application further provides a display panel, which includes the array substrate described in one of the aforementioned embodiments. The display panel can be a light emitting diode display panel or a liquid crystal display panel.

[0063] According to the above embodiments, it can be seen that:

[0064] The application provides an array substrate and a display panel, the array substrate comprises a substrate, a first transistor and a second transistor arranged on the substrate, the mobility of a first active layer of the first transistor is different from the mobility of a second active layer of the second transistor, at most one gate insulating layer is arranged between the first active layer and the second active layer, the first active layer is located in a non-perpendicular direction of the second active layer, one of a first gate, the first active layer and a first source of the first transistor is arranged in the same layer as a second gate of the second transistor, the first source and a first drain of the first transistor are arranged in the same layer as a second source and a second drain of the second transistor; in this way, by sharing part of film layers of the first transistor and the second transistor, the film layer structure can be simplified, the stability of the device can be improved, and the yield can be improved.

[0065] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0066] The embodiments of the application are described in detail above, and the principle and implementation mode of the application are described by applying specific examples; the above embodiment description is only used to help understand the technical scheme of the application and its core idea; the person skilled in the art should understand that the technical scheme recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical scheme deviate from the scope of the technical scheme of the embodiments of the application.

Claims

1. An array substrate, characterized in that: comprising a substrate and a first transistor and a second transistor disposed on the substrate; The first transistor includes a first active layer, a first gate, a first source and a first drain; The second transistor includes a second active layer, a second gate, a second source and a second drain; The mobility of the first active layer is different from the mobility of the second active layer, at most one gate insulating layer is provided between the first active layer and the second active layer, the first active layer is located in a non-vertical direction of the second active layer, one of the first gate, the first active layer, and the first source is provided in the same layer as the second gate, and the first source, the first drain, the second source, and the second drain are provided in the same layer; The second active layer is located on a side of the first active layer away from the substrate, a first gate insulating layer is provided between the first active layer and the second active layer, and the second source electrode and the second drain electrode are located on a side of the second active layer away from the first active layer; The first gate is provided in the same layer as the first source, the second gate is provided in the same layer as the first active layer, and the first source and the first drain are located on a side of the first gate insulating layer away from the first active layer.

2. The array substrate according to claim 1, wherein: Materials of the first active layer and the second active layer both include metal oxide semiconductor materials.

3. The array substrate according to claim 1, wherein: The first source electrode includes a source portion and a first bridge portion connected to the source portion, the first drain electrode includes a drain portion and a second bridge portion connected to the drain portion, the source portion connects the first bridge portion and the first active layer, and the drain portion connects the second bridge portion and the first active layer; The first bridge portion and the second bridge portion are provided in the same layer as the second source electrode, and the second gate electrode is provided in the same layer as the source electrode portion and the drain electrode portion.

4. The array substrate according to claim 1, wherein: The array substrate also includes a second gate insulating layer, which is located on a side of the second active layer away from the first active layer, the first gate is located between the first gate insulating layer and the second gate insulating layer, the second gate is located on a side of the second gate insulating layer away from the second active layer, and the second gate is arranged on the same layer as the second source.

5. The array substrate according to claim 4, wherein: The first source includes a source portion and a first bridge portion connected to the source portion, the first drain includes a drain portion and a second bridge portion connected to the drain portion, the source portion, the drain portion and the first gate are arranged on the same layer, and the first bridge portion and the second bridge portion are arranged on the same layer as the second gate.

6. The array substrate according to claim 4, wherein: The array substrate also includes a first light-shielding portion and a second light-shielding portion. The first light-shielding portion is located on a side of the first active layer close to the substrate and is arranged corresponding to the first active layer. The second light-shielding portion is arranged in the same layer as the first active layer and is arranged corresponding to the second active layer.

7. The array substrate according to claim 1, wherein: The array substrate also includes a second gate insulating layer, which is located on a side of the first active layer away from the second active layer, the first gate is located on a side of the second gate insulating layer away from the first active layer, the second gate is located between the first gate insulating layer and the second gate insulating layer, and the second gate is arranged on the same layer as the first active layer.

8. The array substrate according to claim 1, wherein: The array substrate further includes a second gate insulating layer, the second gate insulating layer is located on a side of the first active layer away from the second active layer, the first gate is located on a side of the second gate insulating layer away from the first active layer, and the second gate is located between the first gate insulating layer and the second gate insulating layer; The first source includes a source portion and a first bridge portion connected to the source portion, the first drain includes a drain portion and a second bridge portion connected to the drain portion, the source portion, the drain portion and the second gate are arranged on the same layer, and the first bridge portion and the second bridge portion are arranged on the same layer as the second source.

9. The array substrate according to claim 1, wherein: The first active layer and the second active layer are arranged in the same layer, a first gate insulation layer is arranged between the first gate and the first active layer, the first gate and the second gate are arranged in the same layer, the second gate and the second source are arranged in the same layer, and the second source is located on a side of the first gate insulation layer away from the second active layer.

10. The array substrate according to claim 1, wherein: The first active layer and the second active layer are arranged in the same layer, a first gate insulating layer is arranged between the first gate and the first active layer, the first gate and the second gate are arranged in the same layer, and the first source is located on a side of the first active layer away from the first gate.

11. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 10.

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