Memory device and method for implementing multi-level memory using same

Abstract

A memory device for implementing a multi-level memory and a method for implementing a multi-level memory by using the memory device are provided. The memory device includes: a first electrode and a second electrode separated from each other; a self-selective memory layer between the first electrode and the second electrode, having a bi-directional threshold switching characteristic, comprising a chalcogenide-based material, and configured to have a threshold voltage that varies depending on the polarity and intensity of a voltage applied thereto; and a resistive memory layer between the second electrode and the self-selection memory layer and having a resistance characteristic that varies depending on a voltage applied thereto. The memory device is configured to implement a multi-level resistance state by changing at least one of a pulse polarity, a number of pulses, a pulse height, and a pulse width of a voltage applied between the first electrode and the second electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority of Korean Patent Application No. 10-2023-0150293 filed on November 2, 2023, and Korean Patent Application No. 10-2024-0042003 filed on March 27, 2024, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] Various example embodiments generally relate to a memory device for implementing a multi-level memory and / or a method of implementing a multi-level memory by using a memory device. Background Art

[0004] As electronic products have become more lightweight and compact, the demand or expectation for high integration of memory devices has increased. A cross-point memory device has a structure in which word lines and bit lines cross each other vertically and memory cells are arranged at the intersection area. This structure has the advantage of having a small memory cell in a plan view. Typically, the memory cell of a cross-point memory device includes a 2-terminal selector and a memory device connected in series to prevent sneak currents between adjacent memory cells. Recently, a self-selecting memory (SSM) device that serves as both a selector and a memory device has been developed. Summary of the invention

[0005] Provided are a memory device for implementing a multi-level memory and / or a method for implementing a multi-level memory by using the memory device.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the various exemplary embodiments.

[0007] According to some example embodiments, a memory device includes: a first electrode and a second electrode separated from each other; a self-selection memory layer between the first electrode and the second electrode, and including a chalcogenide-based material, having a bidirectional threshold switching characteristic, and configured to have a threshold voltage that varies depending on the polarity and intensity of a voltage applied thereto; and a resistive memory layer between the second electrode and the self-selection memory layer and having a resistance characteristic that varies depending on the voltage applied thereto. The memory device is configured to achieve a multi-level resistance state by changing at least one of a pulse polarity, a pulse number, a pulse height, and a pulse width of a voltage applied between the first electrode and the second electrode.

[0008] Alternatively or additionally, according to various example embodiments, there is provided a method for realizing a multi-level memory by using a memory device, the memory device comprising: a first electrode and a second electrode separated from each other; a self-selection memory layer between the first electrode and the second electrode, comprising a chalcogenide-based material, having a bidirectional threshold switching characteristic, and configured to have a threshold voltage that varies depending on the polarity and intensity of a voltage applied thereto; and a resistive memory layer between the second electrode and the self-selection memory layer and having a resistance characteristic that varies depending on the voltage applied thereto. The method comprises: realizing a multi-level resistance state by changing at least one of a pulse polarity, a pulse number, a pulse height, and a pulse width of a voltage applied between the first electrode and the second electrode.

[0009] Alternatively or additionally, according to various example embodiments, a memory device includes: a plurality of bit lines; a plurality of word lines intersecting the plurality of bit lines; and a plurality of memory cells at locations where the plurality of bit lines and the plurality of word lines intersect each other. Each of the plurality of memory cells includes: a first electrode and a second electrode separated from each other; a self-selection memory layer between the first electrode and the second electrode, including a chalcogenide-based material, having a bidirectional threshold switching characteristic, and configured to have a threshold voltage that varies depending on the polarity and intensity of a voltage applied thereto; and a resistive memory layer between the second electrode and the self-selection memory layer and having a resistance characteristic that varies depending on the voltage applied thereto. The memory device is configured to realize a multi-level resistance state by changing at least one of a pulse polarity, a pulse number, a pulse height, and a pulse width of a voltage applied between the first electrode and the second electrode.

[0010] Alternatively or additionally, the multi-level memory device includes: a self-selection memory device having a bidirectional threshold switching characteristic and having a threshold voltage that varies depending on the polarity and strength of a voltage applied thereto; a resistive memory device that is connected in series to the self-selection memory device and has a resistance characteristic that varies depending on the voltage applied thereto; and a memory controller configured to change the height of a pulse voltage of a negative (-) polarity applied to the self-selection memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of certain example embodiments will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0012] Figure 1 schematically illustrates a cross-section of a memory device according to some example embodiments;

[0013] Figure 2 It is shown Figure 1 A graph showing voltage-current characteristics of a self-select memory layer;

[0014] Figure 3A is shown applied to Figure 1 A graph of bias voltages for a set (SET) operation and a read operation of a self-select memory layer is shown;

[0015] Figure 3B is shown for application to Figure 1 A graph of bias voltages for a reset (RESET) operation and a read operation of a self-selected memory layer is shown;

[0016] Figure 4 is shown depending on the applied Figure 1 A graph showing voltage-current characteristics of the magnitude (intensity) of a write voltage of a self-selected memory layer;

[0017] Figure 5 shows that depending on the application Figure 1 The change in threshold voltage according to the number of pulses of the write voltage of the self-selected memory layer is shown;

[0018] Figure 6 It shows that depending on Figure 1 The change of the threshold voltage of the pulse width of the write voltage in the reset operation of the self-selected memory layer is shown;

[0019] Figure 7 It shows that depending on Figure 1 The change of the threshold voltage according to the pulse width of the write voltage in the set operation of the self-selected memory layer is shown;

[0020] Fig. 8A and 8B is shown depending on the application to Figure 1 A graph showing current characteristics of a write voltage pulse number of a resistive memory layer;

[0021] Fig.9A and 9B is shown depending on the applied Figure 1 A graph showing current characteristics of a pulse height of a write voltage for a resistive memory layer;

[0022] Fig. 10A and 10B is shown depending on the application to Figure 1 A graph showing current characteristics of a pulse width of a write voltage for a resistive memory layer;

[0023] Fig.11 Schematically shows the dependence of the applied Figure 1 The change in resistance of the memory device shown with the pulse height and the number of pulses of the write voltage;

[0024] Fig.12 Schematically shows the dependence of the applied Figure 1 The resistance variation of the pulse height and pulse width of the write voltage of the memory device shown;

[0025] Fig.13 Schematically shows the dependence of the applied Figure 1 Changes in resistance of the pulse height, pulse number and pulse width of the write voltage of the memory device shown;

[0026] Fig.14 is a block diagram illustrating a schematic configuration of a memory device according to some example embodiments;

[0027] Fig.15 schematically illustrates a cross-section of a memory device according to some example embodiments;

[0028] Fig.16 is a perspective view schematically illustrating a memory device according to some example embodiments;

[0029] Fig.17 yes Fig.16 An enlarged view of one memory cell in the memory device is shown;

[0030] Fig.18 It is shown in Fig.16 A plan view of the operation of selecting a specific memory cell in the memory device shown;

[0031] Fig.19 is a cross-sectional view schematically illustrating a multi-layer memory device according to some example embodiments;

[0032] Fig. 20 is a conceptual diagram schematically illustrating a device architecture applicable to an electronic apparatus according to some example embodiments;

[0033] Fig.21 is a block diagram of a memory system according to some example embodiments; and

[0034] Fig. 22 is a block diagram illustrating a neuromorphic device and external devices connected thereto, according to some example embodiments. DETAILED DESCRIPTION

[0035] Reference will now be made in detail to an embodiment, examples of which are shown in the accompanying drawings, wherein the same reference numerals represent the same elements throughout. In this respect, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain various aspects. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. Expressions such as "at least one of ... " modify the entire element list when it is before the element list, rather than modifying the individual elements in the list.

[0036] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings will represent the same elements, and the sizes of the elements in the drawings may be exaggerated for the sake of clarity and convenience of description. The embodiments described below are merely examples, and various modifications may be made therein.

[0037] As used herein, the term “on” or “on” may include not only “directly on” or “directly on” but also “indirectly on” or “indirectly on”. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. In addition, when something is referred to as “comprising” a component, it may further include another component unless otherwise indicated.

[0038] The use of the terms "a", "an", and "the" and other similar indicative terms may be interpreted to cover both the singular and the plural. Unless there is an explicit order or description to the contrary, the operations constituting the method may be performed in a suitable order and are not necessarily limited to the order described.

[0039] Furthermore, as used herein, the terms “unit” and “module” may refer to a unit that performs at least one function or operation, and the unit may be implemented as hardware or software or a combination of hardware and software.

[0040] The wiring connections or connecting means between elements shown in the drawings may illustratively represent functional connections and / or physical or logical connections, and may represent various alternative or additional functional connections, physical connections or logical connections in an actual device.

[0041] All examples or illustrative terms used herein are intended only to describe the technical concepts of the present disclosure in detail, and the scope of the present disclosure is not limited by these examples or illustrative terms unless otherwise defined in the accompanying claims.

[0042] Figure 1 A cross section of a memory device 100 according to some example embodiments is schematically illustrated.

[0043] refer to Figure 1 The memory device 100 may include a first electrode 110 and a second electrode 120 arranged separately from each other, a self-selection memory layer 140 arranged between the first electrode 110 and the second electrode 120 , and a resistive memory layer 150 arranged between the second electrode 120 and the self-selection memory layer 140 .

[0044] The first electrode 110 and the second electrode 120 may be used to apply a voltage to the self-selection memory layer 140 and the resistive memory layer 150. To this end, each of the first electrode 110 and the second electrode 120 may include a metal, a conductive metal nitride, a conductive metal oxide, or any combination thereof. For example, each of the first electrode 110 and the second electrode 120 may include at least one or any combination of the following: titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), titanium carbon silicon nitride (TiCSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), tungsten silicide (WSi), titanium tungsten (TiW), molybdenum nitride (MoN), niobium nitride (NbN), titanium nitride Boron (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum aluminum nitride (MoAlN), titanium aluminum (TiAl), titanium oxynitride (TiON), titanium aluminum oxynitride (TiAlON), tungsten oxynitride (WON), tantalum oxynitride (TaON), silicon carbide (SiC), silicon nitride carbon (SiCN), carbon nitride (CN), tantalum nitride carbon (TaCN), tungsten (W), tungsten nitride (WN), and carbon (C). In some cases, the first electrode 110 and the second electrode 120 may include the same material, or different materials, or the same and different materials; example embodiments are not limited thereto.

[0045] In some cases, the third electrode 130 may be arranged between the self-selection memory layer 140 and the resistive memory layer 150. In some example embodiments, the third electrode 1430 may be in the middle between the first electrode 110 and the second electrode 120; however, example embodiments are not limited thereto. The self-selection memory layer 140 and the resistive memory layer 150 may be electrically connected to each other in a series structure. The third electrode 130 may also serve as a diffusion and oxidation prevention (or diffusion and oxygen reduction) layer. For this purpose, the third electrode 130 may include, for example, a carbon-based conductive material (e.g., carbon nitride). However, example embodiments are not limited thereto.

[0046] The first electrode 110, the self-selection memory layer 140, and the third electrode 130 may constitute (or correspond to or be included in) a self-selection memory SSM device. In some cases, the third electrode 130, the resistive memory layer 150, and the second electrode 120 may constitute (or correspond to or be included in) a resistive memory device (resistive random access memory device) ReRAM. For example, the memory device 100 according to various embodiments may have a structure in which the self-selection memory SSM device and the resistive memory device ReRAM are connected in series with each other.

[0047] The self-selection memory layer 140 may have a bidirectional threshold switching (OTS) characteristic, having a high resistance state when a voltage lower than its threshold voltage is applied thereto, and having a low resistance state when a voltage higher than the threshold voltage is applied thereto. In some cases, the self-selection memory layer 140 may have a memory characteristic in which the threshold voltage is shifted according to the polarity and strength (e.g., absolute value) of the bias voltage applied thereto. Therefore, the self-selection memory layer 140 may have the characteristic of performing both a memory function and a selector function.

[0048] The self-selection memory layer 140 may include a chalcogenide-based material. For example, the self-selection memory layer 140 may include a chalcogenide element including at least one of Se, Te, and S, and at least one of Ge, As, and Sb. The self-selection memory layer 140 may also include at least one of In, Al, C, B, Sr, Ga, O, N, Si, Ca, and P. For example, the self-selection memory layer 140 may include at least one of GeAsSe, GeAsSeIn, GeAsSeSIn, GeAsSeSb, GeAsSeTe, GeAsSeAl, GeAsSeAlIn, GeSbSe, GeAsSeGa, GeSe, GeSeIn, GeS, GeSIn, GeCTe, GeCTeN, and GeSbSeN.

[0049] Figure 2 It is shown Figure 1 FIG. 1 is a graph showing voltage-current characteristics of the self-select memory layer 140 .

[0050] refer to Figure 2 , the self-selection memory layer 140 may have any one of a first state (e.g., a low Vth state (LVS)) in which the threshold voltage is relatively low and a second state (e.g., a high Vth state (HVS)) in which the threshold voltage is relatively high. For example, in the first state, the threshold voltage of the self-selection memory layer 140 may be a first voltage V1, and in the second state, the threshold voltage of the self-selection memory layer 140 may be a second voltage V2 that is higher (higher in absolute value) than the first voltage V1.

[0051] In the case where the self-selection memory layer 140 is in the first state, when a voltage lower than the first voltage V1 is applied to the self-selection memory layer 140, almost no current may flow between both ends of the self-selection memory layer 140, and when a voltage higher than the first voltage V1 is applied to the self-selection memory layer 140, the self-selection memory layer 140 may be turned on, so that current may flow through the self-selection memory layer 140. In some examples, in the case where the self-selection memory layer 140 is in the second state, when a voltage lower than the second voltage V2 is applied to the self-selection memory layer 140, almost no current may flow between both ends of the self-selection memory layer 140, and when a voltage higher than the second voltage V2 is applied to the self-selection memory layer 140, the self-selection memory layer 140 may be turned on, so that current may flow through the self-selection memory layer 140.

[0052] Therefore, a voltage between the first voltage V1 and the second voltage V2 may be selected as the read voltage VR. In a case where the self-selection memory layer 140 is in the first state, when the read voltage VR is applied to the self-selection memory layer 140, current may flow through the self-selection memory layer 140, and in this case, the data value stored in the self-selection memory layer 140 may be defined as a first logic value, such as logic “1”. In a case where the self-selection memory layer 140 is in the second state, when the read voltage VR is applied to the self-selection memory layer 140, almost no current may flow through the self-selection memory layer 140, and in this case, the data value stored in the self-selection memory layer 140 may be defined as a second logic value, such as logic “0”. In some example embodiments, when the current flowing through the self-selection memory layer 140 is measured while the read voltage VR is applied to the self-selection memory layer 140, the data value stored in the self-selection memory layer 140 may be read. In some example embodiments, VR may be halfway between V1 and V2; however, example embodiments are not limited thereto, and VR may be greater than a half-way point between V1 and V2 or less than a half-way point between V1 and V2.

[0053] In addition, when the self-selection memory layer 140 is in the first state, when a negative (-) bias voltage is applied to the self-selection memory layer 140, the threshold voltage of the self-selection memory layer 140 may increase, and thus the self-selection memory layer 140 may be converted to the second state. For example, when a negative third voltage V3 is applied to the self-selection memory layer 140, the self-selection memory layer 140 may be converted to the second state. This operation may be referred to as a "reset (RESET)" operation. Alternatively or additionally, when a positive (+) bias voltage higher than the second voltage V2 is applied to the self-selection memory layer 140, the threshold voltage of the self-selection memory layer 140 may be reduced, and thus the self-selection memory layer 140 may be converted to the first state. This operation may be referred to as a "set (SET)" operation. The difference between the second voltage V2 as the reset threshold voltage and the first voltage V1 as the set threshold voltage may correspond to or be referred to as a memory window.

[0054] Figure 3A is shown for application to Figure 1 Graphs of bias voltages for set and read operations of the self-select memory layer 140 are shown.

[0055] refer to Figure 3A , in a set operation, a positive (+) bias voltage higher than the second voltage V2 may be applied to the self-selection memory layer 140. Then, the threshold voltage of the self-selection memory layer 140 may be shifted to the first voltage V1. Thereafter, in a read operation, a positive (+) read voltage VR between the first voltage V1 and the second voltage V2 (e.g., halfway between V1 and V2) may be applied to the self-selection memory layer 140. When the read voltage VR is applied thereto, the self-selection memory layer 140 may be turned on.

[0056] Figure 3B is shown for application to Figure 1 Graphs of bias voltages for a reset operation and a read operation of a self-select memory layer 140 are shown.

[0057] refer to Figure 3B , in a reset operation, a negative (-) bias voltage (e.g., a negative third voltage V3) may be applied to the self-selection memory layer 140. The absolute value of the negative third voltage V3 may be substantially equal to or slightly greater than or less than (the absolute value of) the second voltage V2. Then, the threshold voltage of the self-selection memory layer 140 may be shifted to a second voltage V2 that is higher than the first voltage V1. Thereafter, in a read operation, a positive (+) read voltage VR between the first voltage V1 and the second voltage V2 may be applied to the self-selection memory layer 140. When the read voltage VR is applied thereto, the self-selection memory layer 140 may not be turned on.

[0058] As described above, the self-selection memory layer 140 may have both the OTS characteristic and the memory characteristic in which the threshold voltage is changed. In particular, the threshold voltage of the self-selection memory layer 140 may shift according to the polarity of the bias voltage applied to the self-selection memory layer 140 .

[0059] Figure 4 is shown depending on the applied Figure 1 FIG. 1 is a graph showing voltage-current characteristics of the magnitude or absolute value (intensity) of the write voltage from the selected memory layer 140 .

[0060] refer to Figure 4 , when the write voltage applied to the self-select memory layer 140 is a voltage of positive (+) polarity, the set (SET) threshold voltage may not change even when the amplitude (intensity) of the voltage increases. On the contrary, when the write voltage applied to the self-select memory layer 140 is a voltage of negative (-) polarity, the reset (RESET) threshold voltage may increase as the amplitude (intensity) of the voltage increases. Therefore, by changing the amplitude of the voltage of negative (-) polarity, a multi-level memory can be implemented in the self-select memory layer 140, and in some cases, a single (physical) memory cell can store more than one single bit, for example, 2 or more bits of information. This can help improve the integration density of memory devices.

[0061] Figure 5 shows that depending on the application Figure 1 The change in threshold voltage (Vth) of the selected memory layer 140 according to the number of pulses of the write voltage is shown.

[0062] refer to Figure 5 , when the write voltage applied to the self-select memory layer 140 is a pulse voltage of positive (+) polarity, the set threshold voltage may not change even when the number of pulses increases. Alternatively or additionally, when the write voltage applied to the self-select memory layer 140 is a voltage of negative (-) polarity, the reset threshold voltage may not increase as the number of pulses increases.

[0063] Figure 6 It shows that depending on Figure 1 FIG. 1 shows a change in the threshold voltage (Vth) with respect to the pulse width (pulse time) of the write voltage in the reset operation of the self-selected memory layer 140 . Figure 6 Changes in the threshold voltage depending on the pulse height (pulse amplitude) of the write voltage when the pulse width is 20 ns, 200 ns, 1000 ns, or 2000 ns are shown.

[0064] refer to Figure 6, the threshold voltage may increase as the pulse height of the write voltage increases, but the threshold voltage may hardly change even when the pulse width of the write voltage increases.

[0065] Figure 7 It shows that depending on Figure 1 FIG. 1 is a graph showing a change in threshold voltage (Vth) according to a pulse width of a write voltage in a set operation of the self-select memory layer 140 . Figure 7 A change in the threshold voltage depending on the pulse height of the write voltage when the pulse width is 20 ns, 200 ns, 1000 ns, or 2000 ns is shown.

[0066] refer to Figure 7 , the threshold voltage may not change even when the pulse height of the write voltage increases, and the threshold voltage may hardly change even when the pulse width of the write voltage increases.

[0067] As described above, in the self-selection memory layer 140, when the write voltage is a pulse voltage of positive (+) polarity, the threshold voltage may not change even when any one or more of the pulse height, the number of pulses, and the pulse width changes. Alternatively or additionally, when the write voltage is a pulse voltage of negative (-) polarity, the threshold voltage may change when the pulse height changes, but the threshold voltage may not change even when the number of pulses and / or the pulse width changes. Therefore, when a pulse voltage of negative (-) polarity is applied to the self-selection memory layer 140 as a write voltage and the pulse height of the applied voltage changes, the resistance state of the self-selection memory layer 140 may change.

[0068] Return to reference Figure 1 The resistive memory layer 150 may be disposed between the second electrode 120 and the third electrode 130. The resistive memory layer 150 may include a material whose resistance characteristics change depending on a voltage applied thereto. The resistive memory layer 150 may include, for example, Al 2 O 3 、In 2 O 3 、MgO、MoO 3 、 2 O 5 , HfO 2 、PrCaMnO 3 、TiO 2 、V 2 O 5 Or one or more of ZnO. However, this is only an example.

[0069] The resistance characteristics of the resistive memory layer 150 may depend on whether the conductive filament is formed by the behavior of oxygen in the resistive memory layer 150 according to the applied voltage. In some cases, when a specific voltage is applied to the resistive memory layer 150, oxygen vacancies may be formed in the resistive memory layer 150, and the formed oxygen vacancies may be collected to form the conductive filament. The resistance of the resistive memory layer 150 may be reduced by the formation of the conductive filament. For example, the resistive memory layer 150 may be changed from a high resistance state (HRS) to a low resistance state (LRS).

[0070] Fig. 8A and 8B is shown depending on the application to Figure 1 FIG. 1 is a graph showing the current characteristics of the resistive memory layer 150 as a function of the number of pulses of the write voltage. Figure 8B In the above example, “A” indicates the Fig. 8A The current characteristics of the voltage pulse of negative (-) polarity shown in FIG, and "B" indicates the current corresponding to Fig. 8A The current characteristics of the voltage pulse of positive (+) polarity are shown in FIG.

[0071] Fig. 8A shows the time (t) applied to Figure 1 The resistive memory layer 150 shown has a negative (-) polarity voltage pulse and a positive (+) polarity voltage pulse. Here, the voltage pulses may have the same pulse height (or absolute value of the amplitude) and the same pulse width. In some cases, the duty cycle of the pulse train may be 1:1; however, example embodiments are not limited thereto, and the duty cycle of the pulse train may be less than or greater than 1:1. Figure 8B Shows that Fig. 8A The voltage pulse shown in Figure 1 The current characteristics of the resistive memory layer 150 are shown in FIG. Fig. 8A and Figure 8B , the resistance state of the resistive memory layer 150 may change depending on the number of pulses applied to the resistive memory layer 150. In particular, as the number of voltage pulses of negative (-) polarity increases, the resistance may gradually increase, and as the number of voltage pulses of positive (+) polarity increases, the resistance may gradually decrease.

[0072] Fig.9A and 9B is shown depending on the application to Figure 1 FIG. 1 is a graph showing the current characteristics of the pulse height of the write voltage of the resistive memory layer 150. Fig. 9B In the above example, “A” indicates the Fig.9A The current characteristics of the voltage pulse of negative (-) polarity shown in FIG, and "B" indicates the current corresponding to Fig.9A The current characteristics of the voltage pulse of positive (+) polarity are shown in FIG.

[0073] Fig.9A shows the time (t) applied to Figure 1 The illustrated resistive memory layer 150 has a negative (-) polarity voltage pulse and a positive (+) polarity voltage pulse. Here, the voltage pulses may have the same pulse width and may have a pulse height that increases with time (e.g., linearly and / or in a concave and / or convex manner). Fig. 9B Shows that Fig.9A The voltage pulse shown in Figure 1 The current characteristics of the resistive memory layer 150 are shown in FIG. Fig.9A and Fig. 9B , the resistance state of the resistive memory layer 150 may change depending on the pulse height applied to the resistive memory layer 150. In particular, as the number of voltage pulses of negative (-) polarity increases, the resistance may gradually increase, and as the number of voltage pulses of positive (+) polarity increases, the resistance may gradually decrease. Figure 8B and Fig. 9B , the degree of resistance change as the number of pulses with gradually increasing pulse heights increases may change more linearly than the degree of resistance change as the number of pulses with the same pulse height increases.

[0074] Fig. 10A and 10B is shown depending on the application to Figure 1 FIG. 1 is a graph showing the current characteristics of the pulse width of the write voltage of the resistive memory layer 150. Fig. 10B In the above example, “A” indicates the Fig. 10A The current characteristics of the voltage pulse of negative (-) polarity shown in FIG, and "B" indicates the current corresponding to Fig. 10A The current characteristics of the voltage pulse of positive (+) polarity are shown in FIG.

[0075] Fig. 10A shows the time (t) applied to Figure 1 The resistive memory layer 150 is shown with a negative (-) polarity voltage pulse and a positive (+) polarity voltage pulse. Here, the voltage pulses may have the same pulse height, and may have a varying pulse width, such as a pulse width that increases with time. Fig. 10B Shows that Fig. 10A The voltage pulse shown in Figure 1 The current characteristics of the resistive memory layer 150 are shown in FIG. Fig. 10A and Fig. 10B, the resistance state of the resistive memory layer 150 may change depending on the pulse width applied to the resistive memory layer 150. In particular, as the number of voltage pulses of negative (-) polarity increases, the resistance may gradually increase, and as the number of voltage pulses of positive (+) polarity increases, the resistance may gradually decrease. Figure 8B and Fig. 10B , the degree of resistance change as the number of pulses with gradually increasing pulse widths increases may change more linearly than the degree of resistance change as the number of pulses with the same pulse width increases.

[0076] As described above, in the resistive memory layer 150, when the write voltage is a pulse voltage of positive (+) polarity, the resistance state of the resistive memory layer 150 can be changed when the pulse height, the number of pulses, and the pulse width are changed. Alternatively or additionally, when the write voltage is a pulse voltage of negative (-) polarity, the resistance state of the resistive memory layer 150 can be changed when the pulse height, the number of pulses, and the pulse width are changed.

[0077] As described above, the memory device 100 according to some example embodiments may have a structure in which the self-selection memory layer 140 and the resistive memory layer 150 are connected in series to each other. Therefore, the resistance of the memory device 100 may be determined by the sum of the resistance of the self-selection memory layer 140 and the resistance of the resistive memory layer 150. Hereinafter, a method of implementing a multi-level memory by using the above-described memory device 100 will be described.

[0078] Fig.11 Schematically shows the dependence of the applied Figure 1 The resistance variation of the memory device 100 with respect to the pulse height and the number of pulses of the write voltage is shown. Fig.11 shows a pulse voltage with negative (-) polarity used as Figure 1 The write voltage between the first electrode 110 and the second electrode 120 of the memory device 100 shown in FIG. Fig.11 , “R(SSM)” represents the resistance of the self-select memory layer 140 , and “R(ReRAM)” represents the resistance of the resistive memory layer 150 .

[0079] refer to Fig.11 As the pulse height increases, the resistance R(SSM) of the self-selection memory layer 140 and the resistance R(ReRAM) of the resistive memory layer 150 may increase. In addition, as the number of pulses increases, the resistance R(SSM) of the self-selection memory layer 140 may be constant, but the resistance R(ReRAM) of the resistive memory layer 150 may increase.

[0080] Table 1 shows that when Figure 1The resistance states that can be achieved according to the pulse height and the number of pulses when a pulse voltage of negative (-) polarity is applied between the first electrode 110 and the second electrode 120 of the memory device 100 shown in the figure.

[0081] Table 1 describes the resistance states that can be achieved when the pulse heights are V1, V2, and V3 (where V1 < V2 < V3), and for the corresponding pulse heights, the number of pulses is 1, 2, and 3.

[0082] [Table 1]

[0083]

[0084] Referring to Table 1, when the pulse height is V1, as the number of pulses increases to 1, 2, and 3, the resistance R(SSM) of the self - selective memory layer 140 can all be constant at R(S1), and the resistance R(ReRAM) of the resistive memory layer 150 can change to R(O11), R(O12), and R(O13) (where R(O11) < R(O12) < R(O13)). Therefore, when the pulse height is V1 and the number of pulses becomes 1, 2, and 3, the memory device 100 can achieve three resistance states, namely R(S1)+R(O11), R(S1)+R(O12), and R(S1)+R(O13).

[0085] When the pulse height is V2 (> V1), as the number of pulses increases to 1, 2, and 3, the resistance R(SSM) of the self - selective memory layer 140 can all be constant at R(S2) (> R(S1)), and the resistance R(ReRAM) of the resistive memory layer 150 can change to R(O21), R(O22), and R(O23) (where R(O21) < R(O22) < R(O23)). Therefore, when the pulse height is V2 and the number of pulses becomes 1, 2, and 3, the memory device 100 can achieve three resistance states, namely R(S2)+R(O21), R(S2)+R(O22), and R(S2)+R(O23).

[0086] When the pulse height is V3 (> V2), as the number of pulses increases to 1, 2, and 3, the resistance R(SSM) of the self - selective memory layer 140 can all be constant at R(S3) (> R(S2)), and the resistance R(ReRAM) of the resistive memory layer 150 can change to R(O31), R(O32), and R(O33) (where R(O31) < R(O32) < R(O33)). Therefore, when the pulse height is V3 and the number of pulses becomes 1, 2, and 3, the memory device 100 can achieve three resistance states, namely R(S3)+R(O31), R(S3)+R(O32), and R(S3)+R(O33).

[0087] As described above, when a pulse voltage of negative (-) polarity is applied as a write voltage between the first electrode 110 and the second electrode 120 of the memory device 100, the memory device 100 can achieve up to nine resistance states when using three pulse heights and three pulses. Therefore, when using "n" pulse heights and "m" pulses, the memory device 100 can achieve up to (n × m) resistance states.

[0088] Fig.12 Schematically shows the resistance change depending on the pulse height and pulse width of the write voltage applied to Figure 1 the memory device 100 shown. Fig.12 Shows the case where a pulse voltage of negative (-) polarity is used as Figure 1 the write voltage between the first electrode 110 and the second electrode 120 of the memory device 100 shown in

[0089] Refer to Fig.12 , as described above, as the pulse height increases, the resistance R(SSM) of the self-selective memory layer 140 and the resistance R(ReRAM) of the resistive memory layer 150 can increase. In addition, as the pulse width increases, the resistance R(SSM) of the self-selective memory layer 140 can be constant, but the resistance R(ReRAM) of the resistive memory layer 150 can increase.

[0090] Table 2 shows the resistance states that can be achieved depending on the pulse height and pulse width when a pulse voltage of negative (-) polarity is applied between the first electrode 110 and the second electrode 120 of the memory device 100 shown in Figure 1 .

[0091] Table 2 describes the resistance states that can be achieved when the pulse heights are V1, V2, and V3 (where V1 < V2 < V3) and the pulse widths are W1, W2, and W3 (where W1 < W2 < W3) for the corresponding pulse heights.

[0092] [Table 2]

[0093]

[0094] Referring to Table 2, when the pulse height is V1, as the pulse width increases to W1, W2, and W3, the resistance R(SSM) of the self - select memory layer 140 can all be constant at R(S1), and the resistance R(ReRAM) of the resistive memory layer 150 can change to R(O14), R(O15), and R(O16) (where R(O14) < R(O15) < R(O16)). Therefore, when the pulse width changes to W1, W2, and W3 at a pulse height of V1, the memory device 100 can achieve three resistance states, namely R(S1)+R(O14), R(S1)+R(O15), and R(S1)+R(O16).

[0095] When the pulse height is V2 (> V1), as the pulse width increases to W1, W2, and W3, the resistance R(SSM) of the self - select memory layer 140 can all be constant at R(S2) (> R(S1)), and the resistance R(ReRAM) of the resistive memory layer 150 can change to R(O24), R(O25), and R(O26) (where R(O24) < R(O25) < R(O26)). Therefore, when the pulse width changes to W1, W2, and W3 at a pulse height of V2, the memory device 100 can achieve three resistance states, namely R(S2)+R(O24), R(S2)+R(O25), and R(S2)+R(O26).

[0096] When the pulse height is V3 (> V2), as the pulse width increases to W1, W2, and W3, the resistance R(SSM) of the self - select memory layer 140 can all be constant at R(S3) (> R(S2)), and the resistance R(ReRAM) of the resistive memory layer 150 can change to R(O34), R(O35), and R(O36) (where R(O34) < R(O35) < R(O36)). Therefore, when the pulse width changes to W1, W2, and W3 at a pulse height of V3, the memory device 100 can achieve three resistance states, namely R(S3)+R(O34), R(S3)+R(O35), and R(S3)+R(O36).

[0097] As described above, when a pulse voltage of negative (-) polarity is applied as the write voltage between the first electrode 110 and the second electrode 120 of the memory device 100, when using three pulse heights and three pulse widths, the memory device 100 can achieve up to nine - level resistance states. Therefore, when using "n" pulse heights and "m" pulse widths, the memory device 100 can achieve up to (n × m) resistance states. Here, "m" can be less than, equal to, or greater than "n".

[0098] Fig.13Schematically shows the resistance change depending on the pulse height, pulse number, and pulse width of the write voltage applied to Figure 1 the memory device 100 shown. Fig.13 Shows the case where a pulse voltage of negative (-) polarity is used as Figure 1 the write voltage between the first electrode 110 and the second electrode 120 of the memory device 100 shown in

[0099] Refer to Fig.13 , as described above, as the pulse height increases, the resistance R(SSM) of the self - select memory layer 140 and the resistance R(ReRAM) of the resistive memory layer 150 can increase. In addition, as the pulse number / pulse width increases, the resistance R(SSM) of the self - select memory layer 140 can be constant, but the resistance R(ReRAM) of the resistive memory layer 150 can increase.

[0100] Table 3 shows the resistance states that can be achieved depending on the pulse height and pulse width when a negative (-) polarity pulse voltage is applied between the first electrode 110 and the second electrode 120 of the memory device 100 shown in Figure 1 .

[0101] Table 3 describes the resistance states that can be achieved when the pulse heights are V1, V2, and V3 (where V1 < V2 < V3), and for the corresponding pulse heights, the pulse number / pulse width are 1 / W1, 2 / W2, and 3 / W3.

[0102] [Table 3]

[0103]

[0104] Referring to Table 3, in the case where the pulse height is V1, as the pulse number / pulse width increases to 1 / W1, 2 / W2, and 3 / W3, the resistance R(SSM) of the self - select memory layer 140 can all be constant at R(S1), and the resistance R(ReRAM) of the resistive memory layer 150 can change to R(O17), R(O18), and R(O19) (where R(O17) < R(O18) < R(O19)). Therefore, in the case where the pulse height is V1, when the pulse number / pulse width changes to 1 / W1, 2 / W2, and 3 / W3, the memory device 100 can achieve three resistance states, namely R(S1)+R(O17), R(S1)+R(O18), and R(S1)+R(O19).

[0105] When the pulse height is V2 (> V1), as the pulse number / pulse width increases to 1 / W1, 2 / W2, and 3 / W3, the resistance R(SSM) of the self - select memory layer 140 can all be constant at R(S2) (> R(S1)), and the resistance R(ReRAM) of the resistive memory layer 150 can be changed to R(O27), R(O28), and R(O29) (where R(O27) < R(O28) < R(O29)). Therefore, when the pulse number / pulse width is changed to 1 / W1, 2 / W2, and 3 / W3 at the pulse height of V2, the memory device 100 can achieve three resistance states, namely, R(S2) + R(O27), R(S2) + R(O28), and R(S2) + R(O29).

[0106] When the pulse height is V3 (> V2), as the pulse number / pulse width increases to 1 / W1, 2 / W2, and 3 / W3, the resistance R(SSM) of the self - select memory layer 140 can all be constant at R(S3) (> R(S2)), and the resistance R(ReRAM) of the resistive memory layer 150 can be changed to R(O37), R(O38), and R(O39) (where R(O37) < R(O38) < R(O39)). Therefore, when the pulse number / pulse width is changed to 1 / W1, 2 / W2, and 3 / W3 at the pulse height of V3, the memory device 100 can achieve three resistance states, namely, R(S3) + R(O37), R(S3) + R(O38), and R(S3) + R(O39).

[0107] As described above, when a pulse voltage of negative (-) polarity is applied between the first electrode 110 and the second electrode 120 of the memory device 100 as a write voltage, when using three pulse heights and three pulse / pulse widths, the memory device 100 can achieve up to nine - level resistance states. Therefore, when using "n" pulse heights and "m" pulse / pulse widths, the memory device 100 can achieve up to (n × m) resistance states. Here, "n" can be less than, equal to, or greater than "m".

[0108] The situation where the memory device 100 achieves a multi - level resistance state when a pulse voltage of negative (-) polarity is applied between the first electrode 110 and the second electrode 120 of the memory device 100 has been described above. However, the exemplary implementation is not limited to this, and a multi - level resistance state can also be achieved by applying a pulse voltage of positive (+) polarity between the first electrode 110 and the second electrode 120 of the memory device 100.

[0109] Table 4 shows when Figure 1When a pulse voltage of positive (+) polarity is applied between the first electrode 110 and the second electrode 120 of the memory device 100 shown in FIG. 1 , a resistance state that can be achieved depends on the pulse height and the number of pulses.

[0110] [Table 4]

[0111]

[0112] Referring to Table 4, even when the pulse height is changed to V1', V2' and V3' and the number of pulses increases to 1, 2 and 3, the resistance R(SSM) of the self-selection memory layer 140 can be all constant to R(S0'). In the case where the pulse height is V1', when the number of pulses is changed to 1, 2 and 3, the resistance R(ReRAM) of the resistive memory layer 150 can be changed to R(O11'), R(O12') and R(O13'). In the case where the pulse height is V2', when the number of pulses is changed to 1, 2 and 3, the resistance R(ReRAM) of the resistive memory layer 150 can be changed to R(O21'), R(O22') and R(O23'). In addition, in the case where the pulse height is V3', when the number of pulses is changed to 1, 2 and 3, the resistance R(ReRAM) of the resistive memory layer 150 can be changed to R(O31'), R(O32') and R(O33').

[0113] As described above, in the case where a pulse voltage of positive (+) polarity is applied as a write voltage between the first electrode 110 and the second electrode 120 of the memory device 100, when three pulse heights and three pulses are used, the memory device 100 can achieve up to nine levels of resistance states. Similarly, in the case where a pulse voltage of positive (+) polarity is applied as a write voltage between the first electrode 110 and the second electrode 120 of the memory device 100, even if multiple pulse widths are used, multiple levels of resistance states can be achieved.

[0114] In the memory device 100 according to some example embodiments, a multi-level resistance state may be achieved by adjusting the resistance of the self-selection memory layer 140 and the resistance of the resistive memory layer 150 using at least one of a pulse polarity, a pulse size, a pulse number, and a pulse width of a write voltage applied between the first electrode 110 and the second electrode 120.

[0115] Fig.14 is a block diagram illustrating a schematic configuration of a memory device 100 according to some example embodiments.

[0116] refer to Fig.14 , the memory device 100 may include a self-selection memory SSM device, a resistive memory device ReRAM connected in series to the self-selection memory SSM device, and a memory controller.

[0117] As described above, the self-selection memory SSM device may have an OTS characteristic and may have a threshold voltage that varies depending on the polarity and strength of the voltage applied thereto. The resistive memory device ReRAM may have a resistance characteristic that varies depending on the voltage applied thereto. The memory controller may implement a multi-level memory by being configured to adjust the resistance of the self-selection memory device and the resistance of the resistive memory device. For example, the memory controller may adjust the resistance of the self-selection memory device by changing the height of the pulse voltage of the negative (-) polarity applied to the self-selection memory device. Alternatively or additionally, the memory controller may adjust the resistance of the resistive memory device by changing at least one of the height of the pulse voltage applied to the resistive memory device, the number of pulse voltages, and the width of the pulse voltage.

[0118] Fig.15 A cross section of a memory device 200 according to some example embodiments is schematically illustrated. Hereinafter, differences from the above-described example embodiments are mainly described.

[0119] refer to Fig.15 , the memory device 200 may include a first electrode 210 and a second electrode 220 arranged separately from each other, and a self-selection memory layer 240 and a resistive memory layer 250 arranged between the first electrode 210 and the second electrode 220 .

[0120] The first insertion layer 260 may be disposed between the first electrode 210 and the self-selection memory layer 240. The first insertion layer 260 may prevent oxidation of the self-selection memory layer 240 and may include, for example, a carbon-based conductive material (eg, carbon nitride). However, example embodiments are not limited thereto.

[0121] The second insertion layer 270 may be disposed between the second electrode 220 and the resistive memory layer 250. The second insertion layer 270 may prevent oxidation or reduction of the resistive memory layer 250 and may include, for example, a conductive oxide or a conductive nitride. For example, the second insertion layer 270 may include, but is not limited to, TiO 2 SnO 2 、RuO 2 , one or more of ITO, IZO, TaN, TiN, WN or NbN.

[0122] The third electrode 230 disposed between the self-selection memory layer 240 and the resistive memory layer 250 may also function as a diffusion and oxidation prevention layer. The third electrode 230 may include, for example, a carbon-based conductive material (eg, carbon nitride); however, the present disclosure is not limited thereto.

[0123] Fig.16is a perspective view schematically illustrating a memory device 300 according to some example embodiments. Fig.17 yes Fig.16 0 is an enlarged view of one memory cell MC in the memory device 300 shown in FIG.

[0124] refer to Fig.16 and 17 , the memory device 300 may have a three-dimensional cross-point structure. For example, the memory device 300 may include a plurality of bit lines BL extending in a first direction (i.e., an x-axis direction), a plurality of word lines WL extending in a second direction (i.e., a y-axis direction) intersecting the first direction, and a plurality of memory cells MC arranged at points where the plurality of bit lines BL and the plurality of word lines WL intersect each other.

[0125] Each of the plurality of memory cells MC may correspond to Figure 1 The memory device 100 shown in FIG. The first electrode 310 and the second electrode 320 may be respectively Figure 1 The first electrode 110 and the second electrode 120 of the memory device 100 shown in FIG. 1 are the same, and therefore, redundant description thereof will be omitted for the sake of brevity. The first electrode 310 and the second electrode 320 may be formed integrally with the word line WL and the bit line BL, respectively.

[0126] Between the first electrode 310 and the second electrode 320, the self-selection memory layer 340 and the resistance memory layer 350 may be connected to each other in a series structure. The self-selection memory layer 340 and the resistance memory layer 350 may be connected to each other in a series structure. Figure 1 The self-selection memory layer 140 and the resistive memory layer 150 shown in FIG. 1 are the same, and therefore, for the sake of brevity, a redundant description thereof will be omitted. The third electrode 330 may be disposed between the self-selection memory layer 340 and the resistive memory layer 350. In addition, each of the plurality of memory cells MC may correspond to Fig.15 The memory device 200 shown in FIG.

[0127] In this structure, the memory cell MC can be driven by the potential difference between the word line WL and the bit line BL connected to the two ends of each memory cell MC, and each memory cell MC can realize a multi-level memory by using at least one of the pulse polarity, pulse size, pulse number and pulse width of the voltage applied between the word line WL and the bit line BL.

[0128] Fig.18 Is to show the selection Fig.16 0048. A plan view of the operation of a particular memory cell in the memory device 300 is shown in FIG.

[0129] refer to Fig.18, the memory device 300 may further include a row decoder 360 configured to selectively supply a voltage to a plurality of word lines WL and a column decoder 370 configured to selectively supply a voltage to a plurality of bit lines BL. When a voltage V is applied to a selected memory cell sMC among a plurality of memory cells MC, the row decoder 360 may supply the voltage V to the word line WL connected to the selected memory cell sMC, and supply a voltage V / 2 to other word lines WL. In this case, the column decoder 370 may supply a voltage of 0V to the bit line BL connected to the selected memory cell sMC, and supply a voltage of V / 2 to other bit lines BL.

[0130] Then, the potential difference between the word line WL and the bit line BL of the selected memory cell sMC may be V. On the other hand, the potential difference between the word line WL provided with the voltage V / 2 and the bit line BL provided with the voltage V / 2 may be 0V. Therefore, no voltage may be applied to the unselected memory cell uMC arranged between the word line WL and the bit line BL which are not connected to the selected memory cell sMC. In addition, a voltage of V / 2 may be applied to both ends of the half-selected memory cell hMC connected to the same word line WL as the selected memory cell sMC or to the same bit line BL as the selected memory cell sMC. Because each of the plurality of memory cells MC is a self-selecting memory device as described above, even when a voltage of V / 2 is applied to the half-selected memory cell hMC adjacent to the selected memory cell sMC, the half-selected memory cell hMC may not be turned on, and therefore, sneak current is almost unlikely to occur.

[0131] Fig.19 is a cross-sectional view schematically illustrating a multi-layered memory device 400 according to some example embodiments. The memory device 400 may have a multi-layered structure in which bit lines and word lines alternate vertically with each other. Fig.19 A portion of a memory device 400 having a three-dimensional cross-point structure is shown.

[0132] refer to Fig.19 , the first word line WL1 and the second word line WL2 may be vertically arranged in parallel with each other, and the bit line BL may be arranged between the first word line WL1 and the second word line WL2 to intersect the first word line WL1 and the second word line WL2. Here, the bit line BL may be a common bit line.

[0133] The first memory cell MC1 may be disposed between the first word line WL1 and the bit line BL, and the second memory cell MC2 may be disposed between the second word line WL2 and the bit line BL. Here, each of the first memory cell MC1 and the second memory cell MC2 may correspond to Figure 1The first / second memory cell MC1 / MC2 may have a structure in which a first electrode 410 / 410', a self-selection memory layer 440 / 440', a third electrode 430 / 430', a resistive memory layer 450 / 450', and a second electrode 420 / 420' are sequentially stacked.

[0134] The first memory cell MC1 and the second memory cell MC2 may be arranged in a symmetrical structure with respect to the bit line BL. In particular, the first electrode 410 of the first memory cell MC1 and the first electrode 410' of the second memory cell MC2 may be arranged symmetrically with respect to the bit line BL, and the second electrode 420 of the first memory cell MC1 and the second electrode 420' of the second memory cell MC2 may be arranged symmetrically with respect to the bit line BL. The first electrode 410 of the first memory cell MC1 may be formed integrally with the first word line WL1, and the first electrode 410' of the second memory cell MC2 may be formed integrally with the second word line WL2. In some examples, the second electrode 420 of the first memory cell MC1 and the second electrode 420' of the second memory cell MC2 may be formed integrally with the bit line BL. The self-selection memory layer 440 of the first memory cell MC1 and the self-selection memory layer 440' of the second memory cell MC2 may be arranged symmetrically with respect to the bit line BL, and the resistive memory layer 450 of the first memory cell MC1 and the resistive memory layer 450' of the second memory cell MC2 may be arranged symmetrically with respect to the bit line BL. In addition, each of the first memory cell MC1 and the second memory cell MC2 may correspond to Fig.15 The memory device 200 shown in FIG.

[0135] The memory devices 100 , 200 , 300 , and 400 according to the various embodiments described above may be used for data storage in various electronic devices. Fig. 20 is a conceptual diagram schematically illustrating a device architecture applicable to an electronic apparatus according to an embodiment.

[0136] refer to Fig. 20, a cache memory 1510, an arithmetic logic unit (ALU) 1520, and a control unit 1530 may constitute a central processing unit (CPU) 1500, and the cache memory 1510 may include a static random access memory (SRAM). A main memory 1600 and an auxiliary storage 1700 may be provided separately from the CPU 1500. An input / output device 2500 may be provided. The main memory 1600 may include a dynamic random access memory (DRAM) device, and the auxiliary storage 1700 may include the above-mentioned memory devices 100 and 200. In some cases, the device architecture may be implemented in the form of a computing unit device and a memory unit device adjacent to each other in one chip without distinguishing between subunits.

[0137] The memory devices 100 , 200 , 300 , and 400 according to the above-described embodiments may be implemented as a chip-type memory block to be used as a neuromorphic computing platform, or may be used to configure a neural network.

[0138] Fig.21 is a block diagram of a memory system 2600 according to some example embodiments.

[0139] refer to Fig.21 , the memory system 2600 may include a memory controller 1601 and a memory device 1602. The memory controller 1601 may perform a control operation on the memory device 1602, and, for example, the memory controller 1601 may provide the memory device 1602 with an address ADD and a command CMD for performing a program (or write), read, and / or erase operation on the memory device 1602. In addition, data for a program operation and read data may be transmitted between the memory controller 1601 and the memory device 1602.

[0140] The memory device 1602 may include a memory cell array 1610 and a voltage generator 1620. The memory cell array 1610 may include a plurality of memory cells and may include one or more of the memory devices 100, 200, 300, and 400 according to the embodiments described above.

[0141] The memory controller 1601 may include a processing circuit, such as hardware including a logic circuit; a hardware / software combination, such as a processor executing software; or a combination thereof. More specifically, the processing circuit may include, for example, one or more of a CPU, an ALU, a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, and an application-specific integrated circuit (ASIC); however, example embodiments are not limited thereto. The memory controller 1601 may operate in response to a request from a host (not shown), and may be configured to convert the memory controller 1601 into a dedicated controller by accessing the memory device 1602 and controlling the control operations (e.g., write / read operations) described above. The memory controller 1601 may generate an address ADD and a command CMD for performing program / read / erase operations on the memory cell array 1610. In addition, in response to a command from the memory controller 1601, the voltage generator 1620 (e.g., a power supply circuit) can generate a voltage control signal for controlling the voltage level of a word line for programming / reading data into / from the memory cell array 1610.

[0142] In some cases, the memory controller 1601 may perform a determination operation on the data read from the memory device 1602. For example, the number of on cells and / or the number of off cells may be determined based on the data read from the memory cells. The memory device 1602 may provide a pass / fail signal P / F to the memory controller 1601 based on the read result of the read data. The memory controller 1601 may control the write and read operations of the memory cell array 1610 with reference to the pass / fail signal P / F.

[0143] Fig. 22 is a block diagram illustrating a neuromorphic device 2700 and external devices connected thereto, according to some example embodiments.

[0144] refer to Fig. 22 , the neuromorphic device 2700 may include a processing circuit 1710 and / or an on-chip memory 1720. The neuromorphic device 2700 may include the memory devices 100, 200, 300, and 400 according to the above-described embodiments.

[0145] In some example embodiments, the processing circuit 1710 may be configured to control functions for driving the neuromorphic device 1700. For example, the processing circuit 1710 may be configured to control the neuromorphic device 2700 by executing a program stored in the on-chip memory 1720. In some embodiments, the processing circuit 1710 may include hardware (such as a logic circuit), a hardware / software combination (such as a processor that executes software), or a combination thereof. For example, the processor may include a CPU, a graphics processing unit (GPU), an application processor (AP) included in the neuromorphic device 1700, an ALU, a digital signal processor, a microcomputer, an FPGA, a SoC, a programmable logic unit, a microprocessor, and an ASIC; however, example embodiments are not limited thereto. In some embodiments, the processing circuit 1710 may be configured to read / write various data with respect to the external device 1730 and / or to execute the neuromorphic device 2700 by using the read / written data. In some embodiments, the external device 1730 may include an external memory and / or a sensor array including an image sensor (e.g., a CMOS image sensor circuit).

[0146] In some example embodiments, Fig. 22 The neuromorphic device 2700 can be applied to a machine learning system. The machine learning system can use various artificial neural network structures and processing models, such as a convolutional neural network (CNN), a deconvolutional neural network, a recurrent neural network (RNN) optionally including a long short-term memory (LSTM) unit and / or a gated recurrent unit (GRU), a stacked neural network (SNN), a state-space dynamic neural network (SSDNN), a deep belief network (DBN), a generative adversarial network (GAN), and / or a restricted Boltzmann machine (RBM). One or more.

[0147] Alternatively or additionally, the machine learning system may include other types of machine learning models, such as linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, expert systems, and / or combinations thereof, including ensembles such as random forests. The machine learning model may be used to provide various services and / or applications, and for example, image classification services, user authentication services based on biometric information or biometric data, advanced driver assistance system (ADAS) services, voice assistance services, and automatic speech recognition (ASR) services may be performed by the electronic device.

[0148] Although the memory devices 100, 200, 300 and 400 have been described above with reference to the various exemplary embodiments shown in the figures, this is only an example and those skilled in the art will appreciate that various modifications and other equivalent embodiments may be derived therefrom. For example, the exemplary embodiments are not necessarily mutually exclusive.

[0149] Any of the elements and / or functional blocks disclosed above may include or be implemented in a processing circuit, such as hardware including a logic circuit; a hardware / software combination, such as a processor executing software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. The processing circuit may include an electrical component such as at least one of a transistor, a resistor, a capacitor, etc. The processing circuit may include an electronic component such as a logic gate, and the logic gate includes at least one of an AND gate, an OR gate, a NAND gate, a NOT gate, etc.

[0150] It should be understood that the various embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects within each example embodiment should generally be considered applicable to other similar features or aspects in other example embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A memory device, comprising: A first electrode and a second electrode separated from each other; a self-select memory layer between the first electrode and the second electrode, having a bidirectional threshold switching characteristic, including a chalcogenide-based material, and configured to have a threshold voltage that varies depending on the polarity and intensity of a voltage applied thereto; as well as a resistive memory layer between the second electrode and the self-selection memory layer and having a resistance characteristic that changes depending on a voltage applied thereto, The memory device is configured to achieve a multi-level resistance state by changing at least one of a pulse polarity, a pulse number, a pulse height, and a pulse width of a voltage applied between the first electrode and the second electrode.

2. The memory device according to claim 1, wherein: The self-selection memory layer and the resistive memory layer are electrically connected to each other in series.

3. The memory device according to claim 1, wherein: The self-selection memory layer includes a chalcogen element including at least one of Se, Te, and S, and at least one of Ge, As, and Sb.

4. The memory device according to claim 3, wherein: The self-selection memory layer also includes at least one of In, Al, C, B, Sr, Ga, O, N, Si, Ca and P.

5. The memory device according to claim 1, wherein: The resistive memory layer includes at least one of Al2O3, In2O3, MgO, MoO3, Ta2O5, TiO2, HfO2, PrCaMnO3, V2O5 and ZnO.

6. The memory device according to claim 1, wherein: The memory device is configured to have a pulse voltage of a specific polarity applied between the first electrode and the second electrode, and has a multi-level resistance state achieved by adjusting at least one of the number of pulses, pulse height, and pulse width of the pulse voltage.

7. The memory device according to claim 6, wherein: The memory device is configured to have each of the multi-level resistance states determined by a sum of a first resistance of the self-select memory layer and a second resistance of the resistive memory layer.

8. The memory device of claim 1, further comprising: A third electrode is between the self-selection memory layer and the resistive memory layer.

9. The memory device of claim 1 , further comprising: An insertion layer is in at least one of between the first electrode and the self-selection memory layer and between the second electrode and the resistive memory layer.

10. A method for implementing a multi-level memory by using a memory device, the memory device comprising: A first electrode and a second electrode separated from each other; a self-select memory layer between the first electrode and the second electrode, having a bidirectional threshold switching characteristic, including a chalcogenide-based material, and configured to have a threshold voltage that varies depending on the polarity and intensity of a voltage applied thereto; as well as a resistive memory layer between the second electrode and the self-selection memory layer and having a resistance characteristic that changes depending on a voltage applied thereto, Wherein, the method comprises: The multi-level resistance state is achieved by changing at least one of a pulse polarity, a pulse number, a pulse height, and a pulse width of a voltage applied between the first electrode and the second electrode.

11. The method according to claim 10, wherein: The self-selection memory layer and the resistive memory layer are electrically connected to each other in series.

12. The method according to claim 10, further comprising: applying a pulse voltage of a specific polarity between the first electrode and the second electrode; as well as The multi-level resistance state is achieved by adjusting at least one of the pulse number, pulse height and pulse width of the pulse voltage.

13. The method according to claim 12, further comprising: Each of the multi-level resistance states is determined by summing a first resistance of the self-selection memory layer and a second resistance of the resistive memory layer.

14. The method according to claim 13, wherein: As the pulse height increases, the first resistance and the second resistance change.

15. The method according to claim 13, wherein: As the number of pulses increases, the first resistance is constant and the second resistance changes.

16. The method according to claim 13, wherein: As the pulse width increases, the first resistance is constant and the second resistance changes.

17. A memory device comprising: a plurality of bit lines; a plurality of word lines intersecting the plurality of bit lines; as well as a plurality of memory cells, wherein the plurality of bit lines and the plurality of word lines intersect each other, Wherein, each of the plurality of memory cells comprises: A first electrode and a second electrode separated from each other; a self-selection memory layer between the first electrode and the second electrode, having a bidirectional threshold switching characteristic, including a chalcogenide-based material and configured to have a threshold voltage that varies depending on the polarity and intensity of a voltage applied thereto; and a resistive memory layer between the second electrode and the self-selection memory layer and having a resistance characteristic that changes depending on a voltage applied thereto, The memory device is configured to achieve a multi-level resistance state by changing at least one of a pulse polarity, a pulse number, a pulse height, and a pulse width of a voltage applied between the first electrode and the second electrode.

18. The memory device of claim 17, wherein: The self-selection memory layer and the resistive memory layer are electrically connected to each other in series.

19. The memory device of claim 17, wherein: Each of the multi-level resistance states is based on a sum of a first resistance of the self-selection memory layer and a second resistance of the resistive memory layer.

20. The memory device of claim 17, wherein: The plurality of bit lines and the plurality of word lines are a multi-layer structure that alternates vertically with each other, and the memory cells above and below each of the plurality of bit lines are symmetrical with respect to the bit line.

21. A multi-level memory device comprising: a self-select memory device having a bidirectional threshold switching characteristic and having a threshold voltage that varies depending on the polarity and magnitude of a voltage applied thereto; a resistive memory device connected in series to the self-selecting memory device and having a resistance characteristic that varies depending on a voltage applied thereto; as well as A memory controller is configured to change a height of a pulse voltage of negative polarity applied to the self-selected memory device.

22. The multi-level memory device of claim 21, wherein: The memory controller is configured to vary a height of a pulse voltage applied to the resistive memory device.

23. The multi-level memory device of claim 21, wherein: The memory controller is configured to change a number of pulse voltages applied to the resistive memory device.

24. The multi-level memory device of claim 21, wherein: The memory controller is configured to change a width of a pulse voltage applied to the resistive memory device.

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