Stacked FET standard cell architecture

Abstract

The invention discloses a cell layout for implementing stacked transistors. The cell layout utilizes both top-side metal wirings and back-side metal wirings. Various connection routes may be formed between components of the transistors (e.g., gates, sources, and drains) and either the top side metal wiring or the back side metal wiring. A particular connection route may be determined based on a desired device configuration. Accordingly, the disclosed cell layout enables various devices to be constructed based on the base cell structure.

Description

Background Art Technical Field

[0001] Embodiments described herein relate to power and signal routing for semiconductor devices. More specifically, embodiments described herein relate to power and signal routing through both topside and backside layers for integrated circuit cells having a plurality of transistors.

[0002] Related technical description

[0003] A standard cell is a group of transistors, passive structures, and interconnect structures that can provide logic functions, memory functions, etc. The current trend in standard cell approaches is toward reducing the size of standard cells while increasing the complexity (e.g., circuit density and number of components or transistors) within the standard cells. However, as standard cell designs become smaller and smaller, it becomes more difficult to provide access (e.g., connections) to components within the standard cells within the design / manufacturing constraints of the standard cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The features and advantages of the methods and apparatus of the embodiments described in the present disclosure will be more fully understood by reference to the following detailed description of presently preferred but merely exemplary embodiments according to the embodiments described in the present disclosure when taken in conjunction with the accompanying drawings, in which:

[0005] Figure 1 Depicted is a top side plan view representation of a standard cell according to some embodiments.

[0006] Figure 2 Depicted is a backside plan view representation of a standard cell according to some embodiments.

[0007] Figure 3 Depicts the standard unit along Figure 1 A cross-section representation of line 3-3 is shown.

[0008] Figure 4 Depicts the standard unit along Figure 2 A cross-section representation of line 4-4 is shown.

[0009] Figure 5 Depicts the standard unit along Figure 1 and Figure 2 A cross-section representation of line 5-5 is shown.

[0010] Figure 6 Depicts the standard unit along Figure 1 and Figure 2 A cross-section representation of line 6-6 is shown.

[0011] Figure 7 Depicted is a top side plan view representation of a cell having alternating vias along a border, according to some embodiments.

[0012] Figure 8 is a cross-sectional representation of a cell showing connections to a source region, according to some embodiments.

[0013] Fig. 9 is a cross-sectional representation of a cell showing connections to a drain region, according to some embodiments.

[0014] Fig.10 Depicted is a cross-sectional representation of stacked transistor control signal connections in a cell implementing a via post according to some embodiments.

[0015] Fig.11 Depicted is a cross-sectional representation of stacked transistor control signal connections in a common gate configuration, according to some embodiments.

[0016] Fig.12 Depicted is a cross-sectional representation of stacked transistor control signal connections in a cross-coupled gate configuration, according to some embodiments.

[0017] Fig.13 Depicted is a top side plan view representation of a NAND cell according to some embodiments.

[0018] Fig.14 Depicted is a backside plan view representation of a NAND cell according to some embodiments.

[0019] Fig.15 Depicts the NAND cell along Fig.13 and Fig.14 A cross section along line AA' is shown.

[0020] Fig.16 Depicts the NAND cell along Fig.13 and Fig.14 A cross section along line BB' is shown.

[0021] Fig.17 Depicts the NAND cell along Fig.13 and Fig.14 A cross-section representation of line CC' is shown.

[0022] Fig.18 Depicts the NAND cell along Fig.13 and Fig.14 A cross-section representation of line DD' is shown.

[0023] Fig.19 A schematic representation of a memory cell is depicted.

[0024] Fig. 20 Depicted is a top-side plan view representation of a memory cell having stacked transistors according to some embodiments.

[0025] Fig.21 Depicted is a backside plan view representation of a memory cell having stacked transistors according to some embodiments.

[0026] Fig. 22 Depicts the storage unit along Fig. 20 and Fig.21 A cross section along line AA' is shown.

[0027] Fig.23 Depicts the storage unit along Fig. 20 and Fig.21 A cross section along line BB' is shown.

[0028] Fig.24 Depicts the storage unit along Fig. 20 and Fig.21 A cross-section representation of line CC' is shown.

[0029] Fig.25 Depicted is a block diagram representation of a memory device according to some embodiments.

[0030] Fig.26 Depicted is a top plan view representation of a region with virtual cells according to some embodiments.

[0031] Fig. 27 Depicted is a backside plan view representation of a region with virtual cells according to some embodiments.

[0032] Fig.28 Depicts the region with virtual cells along Fig.26 and Fig. 27 A cross section along line AA' is shown.

[0033] Fig.29 Depicts the region with virtual cells along Fig.26 and Fig. 27 A cross section along line BB' is shown.

[0034] Fig.30 Depicted is a top plan view representation of a region with virtual cells according to some embodiments.

[0035] Fig.31 Depicted is a backside plan view representation of a region with virtual cells according to some embodiments.

[0036] Fig.32 Depicts the region with virtual cells along Fig.30 and Fig.31 A cross section along line AA' is shown.

[0037] Fig.33Depicts the region with virtual cells along Fig.30 and Fig.31 A cross section along line BB' is shown.

[0038] Fig.34 Depicted is a schematic representation of a column I / O cell according to some embodiments.

[0039] Fig.35 Depicted is a layout of a column I / O cell according to some embodiments.

[0040] Fig.36 Depicted is a perspective representation of a contemplated vertical transistor device in accordance with some embodiments.

[0041] Fig.37 Depicted is a perspective representation of another contemplated vertical transistor device in accordance with some embodiments.

[0042] Fig.38 Depicted is a perspective representation of an inverter unit configuration according to some embodiments.

[0043] Fig.39 Depicted is a top plan view representation of an inverter unit configuration according to some embodiments.

[0044] Fig.40 Depicted is a back plan view representation of an inverter unit configuration according to some embodiments.

[0045] Fig.41 Depicted is a reverser unit configuration according to some embodiments. Fig.39 A cross section along line 41-41 is shown.

[0046] Fig.42 Depicted is a reverser unit configuration according to some embodiments. Fig.39 A cross-section representation of line 42-42 is shown.

[0047] Fig.43 Depicted is a perspective representation of a NAND cell construction according to some embodiments.

[0048] Fig.44 Depicted is a top side plan view representation of a NAND cell construction according to some embodiments.

[0049] Fig.45 Depicted is a backside plan view representation of a NAND cell construction according to some embodiments.

[0050] Fig.46 Depicted is a NAND cell structure according to some embodiments. Fig.44 A cross-section representation of line 46-46 is shown.

[0051] Fig.47 Depicted is a NAND cell structure according to some embodiments. Fig.44 A cross section through line 47-47 is shown.

[0052] Fig.48 Depicted is a perspective representation of a MUX unit configuration according to some embodiments.

[0053] Fig.49 Depicted is a top plan view representation of a MUX cell configuration according to some embodiments.

[0054] Fig.50 Depicted is a backside plan view representation of a MUX cell configuration according to some embodiments.

[0055] Fig.51 Depicted is a MUX unit configuration according to some embodiments. Fig.49 A cross section along line 51 - 51 is shown.

[0056] Fig.52 Depicted is a MUX unit configuration according to some embodiments. Fig.49 A cross-section representation of line 52-52 is shown.

[0057] Fig.53 Depicted is a perspective representation of a device according to some embodiments.

[0058] Fig.54 Depicted is a device according to some embodiments along Fig.53 A cross-section representation of line 54-54 is shown.

[0059] Fig.55 is a block diagram of one embodiment of an exemplary system.

[0060] Although the embodiments disclosed herein are susceptible to various modifications and alternative forms, specific embodiments of the invention are shown in the drawings by way of example and described in detail herein. However, it should be understood that the drawings and detailed description thereof are not intended to limit the scope of the claims to the specific forms disclosed. On the contrary, the application is intended to cover all modifications, equivalents and alternatives that fall within the spirit and scope of the disclosure of the application as defined by the appended claims. DETAILED DESCRIPTION

[0061] As used herein, the term "standard cell" refers to a set of transistor structures, passive structures, and interconnect structures formed on a substrate to provide a logic function or a memory function that is standard for a variety of specific implementations. For example, a single standard cell can be a cell in a plurality of cell libraries from which various suitable cells can be selected to implement a particular cell design. Integrated circuit cells can also include custom circuit design cells that are individually designed for a particular specific implementation. The embodiments of the circuit design cells described herein can be implemented in various specific implementations of a logic integrated circuit or a memory integrated circuit.

[0062] Many current designs of cells provide connections and routing of power or signals to transistors or other structures in the area above the transistors. For example, connections and routing of power or signals may be provided in the top side layer of the device. As used herein, the term "top side" refers to an area of ​​the device that is vertically located above the active layer of the device (e.g., above the transistor area of ​​the device when viewed in a typical cross-sectional view). For example, the top side may refer to a component (such as a contact or layer) that is located above the transistor area in the vertical dimension, as depicted in the figure and described herein. In some instances, the term "front side" may be used interchangeably with the term "top side".

[0063] Some recent advances in standard cell design move the connections and routing of power connections to the metal layer below the transistor. For example, the connections and routing of the power supply may be provided in the backside layer of the device. As used herein, the term "backside" refers to an area of ​​the device that is vertically located below the active layer of the device (e.g., below the transistor area of ​​the device when viewed in a typical cross-sectional view). For example, the backside may refer to a component (such as a contact or layer) that is located below the transistor area in the vertical dimension, as depicted in the figure and described herein. It should be noted that, as used herein, the backside elements located below the active layer may be located above, inside, or below the silicon substrate on which the active layer is manufactured. That is, as used herein, "backside" is relative to the active layer, not the silicon substrate.

[0064] The present disclosure relates to various implementations of stacked transistors or vertical transistors in integrated circuit cells (e.g., standard cells) that utilize connections to both topside metal layers and backside metal layers. The inventors have recognized that topside and backside layers can be utilized in a particular manner to provide technical and space saving advantages for implementing a cell layout of stacked transistors or vertical transistors. The disclosed embodiments implement topside and backside metal layers to provide a favorable cell layout and routing (e.g., paths) for control signals or power signals within the cell layout.

[0065] Stacked transistor standard cell design

[0066] Stacked transistors (e.g., where two transistor active areas are stacked vertically above a substrate) can provide various technical and space saving advantages due to the proximity of devices in the transistor. However, due to the design and manufacturing constraints associated with standard cell construction, it is challenging to implement stacked transistors in standard cells. For example, in a standard cell that utilizes only top-side wiring, there are typically not enough paths for wiring to the two transistors without expanding the size of the standard cell. Without changing the size of the standard cell, a standard cell limited to top-side wiring for control signals and back-side wiring for power signals may also lack the necessary wiring and connection availability for two stacked transistors.

[0067] The present disclosure contemplates various techniques for implementing wiring in both the topside and backside metal layers that allow two stacked transistors to be placed in a standard cell. Various embodiments of standard cell constructions are disclosed that provide basic building blocks for many different types of devices, from simple devices (e.g., inverters and NAND devices) to more complex devices (e.g., complex FETs). The disclosed embodiments provide compact standard cell constructions that allow stacked transistors to be implemented in a variety of circuit logic schemes.

[0068] Certain embodiments disclosed herein have four main elements: 1) a first metal layer (e.g., a topside metal layer) located above a transistor region of an integrated circuit cell structure; 2) a second metal layer (e.g., a backside metal layer) located below the transistor region, 3) a pair of vertically stacked transistors in the transistor region, and 4) various possible connection paths for both control signals and power signals between the first metal layer or the second metal layer and the first transistor and the second transistor. In certain embodiments, the pair of vertically stacked transistors include heterogeneous transistors (e.g., complementary transistor types, such as PMOS and NMOS transistors). In some embodiments, the pair of vertically stacked transistors include homogeneous transistors (e.g., the transistors are of the same type).

[0069] In various embodiments, control signals and power signal connections are made to implement logic associated with a specific integrated circuit device having multiple transistors for the standard cell configuration described herein. For example, examples of inverter devices or NAND gate devices that can be implemented based on the standard cell configuration are described below. Embodiments for various possible connections of control signals and voltage signals to stacked transistors within the standard cell configuration are also described. Those skilled in the art will appreciate that combinations of these various possible connections can be implemented to generate many different desired circuits based on stacked transistor structures within the standard cell configuration.

[0070] In short, the inventors have recognized that providing various wiring paths within the standard cell structure allows for connection to the topside metal layer and the backside metal layer for control signals and power signals from the stacked transistors positioned within the standard cell structure. The wiring paths described herein enable the standard cell structure to be used to generate both a variety of simple and complex integrated circuit logic devices based on the stacked transistors within the cell. Additionally, the standard cell structure with stacked transistors described herein provides a scalable template that can be implemented in a device with multiple integrated circuit cells. The standard cell structure with stacked transistors within the present disclosure also implements a cell structure that can be implemented within current manufacturing constraints without changing the size or parameters of the current standard cell. As used herein, the term "wiring" refers to any combination of metal vias, metal wires, metal traces, etc. that provide a path / route between two structures. Additional embodiments in which the metal in the "wiring" is replaced with an alternative conductive material can be envisioned. For example, the metal in the "wiring" can be replaced with a superconductor material, a semiconductor material, or a non-metallic conductor.

[0071] Figures 1 to 6 Depicted is a representation of a standard cell having stacked transistors and both topside and backside layer connections in accordance with some embodiments. Figure 1 Depicted is a top side plan view representation of a standard cell 100 according to some embodiments. Figure 2 Depicted is a backside plan view representation of a standard cell 100 in accordance with some embodiments. Figure 3 Depicts a standard unit 100 along Figure 1 A cross-section representation of line 3-3 is shown. Figure 4 Depicts a standard unit 100 along Figure 2 A cross-section representation of line 4-4 is shown. Figure 5 Depicts a standard unit 100 along Figure 1 and Figure 2 A cross-section representation of line 5-5 is shown. Figure 6 Depicts a standard unit 100 along Figure 1 and Figure 2 A cross-section representation of line 6-6 is shown.

[0072] In order to simplify the drawings, only components relevant to the present disclosure are shown in the representation of the units disclosed herein. It will be understood by those skilled in the art that additional components may be present in any of the units described herein. For example, in Figure 1 In some depictions, various connections (such as vias or contacts as described herein) may be visible. Additionally, to better understand the disclosed embodiments, a degree of material transparency is provided to enable the underlying components to be seen in top and back plan views. For example, in Figure 1 and Figure 2In the embodiment, substrate 102 has a certain transparency to provide visibility of the gate and active area of ​​the underlying transistor, and topside metal layer 112 and backside metal layer 120 have a certain transparency to provide visibility of contacts 114 and backside vias 122, respectively.

[0073] In various embodiments, such as Figures 1 to 6 As shown, standard cell 100 includes substrate 102. In certain embodiments, substrate 102 is a silicon substrate, but other semiconductor substrates are also contemplated. Substrate 102 may include additional components or features for implementation in cell 100. For example, substrate 102 may include one or more insulating layers (e.g., oxide layers), diffusion (e.g., oxide diffusion) regions, or doped regions for implementation in cell 100. To simplify the drawings, substrate 102 is depicted as a material that fills the volume of standard cell 100.

[0074] In various embodiments, the first active region 104 and the second active region 106 are formed in the substrate 102. In certain embodiments, the active region 104 is vertically positioned above the active region 106 in the cell 100. For example, the active region 104 may be positioned in the upper portion of the cell 100, while the active region 106 is in the lower portion of the cell. It should be noted that the active region 104 and the active region 106 may not necessarily be positioned directly above / below each other. For example, some portions of the active region 104 or the active region 106 may be outside the boundary of the other active region. Therefore, when describing that the active region 104 is above the active region 106, it may mean that at least some portion of the active region 104 is above at least some portion of the active region 106, and vice versa.

[0075] In some embodiments, active region 104 is the active region of a first transistor in cell 100, and active region 106 is the active region of a second transistor in the cell. For example, in one contemplated embodiment, active region 104 is the active region of an NMOS transistor having one or more NMOS gates, and active region 106 is the active region of a PMOS transistor having one or more PMOS gates. Alternatively, active region 104 may be the active region of a PMOS transistor, and active region 106 is the active region of an NMOS transistor. Although with respect to Figures 1 to 6Transistor stacks having these complementary transistor types (e.g., heterogeneous transistors) are described, but it should be understood that additional embodiments are also contemplated in which the two transistors are of the same type (e.g., homogeneous transistors). Additionally, while the disclosed embodiments describe silicon-based transistors (e.g., NMOS and PMOS transistors), other types of semiconductor-based transistors are contemplated without departing from the scope of the present disclosure. Furthermore, any type of transistor structure is also contemplated. For example, the transistors formed may include transistors such as, but not limited to, FinFETs, nanosheet FETs (NSHs), or GAAFETs ("gate-all-around" FETs).

[0076] In various embodiments, the transistor having active region 104 includes an upper gate 108 and source / drain regions 124, while the transistor having active region 106 includes a lower gate 116 and source / drain regions 124. The transistors may be positioned between isolation gates 110, such as Figures 1 to 4 As shown. Cell 100 may also include contacts 126 that provide connections to source / drain regions 124. Figures 1 to 6 As depicted, cell 100 includes two upper gates 108A-B, two lower gates 116A-B, six source / drain regions 124A-F (with three source / drain regions 124A-C in the upper transistor and three source / drain regions 124D-F in the lower transistor), and six contacts 126A-F positioned between isolation gates 110 in cell 100. However, Figures 1 to 6 The depicted embodiment of cell 100 is one example of a possible configuration of transistor components within a cell. For example, it should be understood that cell 100 may include any number of transistor components that fit within the boundaries of the cell according to the design and manufacturing constraints of the cell (e.g., the design and manufacturing constraints of a standard cell) without departing from the scope of the present disclosure.

[0077] The upper gate 108 and the lower gate 116 can be, for example, a polysilicon line (e.g., a polysilicon layer) or a high-k / metal gate. In some embodiments, the upper gate 108 and the lower gate 116 include a gate spacer (not shown in the drawings for simplicity). For example, the gate spacer can be positioned between the gate 108 / 116 and the source / drain region 124. In various embodiments, the gate spacer is formed as part of the gate 108 / 116 (e.g., the gate and the spacer are formed in the same process flow). The source / drain region 124 can be, for example, an epitaxial layer grown on a fin or nanosheet stack or any 2D (two-dimensional) channel material. Various embodiments can also be envisioned in which the source / drain region 124 is at least partially positioned in the substrate 102.

[0078] In addition to the transistor components described above, various connections to the gate and / or source / drain regions may be made within cell 100. The connections may include, for example, contacts or vias that provide connections between the transistor components in cell 100 and topside metal layer 112 or backside metal layer 120. Contact 114 (at Figure 1 , Figure 3 and Figure 5 ) is an example of a gate contact that provides a connection between the upper gate 108A and the topside metal layer 112B. The backside via 122 (shown in Figure 2 , Figure 4 and Figure 6 ) is an example of a via that provides a connection between the source / drain region 124F and the backside metal layer 120B.

[0079] In various embodiments, contact 114 is a topside via that provides connections from various portions of the transistor (e.g., source / drain regions, gate, etc.) to topside metal layer 112, while backside via 122 provides connections from various portions of the transistor to the backside metal layer. Contact 114 and backside via 122 are provided as non-limiting examples of possible connections in cell 100. For example, any number or combination of contacts or vias (along with any horizontal wiring) may be implemented in cell 100 to provide connections between various topside metal layers and backside metal layers and transistor components (e.g., upper gate 108, lower gate 116, and source / drain regions 124) within the cell. Connections may also be made depending on whether components within the transistor of cell 100 require control signals or power signals. For example, in Figures 1 to 6 In the depicted embodiment, contacts 114 may provide control signal connections to upper gate 108A, while backside vias 122 provide power signal connections to source / drain regions 124F. The number, type, and positioning of contacts and vias may be determined based on the desired device constructed using the component structures within cell 100. For example, an inverter device has similar characteristics to a NAND device such as Figures 13 to 18 ) different connections as shown in the examples.

[0080] like Figures 1 to 6 As shown, cell 100 includes four topside metal traces (topside metal layers 112A-D) and three backside metal traces (backside metal layers 120A-C). It should be understood that cell 100 may include any number of topside metal traces and backside metal traces as permitted by the design and manufacturing constraints of the cell. For example, the number of metal traces may be higher or lower depending on the design and manufacturing constraints of the cell, such as height, spacing, width, etc. Additionally, the topside metal traces and backside metal traces may not be aligned with each other. For example, as shown in FIG. Figures 5 and 6As clearly depicted, the topside metal layer 112 is not aligned with the backside metal layer 120. However, embodiments are contemplated having aligned topside and backside metal layers.

[0081] In various embodiments, such as Figure 4 As shown, the backside metal layer 120 is formed at or near the bottom surface of the substrate 102. In certain embodiments, the backside metal layer 120 includes one or more backside layers of the active layers in the cell 100 (e.g., the backside metal layer is vertically below the active area 106). In some embodiments, the backside metal layer 120 includes one or more buried layers in the substrate 102 (e.g., the metal layer is buried or embedded below the bottom surface of the substrate). In some embodiments, the backside metal layer 120 is buried below a carrier substrate layer (e.g., a silicon carrier substrate). Additional embodiments are envisioned in which the backside metal layer 120 is not located in the substrate 102.

[0082] Metal traces may also be selected for use as control signal traces (e.g., control signal trunks) or power signal traces (e.g., power signal trunks) based on the desired device use of the cell 100. The control signal traces may provide input or output signal connections to the transistor components in the cell 100, while the power signal traces may provide power wiring to / from Vdd (e.g., supply voltage) and Vss (e.g., ground) and other envisioned power connections. The selection of traces for use as control signal traces or power signal traces may also determine the connection to the metal traces. For example, in the depicted embodiment of the cell 100, the topside metal layer 112B is a control signal trace connected to the upper gate 108A via a contact 114, while the backside metal layer 120B is a power signal trace connected to the source / drain region 124F via a backside via 122. It should be noted that any of the backside metal layers 120A-C may be used as a power signal trace in various envisioned embodiments. The remaining topside metal traces (e.g., topside metal layers 112A, 112C, 112D) may be used for either additional topside control signal traces or topside power signal traces. Similarly, the remaining backside metal traces (e.g., backside metal layers 120A and 120C) may be used for either additional backside power signal traces or backside control signal traces. For example, in one contemplated embodiment, one of the topside metal layers 112A, 112C, 112D may be a topside power signal trace having a contact to a source / drain region (e.g., one of source / drain regions 124A-C) in an upper portion of the cell 100 to provide a power signal connection to an upper transistor having an active region 104. Additionally, one of the backside metal layers 120A and 120C can be a backside control signal line having a contact to a lower gate 116B in a lower portion of the cell 100 (e.g., a lower gate in a split gate configuration) to provide a control signal connection to a lower transistor having an active area 106.

[0083] In various contemplated embodiments, one or more top-side metal traces (e.g., top-side metal layers 112A-D) may be merged when the metal traces are used as power rails (e.g., power signal traces). For example, in some embodiments, when metal traces along the edge of a cell (e.g., top-side metal layer 112A or top-side metal layer 112D) are used as power rails, the metal traces may be merged with metal cell traces from adjacent cells. For example, Figure 1 As shown, the top side metal layer 112D' may be in the adjacent cell in the cell height direction (in Figure 1100 in the depiction of FIG. 100). A power rail merging layer 109 (dashed box) may then be implemented to merge the topside metal layer 112A in the cell 100 with the topside metal layer 112D' in the adjacent cell above. In various embodiments, the power rail merging layer 109 is a metal layer that connects the topside metal layer 112A and the topside metal layer 112D'. In some contemplated embodiments, the topside metal layer 112A, the topside metal layer 112D', and the power rail merging layer 109 may be a single metal trace formed in the cell 100 and the adjacent cells.

[0084] In other contemplated embodiments for merging metal traces, metal traces at or near the center of the cell that serve as power rails may be merged. Figure 1 As shown, power rail merging layer 111 (dashed box) can be implemented to merge topside metal layer 112B and topside metal layer 112C when these layers are used as power rails. Power rail merging layer 111 can be, for example, a metal that connects topside metal layer 112B and topside metal layer 112C. In some cases, topside metal layer 112B, topside metal layer 112C, and power rail merging layer 111 can be a single metal trace in cell 100.

[0085] It should be pointed out that in Figures 1 to 6 In the depicted embodiment of the cell 100, additional contacts for control signals and power signals are not shown in the drawings for simplicity, it being understood that various connections may be made between the depicted metal traces and transistor components within the cell. For example, any metal trace (e.g., any of the topside metal layers 112A, 112C, 112D or any of the backside metal layers 120A and 120C) may be connected to any gate (e.g., upper gate 108 or lower gate 116) or source / drain region 124 within the cell 100 as required by the desired device structure. Thus, Figures 1 to 6 The depicted structure of the cell 100 with components (e.g., gates 108 / 116 and source / drain regions 124) and metal traces (e.g., topside metal layer 112 and backside metal layer 120) provides a basic building block structure from which different variations of the connections between the components and the metal traces can be made to generate many different types of devices.

[0086] like Figures 1 to 6 As shown, upper gate 108 and lower gate 116 may be formed in cell 100 where the relationship between the gates in the stacked transistor structure is different. Figure 3 and Figure 4Two possible implementations of the gate relationship are described in FIG. 1 . In a first contemplated implementation, the upper gate 108A is merged with the lower gate 116A, thereby creating connectivity between the gates. The connectivity created by the merging of the gates allows a single control signal to be provided to both gates. For example, Figure 3 and Figure 4 As shown, due to the connectivity between the gates, the control signal provided from the top side metal layer 112B to the upper gate 108A through the contact 114 can be passed and used as the control signal of the lower gate 116A. It should be noted that in Figure 5 A merged gate configuration is also shown in the cross-sectional representation of . A second contemplated embodiment includes an upper gate 108B that is separated (e.g., split) from a lower gate 116B. Separating the upper gate 108B and the lower gate 116B keeps the gates electrically disconnected. Therefore, the upper gate 108B and the lower gate 116B will require separate control signals because the control signal cannot be passed between the gates due to the separation / segmentation between the gates.

[0087] Although in Figures 1 to 6 , but in various embodiments, the source / drain region 124 can also be merged between the upper transistor and the lower transistor. An example of a merged source / drain region is shown in FIG. Figures 13 to 16 As shown in FIG. 1 , as described below. The merging of the source / drain regions 124 may allow a single power supply signal to connect power to both the upper transistor and the lower transistor or a single control signal (e.g., a single output signal from the drain) to both the upper transistor and the lower transistor. Similar to the segmentation of the gate, when the source / drain regions 124 are segmented, separate connections (e.g., Figures 1 to 6 shown).

[0088] In some embodiments, power routing for transistors in cell 100 (eg, upper transistors and lower transistors) is divided between topside metal layer 112 and backside metal layer 120. For example, Figure 2 , Figure 4 , Figure 6As shown, the backside metal layer 120B is connected to the source / drain region 124F through the backside via 122. Therefore, in some embodiments, the power supply to the lower gate 116B in the lower transistor (e.g., a transistor having an active area 206) is routed from the backside metal layer 120B. In order to divide the power supply, the power supply to the upper gate 108B can be routed from one of the topside metal layers (e.g., the topside metal layer 112C) that is not used for the control signal. Therefore, the upper gate 108B and the lower gate 116B will have separate power rails that provide power to the gate / transistor. Dividing the power supply wiring between the topside metal layer 112 and the backside metal layer 120 can provide more efficient power supply wiring in the cell 100.

[0089] Additional embodiments are contemplated in which power routing is provided from one or the other of the topside metal layer 112 and the backside metal layer 120, but not both layers. For example, as described above, the source / drain regions may be merged, and a single power signal from either the top side or the back side may be provided to the merged region. In another contemplated embodiment, power may be introduced into the cell 100 through a backside metal layer, such as backside metal layer 120A, and vias may route power from the backside metal layer to one of the topside metal layers, which is then connected to the source / drain regions in the upper transistor. The vias may be positioned in an open channel in the cell 100 between the topside metal layer and the backside metal layer. An example of a via is in Figure 6 , where vias 600 (dashed lines) are optionally routed between the topside metal layer 112A and the backside metal layer 120A in the space (e.g., channel) outside the source / drain regions 124C / 124F. The topside metal layer 112A can then be connected (directly or through another topside metal layer) to the source / drain regions 124C to provide power in the upper transistor. Note that Figure 6 The illustrated via 600 may also be used to route signals between the topside metal layer and the backside metal layer.

[0090] Yet another alternative for routing power from the backside layer to the upper portion may include extending the source / drain region 124C to intersect and connect with the via 600, such as Figure 6 The dotted line extending from the source / drain region 124C in FIG. 1 will create a direct connection between the via 600 and the source / drain region 124C. Figures 7 to 12 Other examples of extensions (both gate and source / drain regions) are provided that describe implementations of via posts in the cell (eg, on the perimeter of the cell).

[0091] As discussed above, Figures 1 to 6The embodiment of the depicted cell 100 provides the basis for realizing a compact standard cell structure of two vertically stacked transistors. The transistors can be heterogeneous (e.g., two different types of transistors) or homogeneous (e.g., transistors of the same type). The cell 100 realizes the availability of connection from any of the topside metal layer and the backside metal layer to any of the various transistor components including the gate and the source / drain region. The adaptability of the connection of both the control signal and the power supply for the transistor components allows the basic structure of the cell 100 to be suitable for a wide range of logic schemes to realize different integrated circuit devices using stacked transistors. The compactness of the cell 100 allows the cell with stacked transistors to be realized within the current standard cell design and manufacturing constraints.

[0092] In some cases, placing cell 100 next to an adjacent cell may cause manufacturing problems due to routing traces along the border of the cell. In the case of routing traces along the border, vias from the routing traces may create spacing problems between adjacent cells. One possible solution to this border problem is to replace the routing traces along the edge with via traces, where the vias are alternately used by the current cell and the adjacent cell.

[0093] Figure 7 A top plan view representation of a cell with alternating vias along a border according to some embodiments is depicted. In cell 700, three top side metal layers 112A, 112B, 112C are positioned between via routing 705A and via routing 705B. Via routing 705A and via routing 705B are placed along the border (e.g., edge) of cell 700. Via routing 705A and via routing 705B include via posts 710. In certain embodiments, via posts 710A and via posts 710B are included, wherein via posts 710A belong to cell 700, and via posts 710B belong to adjacent cells. In various embodiments, via posts 710 are placed on the periphery of the cell and are used to provide routing in the interior of cell 700 for either control signal or power signal. It should be noted that adjacent cells may have a mirror image setting of cell 700 to accommodate alternating via post arrangements.

[0094] It is conceivable to connect to Figure 7 Various embodiments of via pillar 710A are shown within cell 700. Embodiments may include routing connections to gate or source / drain regions within cell 700. Figure 8 and Fig. 9 Depicted is a cross-sectional representation of source and drain connections in a cell implementing a via post according to some embodiments. Figure 8 is a cross-sectional representation of cell 800 showing connections to source regions 124A, 124B, and Fig. 9is a cross-sectional representation of cell 800 showing connections to drain regions 124C, 124D.

[0095] In various embodiments, such as Figure 8 As shown, the source regions 124A, 124B are directly connected to the top side metal layer 112B and the back side metal layer 120A, respectively, through the contacts 114. The top side metal layer 112B and the back side metal layer 120A can then be routed to a power source (e.g., Vdd) or ground (e.g., Vss) for power connection to the source regions 124A, 124B. For the drain regions 124C, 124D, as shown in FIG. Fig. 9 As shown, the contact 114 is horizontally routed to the via post 710A. The via post 710A can then be routed to the top side metal layer 112 or the back side metal layer 120 for signal connection. In some embodiments, the contact 114 of the drain region 124C, 124D can be replaced by extending the drain region 124C, 124D horizontally to connect with the via post 710A.

[0096] Fig.10 Depicted is a cross-sectional representation of stacked transistor control signal connections in a cell implementing a via post according to some embodiments. Fig.10 , the cell 1000 includes source / drain regions 124A, 124B connected to the topside metal layer 112C and the backside metal layer 120B, respectively, through the contact 114. The topside metal layer 112C and the backside metal layer 120B may be wirings for control signals provided to the source / drain regions 124A, 124B.

[0097] The via post 710A may also provide routing for control signals from the gates in various embodiments of the stacked transistor. For example, the gates may be coupled as a common gate or a split gate (eg, as used in a transmission gate). Fig.11 Depicted is a cross-sectional representation of stacked transistor control signal connections in a common gate configuration according to some embodiments. In cell 1100, upper gate 108A and lower gate 116A extend to intersect and connect and to via post 710A to connect these gates together. Fig.12 Depicted is a cross-sectional representation of stacked transistor control signal connections in a split gate configuration according to some embodiments. In cell 1200, upper gate 108A is connected to topside metal layer 112C via contact 114, and lower gate 116A extends to intersect and connect with via post 710A. Topside metal layer 112C and via post 710A may then be cross-coupled to cross-couple upper gate 108A and lower gate 116A.

[0098] Example NAND cell with stacked transistors

[0099] Figures 13 to 18 Depicted is a representation of an exemplary NAND cell according to some embodiments. Fig.13 A top side plan view representation of a NAND cell 1300 is depicted, according to some embodiments. Fig.14 A backside plan view representation of a NAND cell 1300 is depicted, according to some embodiments. Fig.15 Depicted is a NAND cell 1300 along Fig.13 and Fig.14 A cross section along line AA' is shown. Fig.16 Depicted is a NAND cell 1300 along Fig.13 and Fig.14 A cross section along line BB' is shown.

[0100] Fig.17 Depicted is a NAND cell 1300 along Fig.13 and Fig.14 A cross-section representation of line CC' is shown.

[0101] Fig.18 Depicted is a NAND cell 1300 along Fig.13 and Fig.14 A cross-section representation of the line DD' is shown.

[0102] In certain embodiments, Fig.13 depicts structures associated with an active region 104 of an upper transistor (eg, an NMOS active region) in a vertically stacked transistor (from the top side), and Fig.14 Structures associated with the active region 106 of the lower transistor (e.g., PMOS active region) in the vertically stacked transistors are depicted (from the back side). In the illustrated embodiment, the topside metal layer 112D is a ground rail (e.g., a VSS rail), while the backside metal layer 120B is a power rail (e.g., a VDD rail). The remaining topside metal layers (e.g., topside metal layers 112A, 112B, 112C) and backside metal layers (e.g., backside metal layers 120A, 120C) may be used for signal routing and / or internal routing within the NAND cell 1300, as described below.

[0103] In the illustrated embodiment, Fig.13As shown, NAND cell 1300 includes upper gate 108A and upper gate 108B, which are active NMOS gates located inside the cell. Isolation gates 110A, 110B (e.g., dummy gates) are located at opposite ends of cell 1300 in the gate spacing direction, and upper contact 126A is located between isolation gate 110A and upper gate 108A, upper contact 126B is located between upper gate 108A and upper gate 108B, and upper contact 126C is also located between upper gate 108B and isolation gate 110B in the gate spacing direction. Further in the illustrated embodiment, as Fig.14 As shown, the NAND cell 1300 includes a lower gate 116A and a lower gate 116B, which are active PMOS gates located inside the cell. In the gate spacing direction, a lower contact 126D is located between the isolation gate 110A and the lower gate 116A, a lower contact 126E is located between the lower gate 116A and the lower gate 116B, and a lower contact 126F is located between the lower gate 116B and the isolation gate 110B.

[0104] In various embodiments, such as Fig.13 and Fig.15 As shown, contact 114A provides a connection between contact 126A and topside metal layer 112D (e.g., ground rail). Contact 126A is also connected to source / drain region 124A of upper gate 108A. Note that Figures 15 to 18 Six source / drain regions 124A-F are depicted in NAND cell 1300, where source / drain regions 124A-C are upper source / drain regions and source / drain regions 124D-F are lower source / drain regions. In NAND cell 1300, upper source / drain regions 124A-C are separated from lower source / drain regions 124D-F. Additionally, upper source / drain regions 124A-C and upper gates 108A, 108B include upper channels 1304, while lower source / drain regions 124D-F and lower gates 116A, 116B include lower channels 1306.

[0105] Fig.13 and Fig.16 The contact 114B shown provides a connection between the upper gate 108A and the topside metal layer 112B, which can be a route for input signals to the device of the NAND cell 1300. The NAND cell 1300 also includes a contact 114D (at Fig.13 and Fig.18 ), which may be a route for an output signal from the device of NAND cell 1300.

[0106] In the contemplated implementation of NAND cell 1300, the upper gate and the lower gate are merged. Fig.16 As shown, the upper gate 108A is merged into the lower gate 116A. Thus, the contact 114B provides a connection (e.g., an input signal route) between the merged upper gate 108A and lower gate 116A and the topside metal layer 112B. The upper gate 108B and the lower gate 116B can be similarly merged and connected to the contact 114C (at Fig.13 ), which contact then provides a connection to the top side metal layer 112C, which can be a second route for the input signal to the NAND cell 1300 device.

[0107] In various embodiments, NAND cell 1300 includes backside via 122A and backside via 122C, such as Fig.14 , Fig.15 , Fig.17 and Fig.18 The backside via 122A provides a connection between the lower contact 126D and the backside metal layer 120C, as shown. Fig.14 and Fig.15 The back metal layer 120C is also connected to the lower contact 126F through the back via 122C, as shown in FIG. Fig.14 and Fig.18 Thus, backside metal layer 120C provides an internal (to-cell) routing path between lower contact 126D (which is connected to lower source / drain region 124D of lower gate 116A) and lower contact 126F (which is connected to lower source / drain region 124F of lower gate 116B).

[0108] In some embodiments, NAND cell 1300 includes via 1302A and via 1302B. Via 1302A and via 1302B are top-to-back vias that connect upper contact 126C to lower contact 126F, such as Fig.13 , Fig.14 and Fig.18 Thus, vias 1302A and 1302B provide connections between the upper source / drain region 124C of the upper gate 108B and the lower source / drain region 124F of the lower gate 116B. Fig.13 and Fig.14 In the depiction of FIG. 1 , via 1302A and via 1302B may be partially hidden from view by contact 114D and backside via 122C, respectively.

[0109] NAND cell 1300 also includes backside vias 122B, such as Fig.14 and Fig.17As shown. The backside via 122B provides a power connection to the lower source / drain region 124E (from the backside metal layer 120B which is the power rail). The lower source / drain region 124E is shared by the lower gate 116A and the lower gate 116B in the lower active region 106. Therefore, because the lower gate 116A and the lower gate 116B are merged to the upper gate 108A and the upper gate 108B respectively, power supply is provided to all active gates through the backside via 122B.

[0110] Complementary FETSRAM Cell

[0111] In various implementations, a stacked transistor, such as those described herein, may be implemented in a memory cell, such as an SRAM cell. Fig.19 A schematic representation of a memory cell is depicted. For example, cell 1700 is a 6T SRAM memory cell. Cell 1700 includes two inverters 1710A, 1710B, which are cross-coupled with inputs fed into outputs at nodes 1712 and 1714. Node 1712 is coupled to the output of pass gate 1720, and node 1714 is coupled to the output of pass gate 1722. Pass gates 1720, 1722 may sometimes be referred to as "access gates" or "transmission gates". Word line 1730 is coupled to pass gate 1720 and pass gate 1722 to provide control signals to these pass gates. Bit line 1740 is coupled to pass gate 1720 to read / write data from the pass gate. Bit line 1742, which is complementary to bit line 1740, is coupled to pass gate 1722 to read / write data from the pass gate.

[0112] Cell 1700 includes six transistors—two in each inverter and one in each pass gate—through inverter 1710A, inverter 1710B, pass gate 1720, and pass gate 1722. In some embodiments, inverter 1710 includes two complementary transistors—for example, each inverter includes an NMOS transistor and a PMOS transistor. Pass gates 1720, 1722 can be transistors of the same type. In one embodiment, both pass gates are NMOS transistors. Thus, in various embodiments, cell 1700 includes four NMOS transistors and two PMOS transistors.

[0113] The present disclosure contemplates various techniques for implementing stacked transistors in memory cells. For example, a stacked transistor such as described above may be implemented in a Fig.19 6T SRAM memory cell shown. The disclosed embodiments utilizing stacked transistors in the memory cell provide the ability to minimize spacing along with multiple transistors in the memory cell. Thus, the disclosed embodiments of the memory cell include multiple transistors at a small scale factor.

[0114] Certain embodiments disclosed herein have five main elements: 1) a first transistor region having a first active region and a second active region in parallel; 2) a second transistor region having a third active region and a fourth active region in parallel, wherein the second transistor region is positioned vertically below the first transistor region, 3) a first inverter formed by a transistor in the first active region and a transistor in the third active region, 4) a second inverter formed by a transistor in the second active region and a transistor in the fourth active region, and 5) a cross-coupling between the first inverter and the second inverter. In certain embodiments, the source / drain regions in the inverters are merged. For example, the source / drain regions on opposite sides of the gates of the two transistors in the first inverter may be merged. In certain embodiments, the cross-coupling is achieved by coupling the horizontal extension of the gate of the transistor in the third active region with the source / drain region of the transistor in the fourth active region and coupling the horizontal extension of the gate of the transistor in the fourth active region with the source / drain region of the transistor in the third active region.

[0115] In various embodiments, the horizontally extending portion of the gate used for cross-coupling is the portion that is toward another active region and possibly extends therein (e.g., the gate of the transistor in the third active region has a portion that extends into the fourth active region). Extended gates as described herein allow cross-coupling connections to be made in the cell region vertically below the active region of the memory cell. The cross-coupling may also be positioned vertically above any backside layer wiring. By removing material in the inactive portions of the third and fourth active regions, the region may be used for cross-coupling.

[0116] In short, the inventors have recognized that stacked transistors can be implemented in a memory cell together with the removal of material for the inactive portion of the active area to achieve cross-coupling of inverters formed by transistors in the memory cell. The cross-coupling of the inverters in the area for the inactive portion provides a memory cell configuration that maintains current design concepts while also reducing the cell height compared to a typical memory cell. The cell height can be reduced because the use of cross-coupling in the area below the active area allows the active areas to be vertically positioned closer together. Therefore, minimizing the vertical spacing between the active areas allows the overall height of the memory cell to be reduced.

[0117] Fig. 20 Depicted is a top-side plan view representation of a memory cell 1800 having stacked transistors, according to some embodiments. Fig.21 Depicted is a backside plan view representation of a memory cell 1800 having stacked transistors, according to some embodiments. Fig. 22 Depicted is a storage unit 1800 along Fig. 20 and Fig.21 A cross section along line AA' is shown. Fig.23 Depicted is a storage unit 1800 along Fig. 20 and Fig.21 A cross section along line BB' is shown. Fig.24 Depicted is a storage unit 1800 along Fig. 20 and Fig.21 A cross-section representation of line CC' is shown.

[0118] In order to simplify the drawings, only components relevant to the present disclosure are shown in the representation of the units disclosed herein. It will be understood by those skilled in the art that additional components may be present in any of the units described herein. For example, in Fig. 20 and 21 In some depictions, various connections (such as vias or contacts as described herein) may be visible. Additionally, to better understand the disclosed embodiments, a degree of material transparency is provided to enable the underlying components to be seen in top and back plan views. For example, in Fig. 20 and Fig.21 In the embodiment, the gate (e.g., polysilicon line) and source / drain regions have a certain degree of transparency to provide visibility of the active areas in the vias / contacts and the transistor underlying regions, and in Fig. 20 and Fig.21 In , the topside metal layer and the backside metal layer have transparency to provide visibility of transistors that would be hidden in the plan view. Figure 22 to Figure 24 The depth of the various components can be more clearly seen in the cross-sectional representation of FIG. Figure 22 to Figure 24 The top side metal layer is not depicted in the cross-sectional representation of FIG.

[0119] In the illustrated embodiment, the cell 1800 includes two upper active regions 1810, 1820 (in Fig. 20 ) and two lower active regions 1830, 1840 (shown in Fig.21 In some embodiments, the upper active regions 1810, 1820 are active regions for NMOS transistors, and the lower active regions 1830, 1840 are active regions for PMOS transistors. The lower active regions 1830, 1840 may include inactive portions 1833, 1842 ( Fig.21 ). The inactive portions 1833, 1842 may be formed by not having diffusion material in these portions (e.g., by removing the diffusion material or not having the diffusion material deposited in these portions) or by disconnecting the diffusion material from the active portions of the lower active regions 1830, 1840 (e.g., by an isolation structure or mechanism).

[0120] Upper active region 1810 is separated from upper active region 1820 by diffusion to diffusion spacing distance 1815. Similarly, lower active region 1830 is separated from lower active region 1840 by diffusion to diffusion spacing distance 1835. In some embodiments, distance 1815 and distance 1835 are substantially the same distance.

[0121] In the illustrated embodiment, the upper active region 1810 includes an upper gate 1812 between the source / drain region 1814A and the source / drain region 1814B and an upper gate 1816 between the source / drain region 1814B and the source / drain region 1814C. The upper active region 1820 includes an upper gate 1822 between the source / drain region 1824A and the source / drain region 1824B and an upper gate 1826 between the source / drain region 1824B and the source / drain region 1824C. The upper gates 1812, 1816, 1822, 1826 may be polysilicon gates or other types of gates for FET transistor devices. In one embodiment, the upper gates 1812, 1816, 1822, 1826 are NMOS gates.

[0122] In certain embodiments, upper gate 1812 is separated from upper gate 1822 and upper gate 1816 is separated from upper gate 1826. For example, the polysilicon for upper gate 1812 is not connected to the polysilicon for upper gate 1822. Similarly, the polysilicon for upper gate 1816 is not connected to the polysilicon for upper gate 1826. The upper gates may be separated by cutting the polysilicon between the upper gates (e.g., cutting the polysilicon between upper active region 1810 and upper active region 1820) or forming the upper gates from separate polysilicon layers in upper active region 1810 and upper active region 1820. The separation of the upper gates between upper active region 1810 and upper active region 1820 provides a distinction between transistors formed by these upper gates to allow the upper gates to form transistors for inverters and pass gates, as described herein.

[0123] In the illustrated embodiment, the lower active region 1830 includes a lower gate 1832 between the source / drain region 1834A and the source / drain region 1834B. The lower active region 1840 includes a lower gate 1846 between the source / drain region 1844B and the source / drain region 1844C. It should be noted that due to the presence of the inactive portions 1833, 1842, there are only two gate regions in the lower active regions 1830, 1840, and only two transistors are required to combine with the four transistors in the upper active region to form a memory cell device. The lower gates 1832, 1846 can be polysilicon gates or other types of gates for FET transistor devices. In one embodiment, the lower gates 1832, 1846 are PMOS gates.

[0124] In certain embodiments, such as Fig.21 As shown, portions of lower gate 1832 and lower gate 1846 extend across separation distance 1835 between lower active region 1830 and lower active region 1840. Fig. 20 In the depiction of , portions of lower gate 1832 and lower gate 1846 extending across the separation distance can also be seen in the gap between upper active region 1810 and upper active region 1820. In some embodiments, portions of lower gate 1832 and lower gate 1846 extending across separation distance 1835 extend below the transistor region of another lower active region. For example, Fig. 20 and Fig.21 As shown, lower gate 1832 extends into the transistor region surrounding lower active region 1840, which is below the transistor region surrounding upper active region 1820. Similarly, lower gate 1846 extends into the transistor region surrounding lower active region 1830, which is below the transistor region surrounding upper active region 1810. In some embodiments, portions of lower gate 1832 and lower gate 1846 extend below the transistor region defining a through gate in the upper active region, as described in more detail below. The extension of lower gate 1832 and lower gate 1846 across the active region provides the ability to be used for cross-coupling connections in cell 1800, also described in more detail below.

[0125] An exemplary embodiment of a 6T (six transistor) SRAM memory cell that may be implemented in the cell 1800 is now described with respect to various connections made within the cell to implement six transistors (e.g., four NMOS transistors and two PMOS transistors) arranged as inverters and pass gates. It should be understood that various additional embodiments of memory cells may be envisioned based on the disclosed structure of the cell 1800. Fig.19As shown, the 6T SRAM memory cell includes two NMOS transistors and two PMOS transistors arranged to form two inverters, which are then cross-coupled. Two more NMOS transistors are then arranged to form a pass gate connected to the inverters.

[0126] Returning to unit 1800, Fig. 20 The upper gate 1812 shown together with the source / drain region 1814A and the source / drain region 1814B can form the first NMOS transistor 1850 of the inverter 1710A. Fig.21 As shown, the lower gate 1832 together with the source / drain region 1834A and the source / drain region 1834B can form the first PMOS transistor 1852 of the inverter 1710A. To form the inverter 1710A with the transistor 1850 and the transistor 1852, the source / drain region 1814A is merged with the source / drain region 1834A through the S / D merge 1860A. The S / D merge 1860A can be, for example, a via or other substantially vertical connection formed between the source / drain region 1814A and the source / drain region 1834A. The merging of the source / drain region 1814A with the source / drain region 1834A merges the power connection between the transistor 1850 and the transistor 1852.

[0127] Additionally, for transistor 1850 and transistor 1852, source / drain region 1814B is merged with source / drain region 1834B via S / D merge 1860B (eg, Fig. 22 ). The merging of source / drain region 1814B and source / drain region 1834B merges the outputs of transistor 1850 and transistor 1852. The inputs of transistor 1850 and transistor 1852 may be merged by merging upper gate 1812 with lower gate 1832 using gate merge 1862A. Fig.23 As shown, gate merge 1862A may be a via or other substantially vertical connection formed between upper gate 1812 and lower gate 1832. With the inputs and outputs of transistors 1850 and 1852 merged, these transistors form inverter 1710A.

[0128] Fig.19 The inverter 1710B shown can be similarly formed by Fig. 20 and Fig.21 The second NMOS transistor 1854 and the second PMOS transistor 1856 are formed as shown. The transistor 1854 can be formed by the upper gate 1826 together with the source / drain region 1824B and the source / drain region 1824C, as shown in FIG. Fig. 20As shown. Transistor 1856 can be formed by lower gate 1846 together with source / drain region 1844B and source / drain region 1844C, as shown. Fig.21 Source / drain region 1814A is merged with source / drain region 1834A via S / D merge 1860A.

[0129] To form inverter 1710B having transistor 1854 and transistor 1856, source / drain region 1824B is connected by S / D merge 1860C (also in FIG. Fig. 22 ) is merged with source / drain region 1844B, and source / drain region 1824C is merged with source / drain region 1844B via S / D merge 1860D (also shown in FIG. Fig.24 1844C). The merging of source / drain region 1824B and source / drain region 1844B merges the outputs of transistor 1854 and transistor 1856, while the merging of source / drain region 1824C and source / drain region 1844C merges the power supply connection between transistor 1854 and transistor 1856. The inputs of transistor 1854 and transistor 1856 are then merged by merging upper gate 1826 with lower gate 1846 using gate merge 1862B. With the inputs and outputs of transistor 1854 and transistor 1856 merged, these transistors form inverter 1710B.

[0130] In various embodiments, in addition to the inverters 1710A, 1710B, the cell 1800 also provides the availability for forming the pass gate 1720 and the pass gate 1722. For example, the pass gate 1720 can be formed with the third NMOS transistor 1858, and the pass gate 1722 can be formed with the fourth NMOS transistor 1859, as shown in FIG. Fig. 20 As shown. It should be noted that both transistor 1858 and transistor 1859 are formed without any underlying PMOS transistor (e.g., above the inactive portion of the lower active region). In the illustrated embodiment, transistor 1858 is formed by upper gate 1822 together with source / drain region 1824A and source / drain region 1824B. Transistor 1859 is formed by upper gate 1816 together with source / drain region 1814B and source / drain region 1814C.

[0131] Both upper gate 1816 and upper gate 1822 may be coupled to a word line (e.g., word line 1730) for transmitting control signals to these gates. A read / write data connection to a bit line (e.g., bit line 1742) of upper gate 1816 may be provided through source / drain region 1814C, while a read / write data connection to a bit line (e.g., bit line 1740) of upper gate 1822 may be provided through source / drain region 1824A. The output of transistor 1859 (which corresponds to pass gate 1722) is provided through source / drain region 1814B, which is also the output of transistor 1850 and is combined with the output of transistor 1852 in inverter 1710A. Accordingly, the output of transistor 1858 (which corresponds to pass gate 1720) is provided through source / drain region 1824B, which is also the output of transistor 1854 and is combined with the output of transistor 1856 in inverter 1710B. Fig.19 , transistors 1858, 1859 provide pass gate transistors 1720, 1722 coupled to inverter 1710A and inverter 1710B.

[0132] As discussed above, in some embodiments, lower gate 1832 (in transistor 1852 of inverter 1710A) and lower gate 1846 (in transistor 1856 of inverter 1710B) extend toward the inactive portion of the active region relative to the transistor region. These extensions provide the ability to provide cross-coupling between inverters below the active region of cell 1800. For example, Fig.23 As shown, the lower gate 1832 extends below the gate 1822 formed in the active region 1820. Through the extension of the lower gate 1832, the cross-coupling 1864B can be coupled between the lower gate 1832 (which is the merged PMOS transistor gate in the inverter 1710A) and the source / drain region 1844B (which is the merged PMOS source / drain region in the inverter 1710B). Therefore, the cross-coupling 1864B cross-couples the input of the inverter 1710A and the output of the inverter 1710B. Similarly, Figure 20 to Figure 22 Cross-coupling 1864A is shown to couple the input of inverter 1710B (via coupling to the extension of lower gate 1846) and the output of inverter 1710A (via coupling to source / drain region 1834B, as shown in FIG. Fig. 22 cross coupling as shown).

[0133] In some embodiments, cross couplings 1864A, 1864B are positioned below the active region in cell 1800 and above backside metal layer 120. For example, Fig. 22 and Fig.23As shown, cross-couplings 1864A, 1864B are coupled to the back side (e.g., bottom) of the lower gate and source / drain regions in the lower transistor region of the PMOS transistor. Due to the removal of material in the inactive portions 1833, 1842 of the lower active regions 1830, 1840, cross-couplings 1864A, 1864B can be placed in this region. Cross-couplings 1864A, 1864. The use of cross-couplings 1864A, 1864B in cell 1800 maintains the current design philosophy of SRAM cells while reducing the cell height relative to typical SRAM cells. For example, cross-couplings 1864A, 1864B as implemented with lower gate 1832 and lower gate 1846 provide better area scaling in cell 1800 by allowing both upper active regions 1810, 1820 and lower active regions 1830, 1840 to be closer together. For example, in some embodiments, upper active regions 1810, 1820 and lower active regions 1830, 1840 can be positioned with a minimum required spacing between diffusion regions in the active regions. Achieving the minimum required spacing can reduce the height of cell 1800 to about 1 / 2 of the typical height of a 6T SRAM cell.

[0134] Macro SRAM Cell

[0135] In various embodiments, in addition to being implemented in memory cells such as SRAM cells (e.g., SRAM bit cells), stacked transistors such as those described herein may also be implemented in peripheral cells associated with SRAM cells. For example, the present disclosure contemplates various techniques for implementing column input / output logic cells that include stacked transistors. Implementing stacked transistors in peripheral cells (such as column input / output logic cells) may allow for the utilization of both top-side and back-side wiring in memory devices that include various types of SRAM cells (including various embodiments of SRAM cells described herein).

[0136] Certain embodiments disclosed herein have four main elements: 1) a plurality of bit cells formed in a first transistor region and a second transistor region disposed vertically relative to each other; 2) a first metal layer (e.g., a topside metal layer) located above the bit cells and a second metal layer (e.g., a backside metal layer) located below the bit cells, 3) a first column input / output logic unit coupled to a first array of bit cells, and 4) a second column input / output logic unit coupled to a second array of bit cells, wherein the second array of bit cells is closer to the logic unit than the first array of bit cells. In certain embodiments, the first metal layer includes a first wiring that couples the first array of bit cells to the first column input / output logic unit, and the second metal layer includes a second wiring that couples the second array of bit cells to the second column input / output logic unit. In some embodiments, the column input / output logic unit implements a stacked transistor, such as those described herein.

[0137] Thus, in various embodiments, a first column input / output logic cell provides column I / O logic for bit cells that are further away from a peripheral region of the device, while a second column input / output logic cell provides column I / O logic for bit cells that are closer to a peripheral region of the device. Splitting the wiring between the topside metal layer and the backside metal layer reduces wiring congestion compared to using only topside wiring or backside wiring for wiring logic in a memory device. In various embodiments, dummy cells can be used for local wiring of bit line signals between the topside metal layer and the backside metal layer. For example, dummy cells can be used for local wiring near the bit cells of the first array (e.g., bit cells that are far away from the logic cell).

[0138] In short, the inventors have recognized that metal congestion in a memory device can be alleviated by routing column I / O logic in both the topside metal layer and the backside metal layer in the memory device. Additionally, when both the topside metal layer and the backside metal layer are used to route logic between bit cells and logic cells, various techniques are implemented to reduce any area penalty associated with transitioning from front to back (or vice versa). In some embodiments, various routing paths provide reduced resistance paths for logic within the memory device. Through various embodiments of the disclosed techniques, the disclosed embodiments of the memory device can have strong signal connectivity, which has improved read / write speeds and therefore improved performance.

[0139] Fig.25A block diagram representation of a memory device according to some embodiments is depicted. In the illustrated embodiment, the memory device 2300 includes a memory cell region 2310 and a logic circuit cell region 2320. The memory cell region 2310 includes a plurality of bit cells that can be divided into a far bit cell array 2312A and a near bit cell array 2312B. The bit cells in the array can be, for example, the SRAM cells 1800 described above. The far bit cell array 2312A includes a plurality of bit cells that are located farther away from the logic circuit cell region 2320 than the bit cells in the near bit cell array 2312B, such as Fig.25 Depicted.

[0140] In various embodiments, the logic circuit unit region 2320 includes a plurality of column input / output (I / O) logic units 2322. The column I / O unit 2322 may, for example, manage reads / writes from the bit cell array 2312. The column I / O unit 2322 may also include portions of sense amplifiers. It should be understood that the logic circuit unit region 2320 may include other logic units in addition to the column input / output (I / O) logic units 2322. For example, the logic circuit unit region 2320 may also include power switch logic units, word line logic circuit units, local I / O circuit units, global I / O circuit units, and the like. In some embodiments, the logic circuit unit region 2320 may be referred to as a peripheral region of the memory device 2300.

[0141] In the contemplated embodiment, the logic circuit cell region 2320 includes a separate column I / O logic cell 2322 for each bit cell array in the memory cell region 2310. For example, in the illustrated embodiment, the logic circuit cell region 2320 includes a first column I / O logic cell 2322A and a second column I / O logic cell 2322B because the memory cell region 2310 has two bit cell arrays 2312A, 2312B.

[0142] In various embodiments, the first column I / O logic cell 2322A provides column I / O logic for the far bit cell array 2312A, and the second column I / O logic cell 2322B provides column I / O logic for the near bit cell array 2312B. Routing in both the topside metal layer 112 and the backside metal layer 120 may be used in the memory device 2300 to alleviate metal congestion in the memory device. The present disclosure contemplates a routing method that also reduces any front-to-back transition region losses while utilizing the topside metal layer 112 and the backside metal layer 120 in the routing logic between the bit cells and the logic cells.

[0143] In certain embodiments, the memory device 2300 uses both the topside metal layer 112 and the backside metal layer 120 for bit line routing in the memory device. For example, the topside metal layer 112 may be used for bit line routing between the near bit cell array 2312B and the second column I / O logic unit 2322B, and the backside metal layer 120 may be used for bit line routing between the far bit cell array 2312A and the first column I / O logic unit 2322A. In the illustrated embodiment, the bit line 1740A and the bit line 1742A provide bit line routing in the far bit cell array 2312A, and the bit line 1740B and the bit line 1742B provide bit line routing in the near bit cell array 2312B. As described herein, the bit line 1740 and the bit line 1742 may be complementary bit lines.

[0144] like Fig.25 As shown, bit line 1740A and bit line 1742A in remote bit cell array 2312A are coupled to bit line output 2314A and bit line output 2316A, respectively. Bit line output 2314A is then coupled to backside bit line wiring 2330 and bit line output 2316A is coupled to backside bit line wiring 2332. In some embodiments, bit line 1740A and bit line 1742A are located in topside metal layer 112. For example, Fig.19 and Fig. 20 As shown, the output of the pass-gate transistor is in the upper transistor region and coupled to the topside metal layer 112. Because the bit line 1740A and the bit line 1742A are routed in the topside metal layer 112, as shown in FIG. Fig.25 As shown, a transition is required from the top side metal layer to the back side metal layer 120, where the back side bit line wiring 2330 and the back side bit line wiring 2332 are located.

[0145] In some embodiments, dummy cells 2340A, 2340B are positioned at or near bit line outputs 2314A, 2316A, respectively. Dummy cell 2340A includes a connection between bit line 1740A in topside metal layer 112 and backside bit line wiring 2330 in backside metal layer 120. Dummy cell 2340B includes a connection between bit line 1742A in topside metal layer 112 and backside bit line wiring 2332 in backside metal layer 120. Fig.26 A top plan view representation of a region with virtual cells 2340 is depicted in accordance with some embodiments. Fig. 27 Depicted is a backside plan view representation of a region having virtual cells 2340 according to some embodiments. Fig.28 A region with virtual cell 2340 is depicted along Fig.26 and Fig. 27 A cross section along line AA' is shown. Fig.29 A region with virtual cell 2340 is depicted along Fig.26and Fig. 27 A cross section along line BB' is shown.

[0146] In various embodiments, such as Fig.26 As shown, in addition to bit line 1740A and bit line 1742A, top side metal layer 112 in region 2400 also includes wiring for ground signal 2401 and word line 2402. In various embodiments, as shown in FIG. Fig. 27 As shown, in addition to the backside bit line wiring 2330 and the backside bit line wiring 2332, the backside metal layer 120 in the region 2400 also includes wiring for the signal 2500 and the power signal 2502. In some embodiments, the dummy gate 2410 is positioned adjacent to the active gate 2440 on both sides of the region 2400. The dummy gate 2410 can be, for example, a gate cutout or other gate that isolates the region between the dummy gates. Isolation can include, for example, prohibiting any gate activity in the region between the dummy gates 2410.

[0147] In some embodiments, the dummy cells 2340A, 2340B include trench metal 2420 formed between the bit line 1742A and the backside bit line wiring 2332 and between the bit line 1740A and the backside bit line wiring 2330, such as Figure 26 to Figure 29 As shown. Bit lines 1740A and 1742A can be connected through vias 2430 (in Fig.26 and Figure 28 to Figure 29 ) is coupled to the trench metal 2420, and the back side bit line wiring 2330, 2332 can be connected through the via 2530 (in Figure 27 to Figure 29 ) is coupled to the trench metal 2420.

[0148] The use of trench metal 2420 for the connection between the bit lines 1740A, 1742A and the backside bit line wiring 2330, 2332 provides a low resistance path for the bit line signal to transition from the topside metal layer 112 to the backside metal layer 120. The dummy cell 2340 provides local flow management for the bit line signal at or near the remote bit cell array 2312A. Although the dummy cell 2340 has some area penalty in the memory device 2300, the area penalty is small because the dummy cell is confined to the shallow metal layer and is not associated with any global wiring.

[0149] Back to Fig.25, after the bit line signals are routed to the backside bit line wiring 2330 and the backside bit line wiring 2332 at the dummy cells 2340A, 2340B, respectively, the backside bit line wiring carries the signals to the bit line input 2324A and the bit line input 2326A at the first column I / O cell 2322A, respectively. As described below, the bit line input 2324A and the bit line input 2326A in the first column I / O cell 2322A (as well as the bit line input in the second column I / O cell 2322B) are inputs in the backside metal layer. Therefore, no additional transition between the topside metal layer 112 and the backside metal layer 120 is required to transfer the bit line signals from the backside bit line wiring 2330 and the backside bit line wiring 2332 to the bit line input 2324A and the bit line input 2326A in the first column I / O cell 2322A.

[0150] Turning now to the near bit cell array 2312B, bit lines 1740B and bit lines 1742B are coupled to bit line outputs 2314B and bit line outputs 2316B, respectively. Bit line outputs 2314B and bit line outputs 2316B are then coupled to top side bit line wiring 2334 and top side bit line wiring 2336, respectively. Since both bit lines 1740B, 1742B and top side bit line wiring 2334, 2336 are located in the top side metal layer 112, no transition between the top side metal layer and the back side metal layer 120 is required at the near bit cell array 2312B.

[0151] In the illustrated embodiment, top side bit line wiring 2334 and top side bit line wiring 2336 carry the bit line signals from the near bit cell array 2312B to the bit line input 2324B and the bit line input 2326B, respectively, at the second column I / O cell 2322B. As noted above and described below, the bit line input 2324B and the bit line input 2326B are positioned in the back side metal layer 120. Therefore, a transition from the top side metal layer 112 to the back side metal layer 120 may be required at the bit line input 2326B and the bit line input 2324B.

[0152] In some embodiments, the dummy cell 2350 is positioned at or near the bit line inputs 2324B, 2326B. The dummy cell 2350 includes a connection between the top side bit line wiring 2334 in the top side metal layer 112 and the bit line input 2324B in the back side metal layer 120, and a connection between the top side bit line wiring 2336 in the top side metal layer 112 and the bit line input 2326B in the back side metal layer 120. Fig.30 Depicted is a top plan view representation of an area with virtual cells 2350 according to some embodiments. Fig.31 Depicted is a backside plan view representation of a region having virtual cells 2350 according to some embodiments. Fig.32 Depicted is a region with virtual cells 2350 along Fig.30and Fig.31 A cross section along line AA' is shown. Fig.33 Depicted is a region with virtual cells 2350 along Fig.30 and Fig.31 A cross section along line BB' is shown.

[0153] In various embodiments, such as Fig.30 As shown, in addition to top side bit line wiring 2334 and top side bit line wiring 2336, top side metal layer 112 in region 2800 also includes wiring for ground signal 2802 and signal 2804. In various embodiments, as shown in FIG. Fig.31 As shown, in addition to the bit line input 2324B and the bit line input 2326B, the backside metal layer 120 in the region 2800 also includes wiring for the signal 2900 and the power signal 2902. In some embodiments, the dummy gate 2810 is positioned adjacent to the active gate 2840 on both sides of the region 2800. The dummy gate 2810 can be, for example, a gate cutout or other gate that isolates the region between the dummy gates. Isolation can include, for example, prohibiting any gate activity in the region between the dummy gates 2810.

[0154] In some embodiments, the dummy cell 2350 includes a trench metal 2820 formed between the top side bit line wiring 2334 and the bit line input 2324B and between the top side bit line wiring 2336 and the bit line input 2326B, such as Figure 30 to Figure 33 The top side bit line wiring 2334, 2336 can be connected through the via 2830 (in Fig.30 and Figure 32 to Figure 33 ) is coupled to the trench metal 2820, and the bit line inputs 2324B, 2326B can be connected through the vias 2930 (in Figure 31 to Figure 33 ) is coupled to the trench metal 2820.

[0155] Similar to dummy cell 2340, the use of trench metal 2820 for connections between topside bitline wiring 2334, 2336 and backside bitline inputs 2324B, 2326B provides a low resistance path for the bitline signal to transition from the topside metal layer 112 to the backside metal layer 120. Dummy cell 2350 provides local flow management for the bitline signal in the logic circuit cell region 2320 (e.g., in the peripheral region).

[0156] Return to Fig.25, like the first column I / O cell 2322A, the bit line inputs 2324B, 2326B in the second column I / O cell 2322B are inputs in the backside metal layer 120. Therefore, after the bit line signals are routed to the bit line inputs 2324B and 2326B by the dummy cell 2350, the second column I / O cell 2322B can receive the bit line signals in the appropriate metal layer. The bit line signals are routed from the memory cell region 2310 to the logic circuit cell region 2320 through a combination of the topside metal layer 112 and the backside metal layer. In various embodiments, the column logic I / O cells 2322 in the logic circuit cell region can have unipolar connectivity in a simple manufacturing scheme.

[0157] In various implementations, column I / O cell 2322 may implement stacked transistors to provide connectivity to the various routing described above for memory device 2300 . Fig.34 A schematic representation of a column I / O cell 2322 is depicted according to some embodiments. In the illustrated embodiment, the cell 2322 includes five PMOS transistors and two NMOS transistors. The PMOS transistors include a PMOS1 transistor 3210, a PMOS2 transistor 3220, a PMOS3 transistor 3230, a PMOS4 transistor 3240, and a PMOS5 transistor 3250. The NMOS transistors include an NMOS1 transistor 3260 and an NMOS2 transistor 3270.

[0158] like Fig.34 As shown, various wiring and connections for transistors in cell 2322 are provided by topside metal layer 112 (solid lines) and backside metal layer 120 (dashed lines). In some embodiments, cell 2322 includes Vdd 3202, Vss 3203, PCH 3204, Rcs 3206, Wcs 3208, word line outputs 3280A, 3280B, and sense outputs 3282A, 3282B. Vdd 3202 provides wiring to power for cell 2322, while Vss 3203 provides wiring to ground. PCH 3204 couples PMOS1 transistor 3210, PMOS2 transistor 3220, and PMOS3 transistor 3230 to form a precharge circuit. Rcs 3206 couples PMOS4 transistor 3240 and PMOS5 transistor 3250 for read column select circuitry, and Wcs 3208 couples NMOS1 transistor 3260 and NMOS2 transistor 3270 for write column select circuitry. Word line outputs 3280A, 3280B provide write outputs from cell 2322, and sense outputs 3282A, 3282B provide read outputs from cell 2322.

[0159] In some embodiments, the transistors in cell 2322 can be formed from stacked transistors as described herein. For example, a PMOS transistor is formed in a lower transistor region and an NMOS transistor is formed in an upper transistor region. Fig.35 Depicted is the layout of unit 2322 according to some embodiments. Fig.35 , the top panel is a topside plan view representation of the upper transistor region 3300, and the bottom panel is a backside plan view representation of the lower transistor region 3350. The upper transistor region 3300 includes an upper active region 3302, and the lower transistor region 3350 includes a lower active region 3352.

[0160] exist Fig.35 In the illustrated embodiment of the upper transistor region 3300 in FIG. 1 , the topside metal layer 112 includes wiring for the bit line input 2324, the bit line input 2326, the Vss 3203, the Wcs 3208, and the word line output 3280A, 3280B. The NMOS1 transistor 3260 includes gates 3262A, 3262B, 3262C and source / drain regions 3264A, 3264B, 3264C, 3264D. The NMOS2 transistor 3270 includes gates 3272A, 3272B, 3272C and source / drain regions 3267A, 3274B, 3274C, 3274D. A dummy gate 3310 (e.g., a gate cutout) separates the NMOS1 transistor 3260 from the NMOS2 transistor 3270. Via 3312 connects gate 3262 and gate 3272 using Wcs 3208. Via 3312 also connects source / drain region 3264A and source / drain region 3264C to word line output 3280A, and source / drain region 3274B and source / drain region 3274D to word line output 3280B. There is also a via 3312 connecting source / drain region 3264B and source / drain region 3264D to bit line input 2324, and connecting source / drain region 3274A and source / drain region 3274C to bit line input 2326.

[0161] exist Fig.353350, the backside metal layer 120 includes wiring for the bit line input 2324, the bit line input 2326, Vdd 3202, PCH 3204, Rcs 3206, and the sense output 3282A, 3282B. The PMOS1 transistor 3210 includes a gate 3212 and source / drain regions 3214A, 3214B. The PMOS2 transistor 3220 includes a gate 3222 and source / drain regions 3214B, 3214C. The PMOS2 transistor 3230 includes a gate 3232 and source / drain regions 3214C, 3214D. The dummy gate 3320 then separates the source / drain region 3214D and the PMOS2 transistor 3230 from the source / drain region 3244A in the PMOS4 transistor 3240. The PMOS4 transistor 3240 includes a gate 3242 and source / drain regions 3244A, 3244B. Another dummy gate 3320 then separates the PMOS4 transistor 3240 from the PMOS5 transistor 3250. The PMOS5 transistor 3250 includes a gate 3252 and source / drain regions 3254A, 3254B.

[0162] Via 3322 connects gate 3212, gate 3222, and gate 3232 through PCH 3204. Via 3322 also connects gates 3242 and 3252 using Rcs 3206. More vias 3322 connect source / drain region 3244B to sense output 3282A and source / drain region 3254B to sense output 3282B. Still further vias 3322 connect source / drain region 3214B and source / drain region 3244A to bit line input 2324, and source / drain region 3214C ​​and source / drain region 3254A to bit line input 2326. Vdd is connected to source / drain region 3214A and source / drain region 3214D through additional vias 3322.

[0163] In some embodiments, source / drain region 3214B in lower transistor region 3350 is merged with source / drain region 3264B in upper transistor region 3300 via source / drain merge 3290A. Additionally, source / drain region 3254A can be merged with source / drain region 3274C via source / drain merge 3290B. The merging of these source / drain regions provides the necessary connections between the NMOS transistor and the PMOS transistor.

[0164] The embodiment of the memory device 2300 described herein provides a memory device that can use current layout technology to provide strong signal connectivity without significant area loss. The wiring in the memory device 2300 utilizes the bit line wiring through the top metal layer and the back metal layer to avoid metal wiring congestion in the device. The memory device 2300 also avoids the typical complexity involved in the manufacture of unipolar devices using various wiring paths and connection paths described herein. The various connection paths described herein can also reduce the resistance in the memory device 2300 and therefore improve the read / write speed and performance of the memory device.

[0165] Vertical transistor cell

[0166] A recent advance in transistor design is the implementation of vertical transistors, where the cell has vertical delivery through vertically displaced source / drain regions and a gate positioned vertically between the source / drain regions. Current vertical transistor designs typically include wider front side (e.g., top side) power rails at the boundaries of the cell for power delivery. However, these wider power rails cause the standard cell height to increase and become larger. Larger standard cell heights reduce the area efficiency of vertical transistors, while also reducing the available connectivity and performance of the transistor.

[0167] The present disclosure contemplates various embodiments that utilize backside power wiring in a vertical transistor design to reduce scale, provide better connectivity, and provide better performance of transistors. Certain embodiments disclosed herein have four main elements: 1) a pair of vertical transistors in an integrated circuit cell; 2) a topside metal layer above the transistor region of the vertical transistor with signal wiring, 3) a backside metal layer below the transistor region with power wiring, and 4) a metal contact layer between the backside metal layer and the source / drain region of the transistor. In certain embodiments, the transistors are complementary transistors. In some embodiments, vias couple the power wiring in the backside metal layer to the metal contact layer. In some embodiments, a second pair of vertical transistors may be included in the cell. Additional embodiments of gate vias, fins, contact vias, and various other connections and wiring are also contemplated in various embodiments.

[0168] In various embodiments, various contacts or vias are used to make control signal and power signal connections to implement logic associated with a specific integrated circuit device having multiple vertical transistors for the cell configuration described herein. For example, examples of inverter devices, NAND devices, and MUX devices that can be implemented based on vertical transistor cell configurations are described below. Embodiments of various possible connections for control signals and voltage signals to vertical transistors within the cell configuration are also described. Those skilled in the art will appreciate that combinations of these various possible connections can be implemented to generate many different desired circuits based on the vertical transistor structures within the cell configurations disclosed herein.

[0169] In short, the inventors have recognized that implementing backside wiring for power connections in combination with vertical transistors provides various opportunities for the construction of specific transistor designs with reduced scale. Additionally, various techniques are implemented to provide specific routing of control signals and power wiring within a cell configuration with vertical transistors as described herein. In implementing the various disclosed techniques, vertical transistor cell configurations that provide improved performance with small scale factors are contemplated.

[0170] Fig.36 Depicted is a perspective representation of a contemplated vertical transistor device in accordance with some embodiments. Fig.37 A perspective representation of another contemplated vertical transistor device according to some embodiments is depicted. It should be noted that Fig.36 The device 3400 and Fig.37 The device 3500 shown is a general representation of a vertical transistor-based device structure without depicting the various connections that can be made to the structure. Figure 38 to Figure 54 Exemplary embodiments of connection structures are further disclosed.

[0171] exist Fig.36 In the illustrated embodiment, device 3400 includes two vertical transistors 3410, 3420. In some embodiments, transistors 3410, 3420 are complementary type transistors. For example, transistor 3410 is a PMOS transistor and transistor 3420 is an NMOS transistor. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. Similarly, transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. In some embodiments, gate 3414 and gate 3424 are fin gates. In various embodiments, gate 3414 includes a gate spacer 3415, and gate 3424 includes a gate spacer 3425. In order to simplify the drawings, gate spacers 3415, 3425 are not marked in the remaining drawings.

[0172] like Fig.36 As shown, the lower source / drain region, the gate, and the upper source / drain region are stacked in the vertical dimension of the transistor. Further as depicted, transistor 3410 and transistor 3420 are parallel and have a certain spacing (e.g., distance) between them in the horizontal direction (e.g., horizontal dimension) of device 3400.

[0173] In some embodiments, transistor 3410 includes an upper contact 3418 coupled to upper source / drain region 3416, and transistor 3420 includes an upper contact 3428 coupled to upper source / drain region 3426. Contacts 3418 and 3428 can be, for example, metal contacts for contacting various resources in a first metal layer located above transistor 3410 and transistor 3420. For example, Fig.36 As shown, contact 3418 can be routed to a resource via route 3430 (e.g., a wiring shown by a dashed line). Route 3430 can be, for example, a metal layer routing path in a first metal layer above transistor 3410 and transistor 3420. It should be noted that the dashed line depiction of route 3430 is provided as an example of one resource (e.g., a wiring) in a metal layer, and a metal layer may include multiple resources (e.g., multiple wirings). Additionally, only the first metal layer above transistor 3410 and transistor 3420 is depicted, and multiple additional metal wirings may exist above route 3430.

[0174] In various embodiments, transistor 3410 includes a lower contact 3419 coupled to lower source / drain region 3412, and transistor 3420 includes a lower contact 3429 coupled to lower source / drain region 3422. Contacts 3419, 3429 can be, for example, metal contacts. Contacts 3419, 3429 can be used to route to a backside power routing layer (e.g., backside power routing 3440A or backside power routing 3440B, such as Fig.36 ) or routed to various other resources within device 3400 as shown and described herein.

[0175] In some embodiments, device 3400 includes a backside power layer. Fig.36 In the illustrated embodiment, the backside power layer includes backside power routing 3440A and backside power routing 3440B. Routing 3440A and routing 3440B can, for example, provide routing to / from power (eg, Vdd) and power ground (eg, Vss) resources of device 3400.

[0176] In various embodiments, gate 3414 and gate 3424 are interconnected by gate bridge 3450. Gate bridge 3450 can be formed, for example, by extending the gate material of gate 3414 and gate 3424 to couple the gates together. In some embodiments, gate bridge 3450 can be formed by extending the gate material of either gate 3414 or gate 3424 unidirectionally to the other gate. Gate bridge 3450 can also include an extension of material for gate spacers. In various embodiments of CMOS devices, gate bridge 3450 incorporates gate 3414 and gate 3424 for implementing transistor 3410 and transistor 3420, some examples of which are described herein. Various embodiments in which gate 3414 and / or gate 3424 extend in other directions can also be envisioned. For example, the gate can include an extension extending toward the outer boundary of device 3400 (e.g., toward the outer boundary of the cell structure in the opposite direction of gate bridge 3450).

[0177] exist Fig.37 In the illustrated embodiment, device 3500 does not have a gate bridge connecting gate 3414 in transistor 3410 and gate 3424 in transistor 3420. Various techniques for connecting transistor 3410 and transistor 3420 without using a gate bridge can be envisioned. For example, in one envisioned embodiment, contact 3418 and contact 3428 can be connected by strip 3510. Strip 3510 can be, for example, a metal strip. In some embodiments, contact 3418, contact 3428, and strip 3510 can be formed as a single contact (e.g., a single strip connecting upper source / drain region 3416 and upper source / drain region 3426). Various embodiments can also be envisioned in which strip 3510 extends from one of contacts 3418, 3428 in another direction. For example, strip 3510 can extend perpendicularly to the depicted embodiment toward another vertical transistor or resource in device 3500.

[0178] In another contemplated embodiment, contact 3419 and contact 3429 may be connected by strip 3520. Strip 3520 may also be a metal strip. In some embodiments, strip 3520 is formed together with contacts 3419 and 3429 as a single contact. For example, strip 3520, contact 3419, and contact 3429 may be part of a single metal contact plate formed in a contact layer. Various embodiments are also contemplated in which contact 3419 and / or contact 3429 extend outward from the bottom of transistors 3410, 3420. For example, the contact may have a portion extending toward the outer boundary of device 3500 (e.g., toward the outer boundary of the cell structure).

[0179] It should be understood that although Fig.36 The device 3400 and Fig.37The illustrated device 3500 is depicted separately as having various connection structures, but embodiments in which structures from device 3400 are combined with structures from device 3500 in a cell design are contemplated. For example, a device including gate bridge 3450 and one or both of strips 3510 and strips 3520 is contemplated. Various exemplary device cell configurations are now described based on device 3400 and / or device 3500 as examples. It should be noted that the various device cell configurations are provided as examples, and various additional device cell configurations may be implemented based on the description herein.

[0180] Figures 38 to 42 Depicted is a representation of an inverter unit configuration according to some embodiments. Fig.38 Depicted is a perspective representation of an inverter unit configuration according to some embodiments. Fig.39 Depicted is a top plan view representation of an inverter unit configuration according to some embodiments. Fig.40 Depicted is a back plan view representation of an inverter unit configuration according to some embodiments. Fig.41 Depicted is an inverter cell structure according to some embodiments. Fig.39 A cross-section representation along line 41 - 41 (eg, along a gate bridge) is shown. Fig.42 Depicted is a reverser unit configuration according to some embodiments. Fig.39 A cross-section representation is shown along line 42 - 42 (eg, perpendicular to the gate fin of transistor 3410 ).

[0181] The inverter unit device 3600 can be obtained from the structure of the device 3400, such as Fig.36 As shown. Figures 38 to 42 In the illustrated embodiment, device 3600 includes a vertical transistor 3410 and a vertical transistor 3420. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, an upper source / drain region 3416, an upper contact 3418, and a lower contact 3419. Transistor 3420 includes a lower source / drain region 3422, a gate 3424, an upper source / drain region 3426, an upper contact 3428, and a lower contact 3429. In the illustrated embodiment of device 3600, transistor 3410 is a PMOS transistor, and transistor 3420 is an NMOS transistor.

[0182] In certain embodiments, device 3600 includes backside vias 3610A, 3610B. Backside via 3610A is coupled to lower source / drain region 3412 through lower contact 3419. Backside via 3610A couples lower source / drain region 3412 to backside power wiring 3440A. For device 3600, backside power wiring 3440A provides power (e.g., Vdd) to lower source / drain region 3412 and transistor 3410. Backside via 3610B is coupled to lower source / drain region 3422 through lower contact 3429. Backside via 3610B couples lower source / drain region 3422 to backside power wiring 3440B. For device 3600 , backside power routing 3440B provides ground power (eg, Vss) to lower source / drain regions 3422 and transistor 3420 .

[0183] In various embodiments, device 3600 includes topside vias 3620A, 3620B. Topside via 3620A can be coupled to upper source / drain region 3416 via upper contact 3418, and topside via 3620B can be coupled to upper source / drain region 3426 via upper contact 3428. Topside vias 3620A, 3620B can provide connections to signal routing resources (e.g., routes 3430A-E) in the first metal layer above transistor 3410 and transistor 3420. For example, in the illustrated embodiment, topside via 3620A is coupled to route 3430B, and topside via 3620B is coupled to route 3430D. Routes 3430B and 3430D can provide routes for output signals from transistor 3410 and transistor 3420, respectively.

[0184] In some embodiments, the routing of the input signal to transistor 3410 and transistor 3420 is provided by routing 3430C. Fig.38 and Fig.39 As shown, route 3430C is coupled to gate via 3630, which is coupled to gate bridge 3450. Thus, gate via 3630 provides a connection between route 3430C (e.g., input signal route) and both gate 3414 in transistor 3410 and gate 3424 in transistor 3420. Through connections to the input signal route, output signal route, and power / ground routes, transistor 3410 and transistor 3420 are connected to form inverter cell device 3600.

[0185] It should be noted that although Fig.38 and Fig.39Five routes 3430A-E are depicted in the first metal layer above transistor 3410 and transistor 3420, but the first metal layer may include additional routes. In addition, additional metal layers may be positioned above the first metal layer and provide various connections to either the first metal layer or device 3600. For example, in one embodiment, the metal layer above the first metal layer may include a strip (or other connector) coupling route 3430B and route 3430D so that the outputs of transistor 3410 and transistor 3420 are merged together into a single output. Additionally, while two backside power routings (e.g., routing 3440A and routing 3440B) are shown, the backside power layer may include additional routings (e.g., routings for other power and signal resources).

[0186] Fig.39 and Fig.40 The top and back plan views of device 3600 shown also depict gate fins that may be present in the gate of the transistor. For example, gate fin 3415 is the gate fin of gate 3414, and gate fin 3425 is the gate fin of gate 3424. Fig.41 The cross-sectional representation of device 3600 in FIG. 1 also shows gate fin 3415 and gate fin 3425, and in FIG. Fig.42 The gate fin 3415 is shown in the cross-sectional representation of transistor 3410 in FIG. Fig.42 The cross section shows a cross section perpendicular to the gate fin of transistor 3410, which is Fig.38 and Fig.39 Directions for route 3430B are shown.

[0187] Figure 43 to Figure 47 Depicted is a representation of a NAND cell construction according to some embodiments. Fig.43 Depicted is a perspective representation of a NAND cell construction according to some embodiments. Fig.44 Depicted is a top side plan view representation of a NAND cell construction according to some embodiments. Fig.45 Depicted is a backside plan view representation of a NAND cell construction according to some embodiments. Fig.46 Depicted is a NAND cell structure according to some embodiments. Fig.44 A cross-section representation is shown along line 46 - 46 (eg, along gate bridge 3450 ′). Fig.47 Depicted is a NAND cell structure according to some embodiments. Fig.44 A cross-sectional representation of line 47 - 47 (eg, perpendicular to the gate fins of transistor 3410 and transistor 3410 ′) is shown.

[0188] NAND cell device 4100 can be obtained from the structure of device 3400, such as Fig.36As shown. Figure 43 to Figure 47 In the illustrated embodiment, device 4100 includes vertical transistor 3410, vertical transistor 3420, vertical transistor 3410' and vertical transistor 3420'. Transistor 3410 includes lower source / drain region 3412, gate 3414 and upper source / drain region 3416. Transistor 3420 includes lower source / drain region 3422, gate 3424 and upper source / drain region 3426. Transistor 3410' includes lower source / drain region 3412', gate 3414' and upper source / drain region 3416'. Transistor 3420' includes lower source / drain region 3422', gate 3424' and upper source / drain region 3426'. In the illustrated implementation of device 4100, transistor 3410 and transistor 3410' are PMOS transistors, while transistor 3420 and transistor 3420' are NMOS transistors.

[0189] In some embodiments, the routing of the input signal to transistor 3410, transistor 3410', transistor 3420, and transistor 3420' is provided by routing 3430C. Fig.43 and Fig.44 As shown, route 3430C is coupled to gate via 3630A and gate via 3630B, with gate via 3630A coupled to gate bridge 3450 and gate via 3630B coupled to gate bridge 3450'. Thus, gate via 3630A provides a connection between route 3430C (e.g., input signal route) and both gate 3414 in transistor 3410 and gate 3424 in transistor 3420. Gate via 3630B provides a connection between route 3430C (e.g., input signal route) and both gate 3414' in transistor 3410 and gate 3424' in transistor 3420'.

[0190] In certain embodiments, the upper source / drain region 3416 of transistor 3410 and the upper source / drain region 3416' of transistor 3410' are connected by contact 3418. Similarly, the upper source / drain region 3426 of transistor 3420 and the upper source / drain region 3426 of transistor 3420 are connected by contact 3428. In various embodiments, device 4100 includes a topside via 3620 connected to contact 3418. Topside via 3620 can provide a connection to route 3430B in the first metal layer above the transistor region of device 4100. In the illustrated embodiment, route 3430B provides a route for output signals from transistor 3410 and transistor 3410'.

[0191] In the illustrated embodiment, only transistor 3410, transistor 3410', and transistor 3420 are connected to the backside layer. Fig.42 and Fig.45 As shown, transistor 3410 is connected to backside power wiring 3440A through contact 3419 and backside via 3610A, transistor 3410′ is connected to backside power wiring 3440A through contact 3419′ and backside via 3610A′, and transistor 3420 is connected to backside power wiring 3440B through contact 3429 and backside via 3610B. In various embodiments of device 4100, backside power wiring 3440A provides power (e.g., Vdd) to lower source / drain region 3412 and transistor 3410 and lower source / drain region 3412′ and transistor 3410′, while backside power wiring 3440B provides ground power (e.g., Vss) to lower source / drain region 3422 and transistor 3420.

[0192] In some embodiments, the lower source / drain region 3422' in transistor 3420' is connected to a contact 3429' that is not connected to the backside power wiring layer. Fig.43 , Fig.45 and Fig.46 As shown, contact 3429' extends away from the lower source drain region 3422' and extends toward the boundary of the cell. Contact 3429' is then coupled to route 3430E through contact via 4110. Route 3430E is a route in the first metal layer above the transistor region. Contact via 4110 is a via that belongs to the cell structure of device 4100 and is not shared with any adjacent cells along the cell boundary. In some embodiments, route 3430E is a signal route in the first metal layer for outputting signals from transistor 3420'. Therefore, the signal in the NMOS transistor (e.g., transistor 3420 and transistor 3420') is routed through these transistors from the lower source / drain region 3422 (connected to the ground through the back side power wiring 3440B) and is led out to route 3430E through contact via 4110.

[0193] In the illustrated embodiment, route 3430E provides a route for output signals from transistor 3420 and transistor 3420'. The output signal routed through route 3430E can be combined with the output signal from route 3430B. For example, the metal layer above the first metal layer can include a stripe (or other connector) that couples route 3430B and route 3430E so that the outputs of the transistors are combined together into a single output.

[0194] The various wiring and connections in device 4100 form a NAND cell device. Fig.44 and Fig.45The gate fins 3415, 3415', 3425, 3425' in the gates 3414, 3414', 3424, 3424' are shown respectively. The gate fins 3415' and 3425' are also shown in FIG. Fig.46 4100, and the gate fin 3415 and the gate fin 3415' are shown in the cross-sectional representation of the device 4100 in FIG. Fig.47 A cross-sectional representation of the device 4100 is shown in FIG. 4 . Note that Fig.47 The cross section of FIG. 1 shows a cross section perpendicular to the gate fins of transistor 3410 and transistor 3410′, which is Fig.44 Directions for route 3430B are shown.

[0195] Figures 48 to 52 Depicted is a representation of a MUX (multiplexer) cell configuration according to some embodiments. Fig.48 Depicted is a perspective representation of a MUX unit configuration according to some embodiments. Fig.49 Depicted is a top plan view representation of a MUX cell configuration according to some embodiments. Fig.50 Depicted is a backside plan view representation of a MUX cell configuration according to some embodiments. Fig.51 Depicted is a MUX unit configuration according to some embodiments. Fig.49 A cross-section representation of line 51 - 51 (eg, along gate fin 3415 ′ and gate fin 3425 ″) is shown. Fig.52 Depicted is a MUX unit configuration according to some embodiments. Fig.49 A cross-sectional representation of line 52 - 52 (eg, perpendicular to the gate fins of transistor 3410 and transistor 3410 ″) is shown.

[0196] The MUX unit device 4600 can be derived from the structure of the device 3500, such as Fig.37 As shown. Figures 48 to 52In the illustrated embodiment, device 4600 includes a vertical transistor 3410, a vertical transistor 3420, a vertical transistor 3410", and a vertical transistor 3420". As in device 3500, a gate bridge exists between the gates of the transistors in device 4600 so that there is no common gate between complementary transistors. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. Transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. Transistor 3410" includes a lower source / drain region 3412", a gate 3414", and an upper source / drain region 3416". Transistor 3420" includes a lower source / drain region 3422", a gate 3424", and an upper source / drain region 3426". In the illustrated embodiment of device 4600, transistor 3410 and transistor 3410" are PMOS transistors, and transistor 3420 and transistor 3420" are NMOS transistors.

[0197] Since the MUX cell device 4600 is a transmission device, neither transistor 3410 nor transistor 3410″ and neither transistor 3420 nor transistor 3420″ is connected to any power supply in the MUX cell structure. In various embodiments of the MUX cell device 4600, the lower source / drain regions of the transistors are connected together (e.g., merged together). For example, in the illustrated embodiment, the contact plate 4620 is connected to the lower source / drain region 3412 in transistor 3410, the lower source / drain region 3412″ in transistor 3410″, the lower source / drain region 3422 in transistor 3420, and the lower source / drain region 3422″ in transistor 3420″.

[0198] In some embodiments, contact via 4630 is coupled to contact plate 4620. Contact via 4630 can be connected to contact plate 4620 at or near the center of the contact plate. Contact via 4630 is then connected to route 3430C in the first metal layer above the transistor region. In various embodiments, route 3430C provides output wiring for MUX cell device 4600. Therefore, contact via 4630 can be referred to as an output pin of MUX cell device 4600.

[0199] In various embodiments, gates 3414, 3414", 3424, 3424" extend toward the boundary of the cell to provide a surface for direct vertical connection to the gate from a route in the first metal layer above. For example, Figures 48 to 52As shown, gate 3414 includes gate extension 4640A that extends toward the boundary of the cell (e.g., extends horizontally toward the boundary of the cell). Similarly, gate 3414" includes gate extension 4640B, gate 3424 includes gate extension 4640C, and gate 3424" includes gate extension 4640D. Gate extensions 4640A-D are then connected to the routing in the first metal layer above through gate vias 3630A-D, respectively. For example, as shown in FIG. Fig.48 and Fig.49 As shown, gate via 3630A connects gate extension 4640A to route 3430A, gate via 3630B connects gate extension 4640B to route 3430A, gate via 3630C connects gate extension 4640C to route 3430E, and gate via 3630D connects gate extension 4640D to route 3430E. One or both of route 3430A and route 3430E are located at the boundary of the cell and are not shared with adjacent cells. Route 3430A and route 3430E can provide input routes to device 4600.

[0200] In certain embodiments, upper source / drain region 3416 in transistor 3410 is connected to upper source / drain region 3426 in transistor 3420 via contact 4610A. This connection merges upper source / drain region 3416 with upper source / drain region 3426. Similarly, upper source / drain region 3416" in transistor 3410" is connected to upper source / drain region 3426" in transistor 3420" via contact 4610B. By merging these upper source / drain regions and a common connection between the lower source / drain regions (and a single output via contact via 4630), device 4600 can be used as a MUX (multiplexer) with signals input through gate vias 3630A-D and output through contact via 4630.

[0201] Fig.49 and Fig.50 The gate fins 3415, 3415", 3425, 3425" in the gates 3414, 3414", 3424, 3424" are shown respectively. The gate fins 3415 and 3425 are also shown in FIG. Fig.51 4600, and the gate fin 3415 and the gate fin 3415' are shown in Fig.52 A cross-sectional representation of the device 4600 is shown in FIG. 4 . Note that Fig.52 The cross section of FIG. 1 shows a cross section perpendicular to the gate fins of transistor 3410 and transistor 3410′, which is Fig.49 Directions for route 3430B are shown.

[0202] Fig.53 and Fig.54 Depicted is a representation of a unit cell device having dielectric walls according to some embodiments. Fig.53 A perspective representation of a device 5100 is depicted, according to some embodiments. Fig.54 Depicted is a device 5100 according to some embodiments. Fig.53 A cross-section representation is shown along line 54 - 54 (eg, along gate bridge 3450 ′).

[0203] Device 5100 can be obtained from the structure of device 3400, such as Fig.36 In some embodiments, the device 5100 may be similar to Figure 43 to Figure 47 The inverter unit device 4100 is shown. Fig.53 and Fig.54 In the illustrated embodiment, device 5100 includes a vertical transistor 3410 and a vertical transistor 3420. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. Transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. In some embodiments, transistor 3410 is a PMOS transistor and transistor 3420 is an NMOS transistor.

[0204] In various embodiments, such as Fig.53 and Fig.54 As shown, wall 5100A can be positioned on a first side of the cell (e.g., on one side of transistor 3410), and wall 5100B can be positioned on a second side of the cell (e.g., on the side of transistor 3420 opposite transistor 3410). In some embodiments, wall 5100A and wall 5100B are dielectric walls. Placing dielectric walls on one or both sides of device 5100 can reduce the space required between device 5100 and another adjacent cell. Therefore, wall 5100A and wall 5100B can be implemented when it is necessary to reduce the scale of the device.

[0205] Example Computer System

[0206] Next go to Fig.55, which shows a block diagram of one embodiment of a system 5300 that can incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, the system 5300 includes at least one instance of a system on a chip (SoC) 5306, which can include multiple types of processing units (such as a central processing unit (CPU), a graphics processing unit (GPU), or other), a communication structure, and interfaces to memory and input / output devices. In some embodiments, one or more processors in the SoC 5306 include multiple execution lanes and instruction issue queues. In various embodiments, the SoC 5306 is coupled to external memory 5302, peripherals 5304, and a power supply 5308.

[0207] A power supply 5308 is also provided, which supplies a supply voltage to the SoC 5306 and one or more supply voltages to the memory 5302 and / or peripherals 5304. In various embodiments, the power supply 5308 represents a battery (e.g., a rechargeable battery in a smartphone, laptop or tablet, or other device). In some embodiments, more than one instance of the SoC 5306 is included (and more than one external memory 5302 is also included).

[0208] The memory 5302 is any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, etc., and / or low power versions of SDRAM, such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled to the circuit board to form a memory module, such as a single inline memory module (SIMM), a dual inline memory module (DIMM), etc. Alternatively, the device can be mounted together with the SoC or integrated circuit in a chip stacking configuration, a package stacking configuration, or a multi-chip module configuration.

[0209] Peripheral devices 5304 include any desired circuitry, depending on the type of system 5300. For example, in one embodiment, peripheral devices 5304 include devices for various types of wireless communications, such as Wi-Fi, Bluetooth, cellular, global positioning systems, etc. In some embodiments, peripheral devices 5304 also include additional memory, including RAM storage, solid-state storage, or disk storage. Peripheral devices 5304 include user interface devices such as display screens, including touch screens or multi-touch screens, keyboards or other input devices, microphones, speakers, etc.

[0210] As illustrated, system 5300 is shown to have applications in a wide range of fields. For example, system 5300 can be used as a part of a chip, circuit, component, etc. of a desktop computer 5310, a laptop computer 5320, a tablet computer 5330, a cellular or mobile phone 5340, or a TV 5350 (or a set-top box coupled to a TV). Smart watches and health monitoring devices 5360 are also illustrated. In some embodiments, smart watches may include various general computing related functions. For example, smart watches may provide access to email, mobile phone services, user calendars, etc. In various embodiments, health monitoring devices may be dedicated medical devices or otherwise include dedicated health-related functionality. For example, health monitoring devices may monitor a user's vital signs, track the proximity of a user to other users for the purpose of epidemiological social distance, contact tracking, provide communications to emergency services in the event of a health crisis, etc. In various embodiments, the above-mentioned smart watches may include or may not include some or any health monitoring related functions. Other wearable devices are also contemplated, such as devices worn around the neck, devices implantable in the human body, glasses designed to provide augmented and / or virtual reality experiences, and the like.

[0211] The system 5300 may also be used as part of a cloud-based service 5370. For example, the previously mentioned devices and / or other devices may access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Further, the system 5300 may be used in one or more devices in the home 5380 other than those previously mentioned. For example, a household appliance may monitor and detect noteworthy situations. For example, various devices in a home (e.g., a refrigerator, a cooling system, etc.) may monitor the status of the device, and an alert should be provided to the homeowner (or, for example, a maintenance agency) if a particular event is detected. Alternatively, a thermostat may monitor the temperature in the home, and may automatically adjust the heating / cooling system based on a history of responses by the homeowner to various situations. Fig.55 Also illustrated in the 5300 are applications of various modes of transportation 5390. For example, the system 5300 may be used for control and / or entertainment systems for airplanes, trains, buses, taxis, private cars, watercraft ranging from private boats to cruise ships, scooters (for rental or private use), and the like. In various cases, the system 5300 may be used to provide automated guidance (e.g., self-driving vehicles), general system control, and the like. Any of these and many other implementations are possible and contemplated. Note that Fig.55 The devices and applications shown are exemplary only and are not intended to be limiting. Other devices are possible and contemplated.

[0212] ***

[0213] This disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different specific implementations or examples of the disclosed concepts. References to "an embodiment," "one embodiment," "a particular embodiment," etc. are not necessarily to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the present disclosure.

[0214] The present disclosure may discuss potential advantages that may be generated by the disclosed embodiments. Not all of these implementations will necessarily exhibit any or all of the potential advantages. Whether a particular implementation achieves an advantage depends on many factors, some of which are outside the scope of the present disclosure. In fact, there are many reasons why an implementation that falls within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular implementation may include other circuits outside the scope of the present disclosure that, in combination with one of the disclosed embodiments, negate or reduce one or more of the disclosed advantages. In addition, suboptimal design execution of a particular implementation (e.g., a specific implementation technique or tool) may also negate or reduce the disclosed advantages. Even assuming a specific implementation of the technology, the realization of the advantages may still depend on other factors, such as the environmental conditions in which the specific implementation is deployed. For example, the input provided to a particular implementation may prevent one or more problems solved in the present disclosure from occurring in a particular occasion, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors external to the present disclosure, it is hereby clarified that any potential advantages described herein should not be construed as claim limitations that must be met in order to prove infringement. Instead, the identification of such potential advantages is intended to illustrate the types of improvements available to designers who benefit from the present disclosure. Permanently describing such advantages (eg, stating that a particular advantage "may occur") is not intended to convey a doubt as to whether such advantage can actually be achieved, but rather to recognize that achievement of such advantage typically depends on technical realities of additional factors.

[0215] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on the present disclosure, even if only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive, without any contrary statement in the present disclosure. Therefore, the present application is intended to allow claims covering the disclosed embodiments, as well as such alternatives, modifications and equivalents, which will be apparent to those skilled in the art who are aware of the beneficial effects of the present disclosure.

[0216] For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be made during the prosecution of this application (or an application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features of dependent claims may be combined, where appropriate, with features of other dependent claims, including claims that are dependent on other independent claims. Similarly, features from corresponding independent claims may be combined, where appropriate.

[0217] Thus, while the appended dependent claims may be drafted such that each dependent claim is dependent upon a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with the present disclosure is contemplated and may be claimed in this or another application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0218] It is also contemplated that claims drafted in one format or legal type (eg, apparatus) are intended to support corresponding claims in another format or legal type (eg, method), where appropriate.

[0219] ***

[0220] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0221] Unless the context clearly dictates otherwise, reference to an item in the singular (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, reference to "an item" in a claim does not exclude additional instances of that item without the accompanying context. A "plurality" of an item refers to a collection of two or more of the items.

[0222] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0223] The terms "including" and "comprising" and forms thereof are open ended and mean "including, but not limited to."

[0224] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0225] The expressions "w, x, y, or z, or any combination thereof" or "... at least one of w, x, y, and z" are intended to cover all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "... at least one of w, x, y, and z" thus refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in the list of elements. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0226] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels used for a feature (e.g., "a first circuit," "a second circuit," "a particular circuit," "a given circuit," etc.) refer to different instances of the feature. Additionally, unless otherwise stated, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0227] The phrase "based on" is used to describe one or more factors that influence a determination. The term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based only on specified factors or on specified factors and other unspecified factors. Consider the phrase "A is determined based on B." The phrase specifies that B is a factor used to determine A or that B influences the determination of A. The phrase does not exclude that the determination of A may also be based on some other factor such as C. The phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0228] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. The phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with the specified factors or independently of the specified factors. That is, the effect may be responsive to these factors alone, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "A is performed in response to B." The phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. The phrase does not exclude that the execution of A may also be responsive to certain other factors, such as C. The phrase also does not exclude that the execution of A may be performed jointly in response to B and C. The phrase is also intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to."

[0229] ***

[0230] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. The expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, the expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be considered to be "configured to" perform a task even if the structure is not currently being operated. Thus, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a system with a processor unit, and a memory storing executable program instructions, etc. This phrase is not used herein to refer to an intangible thing.

[0231] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations, even if not specifically stated.

[0232] The term "configured to" is not intended to mean "capable of being configured to". For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA may be "configurable to" perform that function. After being appropriately programmed, the FPGA may then be considered "configured to" perform a particular function.

[0233] For purposes of a U.S. patent application based on the present disclosure, stating in a claim that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution of a U.S. patent application based on the present disclosure, it would use the “means for [performing the function]” construct to phrase the claim element.

[0234] Different "circuits" may be described in the present disclosure. These circuits or "circuits" constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits or circuits.

[0235] Thus, the disclosed circuits / units / components and other elements illustrated in the drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the functionality of that circuit. For example, a particular "decode unit" may be described as performing the function of "processing an opcode for an instruction and routing the instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function. For one skilled in the computer arts, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0236] In various embodiments, as discussed in the preceding paragraphs, circuits, units, and other elements defined by the functions or operations they are configured to implement, with respect to the arrangement of each other and such circuits / units / components and the manner in which they interact, form a microarchitecture definition of hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, the microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall into the broader structure described by the microarchitecture definition. That is, a technician with a microarchitecture definition provided in accordance with the present disclosure can implement the structure by encoding a description of the circuit / unit / component in a hardware description language (HDL) such as Verilog or VHDL without undue experimentation and with the application of ordinary technicians. HDL descriptions are often expressed in a manner that can be rendered functional. However, for those skilled in the art, the HDL description is a way to convert the structure of a circuit, unit, or component into the next level of specific implementation details. Such HDL descriptions may take the form of behavioral code (which is generally non-synthesizable), register transfer language (RTL) code (which is generally synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may be sequentially synthesized for a library of cells designed for a given integrated circuit manufacturing technology, and may be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuits or portions thereof may also be custom designed in a schematic editor and captured into an integrated circuit design along with the synthesized circuits. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented in an FPGA. This decoupling between the design of a set of circuits and the subsequent low-level implementation of those circuits often leads to a situation where a circuit or logic designer never specifies a particular set of structures for the low-level implementation beyond a description of what the circuits are configured to do, because that process is performed at different stages of the circuit implementation process.

[0237] The fact that many different low-level combinations of circuit elements can be used to achieve the same specification of a circuit results in a large number of identical structures for that circuit. As noted, these low-level circuit implementations can vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the cell libraries provided for a particular project, etc. In many cases, the selection made by different design tools or methodologies to produce these different implementations can be arbitrary.

[0238] Furthermore, for a given embodiment, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Thus, the shear volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single embodiment, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of the circuit using functional shorthand commonly used in the industry.

Claims

1. A device, comprising: a first transistor formed in a transistor region of an integrated circuit cell structure, the first transistor having a first active region, a first gate, and a first source / drain region in the transistor region; a second transistor formed in the transistor region, the second transistor having a second active region, a second gate, and second source / drain regions in the transistor region, wherein at least a portion of the second active region is positioned below the first active region in a vertical dimension perpendicular to the transistor region; a first metal layer located above the transistor region in the vertical dimension, wherein the first metal layer includes a first signal wiring connected to the first transistor; and A second metal layer is located below the transistor region in the vertical dimension, wherein the second metal layer includes a second signal wiring connected to the second transistor, and wherein the second metal layer includes a power wiring connected to the second transistor. 2 . The device according to claim 1 , wherein the first signal wiring in the first metal layer is connected to a signal input of the first gate in the first transistor. 3 . The device according to claim 1 , wherein the second signal wiring in the second metal layer is connected to at least one second source / drain region in the second transistor. 4 . The device of claim 1 , wherein the power wiring in the second metal layer is connected to at least one second source / drain region in the second transistor. 5 . The device of claim 1 , wherein a portion of the first active region forming the first gate contacts a portion of the second active region forming the second gate. 6 . The device according to claim 5 , wherein the first signal wiring in the first metal layer is connected to a signal input of the first gate in the first transistor. 7 . The device of claim 1 , wherein a portion of the first active region forming the first gate is separated from a portion of the second active region forming the second gate.

8. The device according to claim 7, wherein the first signal wiring in the first metal layer is connected to a signal input of the first gate in the first transistor, and wherein the second signal wiring in the second metal layer is connected to a signal input of the second gate in the second transistor. 9 . The device of claim 1 , wherein the first metal layer includes a power supply wiring connected to the first transistor.

10. The device according to claim 1, further comprising: a via connected to the power wiring or the signal wiring in the second metal layer and positioned outside the first active area and the second active area in a horizontal dimension perpendicular to the vertical dimension, wherein the via connects the power wiring or the signal wiring in the second metal layer to the power wiring or the signal wiring in the first metal layer; and A contact via coupled between the power wiring or the signal wiring in the first metal layer and at least one first source / drain region in the first transistor, the contact via connecting the power wiring or the signal wiring in the second metal layer to the first transistor.

11. The device of claim 1, wherein the first transistor and the second transistor are complementary transistor types.

12. The device according to claim 1, further comprising: a via connected to the power wiring or the signal wiring in the second metal layer and positioned outside the second active area in a horizontal dimension perpendicular to the vertical dimension; and A source / drain contact connected to at least one second source / drain region, wherein the source / drain contact is positioned above the second active region in the vertical dimension, and wherein at least a portion of the source / drain contact extends beyond the second active region in the horizontal dimension, such that the source / drain contact is connected to the via and the via connects the power wiring or the signal wiring in the second metal layer to the at least one second source / drain region.

13. A device, comprising: A plurality of integrated circuit unit structures, at least one integrated circuit unit structure comprising: a first transistor formed in a transistor region of the integrated circuit cell structure, the first transistor having a first active region, a first gate, and a first source / drain region in the transistor region; and a second transistor formed in the transistor region, the second transistor having a second active region, a second gate, and second source / drain regions in the transistor region, wherein at least a portion of the second active region is positioned below the first active region in a vertical dimension perpendicular to the transistor region; a first metal layer located above the transistor region in the vertical dimension; a second metal layer located below the transistor region in the vertical dimension; and A plurality of via posts are positioned on the periphery of the integrated circuit unit structure, the via posts extending through the transistor area in the vertical dimension between the first metal layer and the second metal layer, wherein at least some of the via posts are positioned on opposite sides of the first active area and the second active area, and wherein alternating via posts on one side alternately belong to at least one integrated circuit unit structure and an adjacent integrated circuit unit structure. 14 . The device according to claim 13 , wherein the first metal layer includes a first signal wiring connected to the first transistor, and wherein the second metal layer includes a second signal wiring connected to the second transistor. 15 . The device according to claim 13 , wherein the first metal layer includes a first power wiring connected to the first transistor, and wherein the second metal layer includes a second power wiring connected to the second transistor.

16. The device of claim 13, further comprising a contact between a signal input of the first gate and at least one of the via posts belonging to the at least one integrated circuit unit structure, the contact being formed in the transistor region.

17. The device of claim 13, further comprising a contact between a signal input of the second gate and at least one of the via posts belonging to the at least one integrated circuit unit structure, the contact being formed in the transistor region.

18. The device of claim 13, further comprising a contact between a drain region of the first transistor and at least one of the via pillars belonging to the at least one integrated circuit unit structure, the contact being formed in the transistor region.

19. The device of claim 13, further comprising a contact between a drain region of the second transistor and at least one of the via pillars belonging to the at least one integrated circuit unit structure, the contact being formed in the transistor region.

20. A device, comprising: a first transistor formed in a transistor region of an integrated circuit cell structure, the first transistor having a first active region, a first gate, one or more first source regions, and one or more first drain regions in the transistor region; a second transistor formed in the transistor region, the second transistor having a second active region, a second gate, one or more second source regions, and one or more second drain regions in the transistor region, wherein at least a portion of the second active region is positioned below the first active region in a vertical dimension perpendicular to the transistor region; a first metal layer located above the transistor region in the vertical dimension, wherein the first metal layer comprises: a first set of signal routing paths; and A first set of power wiring paths; a second metal layer located below the transistor region in the vertical dimension, wherein the second metal layer comprises: a second set of signal routing paths; and The second set of power supply wiring paths, at least one gate contact formed in the transistor region, wherein the at least one gate contact provides a connection between a signal input for one of the first gate or the second gate and a signal routing path from one of the first set of signal routing paths or the second set of signal routing paths; at least one source power contact formed in the transistor region, wherein the at least one source power contact provides a connection between a source region from one of the first source region or the second source region and a power routing path from one of the first set of power routing paths or the second set of power routing paths; and At least one drain power contact is formed in the transistor region, wherein the at least one drain power contact provides a connection between a drain region from one of the first drain region or the second drain region and a power wiring path from one of the first group of power wiring paths or the second group of power wiring paths.

21. A memory device, the memory device comprising: a first transistor region of an integrated circuit unit structure, the first transistor region having a first active region and a second active region, the first active region and the second active region being parallel and separated by a first distance; a second transistor region of the integrated circuit cell structure, the second transistor region having a third active region and a fourth active region, the third active region and the fourth active region being parallel and separated by a second distance, wherein at least a portion of the second transistor region is positioned below the first transistor region in a vertical dimension of the integrated circuit cell structure, and wherein the second transistor region is complementary to the first transistor region; A first inverter, the first inverter comprising: a first transistor having a first gate formed in the first active region, the first gate having first and second source / drain regions on opposite sides of the first gate; and a second transistor having a second gate formed in the third active region, the second gate having a third source / drain region and a fourth source / drain region on opposite sides of the second gate, wherein the third source / drain region merges with the first source / drain region and the fourth source / drain region merges with the second source / drain region, and wherein a portion of the second gate extends below the first transistor region; A second inverter, the second inverter comprising: a third transistor having a third gate formed in the second active region, the third gate having a fifth source / drain region and a sixth source / drain region on opposite sides of the third gate; and a fourth transistor having a fourth gate formed in the fourth active region, the fourth gate having a seventh source / drain region and an eighth source / drain region on opposite sides of the fourth gate, wherein the seventh source / drain region merges with the fifth source / drain region and the eighth source / drain region merges with the sixth source / drain region, and wherein a portion of the fourth gate extends below the first transistor region; The first inverter is connected to the seventh source / drain region by a first coupling between the portion of the second gate extending under the second active region and the seventh source / drain region and between the portion of the fourth gate extending under the first active region and the seventh source / drain region. A second coupling between four source / drain regions is cross-coupled to the second inverter, the first coupling and the second coupling being positioned below the second transistor region in the vertical dimension.

22. The memory device of claim 21 , further comprising a first pass gate coupled to a word line, the first pass gate being formed in the second active region and having the fifth source / drain region and a ninth source / drain region on opposite sides of the first pass gate, wherein the ninth source / drain region is coupled to a first bit line.

23. The memory device of claim 22, wherein the portion of the second gate extending under the first transistor region is positioned under the first pass gate.

24. The memory device of claim 22 , further comprising a second pass gate coupled to the word line, the second pass gate being formed in the first active region and having the second source / drain region and a tenth source / drain region on opposite sides of the second pass gate, wherein the tenth source / drain region is coupled to a second bit line, the second bit line being complementary to the first bit line.

25. The memory device of claim 24, wherein the portion of the fourth gate extending under the first transistor region is positioned under the second pass gate.

26. The memory device of claim 21, further comprising a metal layer located below the second transistor region in the vertical dimension, wherein the metal layer includes power wiring connected to the first inverter and the second inverter.

27. The memory device of claim 26, further comprising: a first backside via coupling the power wiring in the metal layer to the third source / drain region; and A second backside via couples the power wiring in the metal layer to the eighth source / drain region.

28. The memory device of claim 21, further comprising a metal layer located above the first transistor region in the vertical dimension, wherein the metal layer includes signal routing connected to the first inverter and the second inverter.

29. The memory device of claim 21, wherein the first inverter is cross-coupled to the second inverter such that an output of the first inverter is provided as an input to the second inverter and an output of the second inverter is provided as an input to the first inverter.

30. The memory device of claim 21, wherein the third active region is positioned below the first active region, and the fourth active region is positioned below the second active region.

31. The memory device of claim 21, wherein the first distance is substantially the same as the second distance.

32. The memory device of claim 21, wherein the portion of the second gate extending under the first transistor region extends to an inactive portion of the fourth active region.

33. The memory device of claim 21, wherein the portion of the fourth gate extending under the first transistor region extends to an inactive portion of the third active region.

34. The memory device of claim 33, wherein the inactive portion of the third active region is free of diffusion material.

35. The memory device of claim 21, further comprising: a first gate merging via coupling the first gate to the second gate; and A second gate merging via couples the third gate to the fourth gate.

36. A memory device, the memory device comprising: a first transistor region of an integrated circuit unit structure, the first transistor region having a first active region and a second active region, the first active region and the second active region being parallel and separated by a first distance; a second transistor region of the integrated circuit cell structure, the second transistor region having a third active region and a fourth active region, the third active region and the fourth active region being parallel and separated by a second distance, wherein at least a portion of the second transistor region is positioned below the first transistor region in a vertical dimension of the integrated circuit cell structure, and wherein the second transistor region is complementary to the first transistor region; a first pass gate formed in the second active region, the first pass gate coupled to a word line, wherein a source / drain region of the first pass gate is coupled to a first bit line; a second pass gate formed in the first active region, the second pass gate coupled to the word line, wherein a source / drain region of the second pass gate is coupled to a second bit line complementary to the first bit line; a first inverter formed by a first transistor in the first active region and a second transistor in the third active region, wherein inputs of the first transistor and the second transistor are combined, wherein outputs of the first transistor and the second transistor are combined, and wherein a portion of the second transistor extends below the first pass gate in the vertical dimension; a second inverter formed by a third transistor in the second active region and a fourth transistor in the fourth active region, wherein inputs of the third and fourth transistors are combined, wherein outputs of the third and fourth transistors are combined, and wherein a portion of the fourth transistor extends below the second pass gate in the vertical dimension; a first coupling between the portion of the second transistor extending under the second pass gate and a source / drain region of the fourth transistor, the first coupling being positioned under the second transistor region in the vertical dimension; and A second coupling between the portion of the fourth transistor extending under the first pass gate and a source / drain region of the second transistor, the second coupling being positioned under the second transistor region in the vertical dimension.

37. The memory device of claim 36, wherein the first inverter is cross-coupled to the second inverter through the first coupling and the second coupling.

38. The memory device of claim 36, further comprising a metal layer located below the second transistor region in the vertical dimension, wherein the metal layer includes power wiring connected to the first inverter and the second inverter.

39. The memory device of claim 38, wherein the first coupling and the second coupling are positioned between the metal layer and the second transistor region in the vertical dimension.

40. The memory device of claim 36, wherein the outputs of the third and fourth transistors are provided as the inputs of the first and second transistors, and wherein the outputs of the first and second transistors are provided as the inputs of the third and fourth transistors.

41. A memory device, the memory device comprising: a plurality of bit cells, wherein the bit cells include a first set of first transistors formed in a first transistor region and a second set of second transistors formed in a second transistor region, the second transistor region being positioned below the first transistor region in a vertical dimension perpendicular to the plurality of bit cells, wherein the plurality of bit cells are divided into at least a first bit cell array and a second bit cell array; a first metal layer located below the plurality of bit cells in the vertical dimension, wherein the first metal layer includes first wiring coupled to bit line outputs of the first array of bit cells; a second metal layer located above the plurality of bit cells in the vertical dimension, wherein the second metal layer includes second wiring coupled to bit line outputs of the second array of bit cells; a first column input / output logic unit coupled to the bit line output of the first bit cell array through the first wiring; and a second column input / output logic unit coupled to the bit line output of the second bit cell array through the second wiring; The first bit cell array is located farther away from the first column input / output logic unit and the second column input / output logic unit than the second bit cell array.

42. The memory device of claim 41, wherein an output of the first column input / output logic unit is coupled to an output of the second column input / output logic unit.

43. The memory device of claim 41, wherein the bit line output of the first bit cell array comprises outputs from a pair of complementary bit lines coupled to the first bit cell array.

44. The memory device of claim 41, wherein the bit line outputs of the second bit cell array comprise outputs from a pair of complementary bit lines coupled to the second bit cell array.

45. The memory device of claim 41, wherein the bit line output of the first bit cell array and the bit line output of the second bit cell array are outputs of at least some first transistors.

46. ​​The memory device of claim 41, wherein the bit line output of the first bit cell array is coupled to a pair of bit lines positioned in the second metal layer, the memory device further comprising: A first pair of connections between the bit lines in the second metal layer and the first wiring in the first metal layer, the first pair of connections being located proximate to the first bit cell array.

47. The memory device of claim 46, wherein the first pair of connections are positioned in a pair of first dummy cells near a boundary between the first bitcell array and the second bitcell array.

48. The memory device of claim 41 , further comprising: A second pair of connections between the second wiring in the second metal layer and the input of the second column input / output logic unit, the second pair of connections are located near the second column input / output logic unit, and the input of the second column input / output logic unit is positioned in the second transistor region.

49. The memory device of claim 48, wherein the second pair of connections are positioned in a second dummy cell near a boundary between the first column of input / output logic cells and the second column of input / output logic cells.

50. The memory device of claim 41, wherein the first bit cell array is adjacent to the second bit cell array in a horizontal dimension perpendicular to the vertical dimension, and wherein the first column of input / output logic cells is adjacent to the second column of input / output logic cells in the horizontal dimension.

51. The memory device of claim 41 , wherein the first column of input / output logic cells comprises: a third group of first transistors formed in the first transistor region; and a fourth group of second transistors formed in the second transistor region; An input of the first transistor and an input of the second transistor are combined and coupled to the bit line output of the first bit cell array through the first wiring.

52. The memory device of claim 51, wherein gates of at least two of the first transistors are coupled by wiring in the second metal layer.

53. The memory device of claim 51, wherein the third group of first transistors includes two first transistors, and wherein the fourth group of second transistors includes five second transistors.

54. The memory device of claim 41 , wherein at least one of the bit cells comprises four first transistors and two second transistors, the bit cell having: a first pass gate formed by a first one of the first transistors; a second pass gate formed by a second first transistor among the first transistors; a first inverter formed by a third first transistor among the first transistors and a first second transistor among the second transistors; and a second inverter formed by a fourth first transistor among the first transistors and a second second transistor among the second transistors; Wherein an input of the first inverter is cross-coupled with an output of the second inverter, and wherein an input of the second inverter is cross-coupled with an output of the first inverter.

55. An input / output logic unit for a memory device, the input / output logic unit comprising: a pair of first transistors formed in the first transistor region, wherein the first transistors include a first input source / drain region, a first output source / drain region, and a first gate; a set of five second transistors formed in a second transistor region, wherein the second transistors include a second input source / drain region, a second output source / drain region, and a second gate, and wherein the second transistor region is positioned below the first transistor region in a vertical dimension; a first metal layer located below the second transistor region in the vertical dimension, wherein the first metal layer includes a first wiring coupled to a bit line output of a first bit cell array; and a second metal layer located above the first transistor region in the vertical dimension; wherein the first input source / drain region of the first transistor and the second input source / drain region of the second transistor are merged, and wherein the merged source / drain region is coupled to the bit line output of the first bit cell array through the first wiring; wherein the gates of the pair of first transistors are coupled through wiring in the second metal layer, and wherein the gates of at least two of the second transistors are coupled through wiring in the first metal layer.

56. The input / output logic unit of claim 55, further comprising a second input / output logic unit for the memory device, the second input / output logic unit comprising: a second pair of first transistors formed in the first transistor region; and A second group of five second transistors is formed in the second transistor region.

57. An input / output logic unit according to claim 56, wherein the second metal layer includes a second wiring coupled to the bit line output of the second bit cell array, and wherein the merged source / drain region in the second input / output logic unit is coupled to the bit line output of the second bit cell array through the second wiring.

58. A memory device, the memory device comprising: a plurality of bit cells, wherein the bit cells include a first set of first transistors formed in a first transistor region and a second set of second transistors formed in a second transistor region, the second transistor region being positioned below the first transistor region in a vertical dimension perpendicular to the plurality of bit cells, wherein the plurality of bit cells are divided into at least a first bit cell array and a second bit cell array; a first metal layer located below the plurality of bit cells in the vertical dimension, wherein the first metal layer includes a first wiring; a second metal layer located above the plurality of bit cells in the vertical dimension, wherein the second metal layer includes second wiring coupled to bit line outputs of the second array of bit cells; a pair of bit lines positioned in the second metal layer, the pair of bit lines coupled to the bit line outputs of the first bit cell array; and A pair of connections between the bit line in the second metal layer and the first wiring in the first metal layer, the pair of connections being located near the first bit cell array.

59. The memory device of claim 58, wherein the pair of connections are positioned in a pair of dummy cells near a boundary between the first bitcell array and the second bitcell array.

60. The memory device of claim 59, wherein the pair of connections comprises trench metal in the pair of dummy cells.

61. An apparatus, comprising: a first vertical transistor formed in a transistor region of an integrated circuit unit structure, the first vertical transistor having a lower source / drain region, a first gate, and an upper source / drain region stacked in a vertical dimension; a second vertical transistor formed in the transistor region, the second vertical transistor having a lower source / drain region, a second gate, and an upper source / drain region stacked in the vertical dimension, wherein the second vertical transistor is parallel to the first vertical transistor and has at least some spacing therebetween in the horizontal dimension; a first metal layer located above the transistor region in the vertical dimension, wherein the first metal layer includes signal wiring; a second metal layer located below the transistor region in the vertical dimension, wherein the second metal layer includes power wiring; and A third metal layer is positioned below the lower source / drain regions and above the second metal layer, wherein the third metal layer includes at least one metal portion in contact with at least one of the lower source / drain regions.

62. The device of claim 61, wherein the first vertical transistor and the second vertical transistor are complementary transistor types.

63. The device according to claim 61, wherein the signal wiring includes a signal input wiring and a signal output wiring for the first vertical transistor and the second vertical transistor.

64. The apparatus of claim 61, further comprising a first via coupled between the at least one metal portion in the third metal layer and the power wiring in the second metal layer.

65. The apparatus of claim 61, further comprising at least one via coupled between at least one upper source / drain region and the signal routing in the first metal layer.

66. The device of claim 61, wherein the at least one metal portion in contact with at least one of the lower source / drain regions is in contact with at least one additional lower source / drain region of the lower source / drain regions.

67. The apparatus of claim 61, further comprising: A fourth metal layer is positioned above the upper source / drain regions and below the first metal layer, wherein the fourth metal layer includes at least one metal portion in contact with at least one of the upper source / drain regions.

68. The device of claim 67, wherein the at least one metal portion contacts an upper source / drain region of at least one additional vertical transistor in the integrated circuit cell structure.

69. The apparatus of claim 61, further comprising: wherein the second vertical transistor is a transistor type complementary to the first vertical transistor, and the second gate is merged with the first gate; The third metal layer comprises: a first metal contact coupled to the lower source / drain region of the first vertical transistor; and a second metal contact coupled to the lower source / drain region of the second vertical transistor; a first via coupled between the first metal contact and the power wiring in the second metal layer; and A second via is coupled between the second metal contact and the power wiring in the second metal layer.

70. The apparatus of claim 69, further comprising: a first via coupled between the upper source / drain region of the first vertical transistor and the signal wiring in the first metal layer; and A second via is coupled between the upper source / drain region of the second vertical transistor and the signal wiring in the first metal layer.

71. The apparatus of claim 69, further comprising: a gate bridge extending across the at least some spacing between the vertical transistors, wherein the gate bridge merges the first gate to the second gate; and A gate via is coupled between the gate bridge and the signal wiring in the first metal layer.

72. The apparatus of claim 61, further comprising: a first dielectric wall positioned on a first side of the first vertical transistor in the horizontal dimension; and A second dielectric wall is positioned on a second side of the second vertical transistor in the horizontal dimension, the second side of the second vertical transistor being distal from the first side of the first side of the first vertical transistor in the device.

73. An apparatus, comprising: a first vertical transistor formed in a transistor region of an integrated circuit unit structure, the first vertical transistor having a lower source / drain region, a first gate, and an upper source / drain region stacked in a vertical dimension; a second vertical transistor formed in the transistor region, the second vertical transistor having a lower source / drain region, a second gate, and an upper source / drain region stacked in the vertical dimension, the second gate being merged with the first gate, wherein the second vertical transistor is parallel to the first vertical transistor and the vertical transistors have at least a first spacing therebetween in the horizontal dimension; a third vertical transistor formed in the transistor region of the integrated circuit unit structure, the third vertical transistor having a lower source / drain region, a third gate, and an upper source / drain region stacked in the vertical dimension; a fourth vertical transistor formed in the transistor region, the fourth vertical transistor having a lower source / drain region, a fourth gate, and an upper source / drain region stacked in the vertical dimension, the fourth gate being merged with the third gate, wherein the fourth vertical transistor is parallel to the third vertical transistor and the vertical transistors have the at least a first spacing therebetween in the horizontal dimension; wherein the second vertical transistor and the fourth vertical transistor are transistor types complementary to the first vertical transistor and the third vertical transistor, and wherein the third vertical transistor and the fourth vertical transistor are parallel to the first vertical transistor and the second vertical transistor and have at least a second spacing in the horizontal dimension, the second spacing being perpendicular to the first spacing; a first metal layer located above the transistor region in the vertical dimension, wherein the first metal layer includes signal wiring; a second metal layer located below the transistor region in the vertical dimension, wherein the second metal layer includes power wiring; a third metal layer positioned below the lower source / drain region and above the second metal layer, wherein the third metal layer comprises: a first metal contact coupled to the lower source / drain region of the first vertical transistor; a second metal contact coupled to the lower source / drain region of the second vertical transistor; and a third metal contact coupled to the lower source / drain region of the third vertical transistor; a fourth metal layer positioned above the upper source / drain and below the first metal layer, wherein the fourth metal layer comprises: a first metal strip coupled between the upper source / drain region of the first vertical transistor and the upper source / drain region of the third vertical transistor; and a second metal strip coupled between the upper source / drain region of the second vertical transistor and the upper source / drain region of the fourth vertical transistor; a first via coupled between the first metal contact and the power wiring in the second metal layer; a second via coupled between the second metal contact and the power wiring in the second metal layer; and A third via is coupled between the third metal contact and the power wiring in the second metal layer.

74. A device according to claim 73, wherein the third metal layer includes a fourth metal contact coupled to the lower source / drain region of the fourth vertical transistor, wherein the fourth metal contact extends toward a boundary of the integrated circuit unit structure, and the device also includes a contact via coupled between the fourth metal contact and the power and / or signal wiring in the first metal layer.

75. The apparatus of claim 73, further comprising a first via coupled between the first metal strip and the signal routing in the first metal layer.

76. The apparatus of claim 73, further comprising: a first gate bridge extending across the at least some first spacing between the first vertical transistor and the second vertical transistor, wherein the first gate bridge merges the first gate into the second gate; a second gate bridge extending across the at least some first interval between the third vertical transistor and the fourth vertical transistor, wherein the second gate bridge merges the third gate into the fourth gate; a first gate via coupled between the first gate bridge and the signal wiring in the first metal layer; and A second gate via is coupled between the second gate bridge and the signal wiring in the first metal layer.

77. An apparatus, comprising: a first vertical transistor formed in a transistor region of an integrated circuit unit structure, the first vertical transistor having a lower source / drain region, a first gate, and an upper source / drain region stacked in a vertical dimension; a second vertical transistor formed in the transistor region, the second vertical transistor having a lower source / drain region, a second gate, and an upper source / drain region stacked in the vertical dimension, wherein the second vertical transistor is parallel to the first vertical transistor and has at least a first spacing therebetween in the horizontal dimension; a third vertical transistor formed in the transistor region of the integrated circuit unit structure, the third vertical transistor having a lower source / drain region, a third gate, and an upper source / drain region stacked in the vertical dimension; a fourth vertical transistor formed in the transistor region, the fourth vertical transistor having a lower source / drain region, a fourth gate, and an upper source / drain region stacked in the vertical dimension, wherein the fourth vertical transistor is parallel to the third vertical transistor and has the at least a first spacing therebetween in the horizontal dimension; wherein the second vertical transistor and the fourth vertical transistor are transistor types complementary to the first vertical transistor and the third vertical transistor, and wherein the third vertical transistor and the fourth vertical transistor are parallel to the first vertical transistor and the second vertical transistor and have at least a second spacing in the horizontal dimension, the second spacing being perpendicular to the first spacing; a first metal layer located above the transistor region in the vertical dimension, wherein the first metal layer includes signal wiring; a third metal layer positioned below the lower source / drain region, wherein the third metal layer comprises: a metal contact plate coupled to the lower source / drain regions of the first vertical transistor, the second vertical transistor, the third vertical transistor, and the fourth vertical transistor; a fourth metal layer positioned above the upper source / drain region and below the first metal layer, wherein the fourth metal layer comprises: a first metal strip coupled between the upper source / drain region of the first vertical transistor and the upper source / drain region of the second vertical transistor; and A second metal strip is coupled between the upper source / drain region of the third vertical transistor and the upper source / drain region of the fourth vertical transistor.

78. The apparatus of claim 77, further comprising: a first gate extension extending from the first gate toward a boundary of the integrated circuit unit in the horizontal dimension; a second gate extension extending from the second gate toward the boundary of the integrated circuit unit in the horizontal dimension, the second gate extension extending toward the boundary in an opposite direction from the first gate extension; a third gate extension extending from the third gate toward the boundary of the integrated circuit unit in the horizontal dimension, the third gate extension extending toward the boundary in the same direction as the first gate extension; and A fourth gate extension extends from the fourth gate toward the boundary of the integrated circuit unit in the horizontal dimension, the fourth gate extension extending toward the boundary in the same direction as the second gate extension.

79. The apparatus of claim 78, further comprising: a first gate via coupled between the first gate extension and the signal wiring in the first metal layer; a second gate via coupled between the second gate extension and the signal wiring in the first metal layer; a third gate via coupled between the third gate extension and the signal wiring in the first metal layer; and A fourth gate via is coupled between the fourth gate extension and the signal wiring in the first metal layer.

80. The apparatus of claim 77, further comprising a contact via coupled between the metal contact plate and the signal wiring in the first metal layer.

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