A method for inserting sub-resolution assist features

Abstract

The present invention discloses a method for inserting sub-resolution assist features, specifically an optimization method for sub-resolution assist feature insertion rules and a method for inserting sub-resolution assist features applying the optimization method. First, sub-resolution assist feature parameters are set, a distance metric function is selected according to the main pattern, and the main pattern is converted into a level set representation using a signed distance function. Then, according to the set sub-resolution assist feature parameters, multiple circles of sub-resolution assist features are inserted around the main pattern. Conflict cleaning is performed on the multiple circles of sub-resolution assist features, and finally a chamfering operation is carried out to complete the optimization. By changing the above sub-resolution assist feature parameters and performing separate insertions, the insertion rule with the greatest improvement in mask optimization effect is selected as the final sub-resolution assist feature insertion rule to be used. The present invention has the advantages of simple parameters, high mask manufacturability, and significant mask optimization effect, and is applicable to the field of next-generation integrated circuit manufacturing.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a method for inserting sub-resolution assist features. Background Art

[0002] With the rapid development of semiconductor technology, the feature size of integrated circuits has gradually entered the nanoscale era, posing unprecedented challenges to the lithography process. Lithography, as the most critical manufacturing process in semiconductor manufacturing, aims to accurately transfer the designed pattern onto the silicon wafer to form a micro-nano structure with specific functions. However, with the continuous reduction of the feature size, the lithography process faces a series of severe problems, among which the most significant is the sharp reduction of the process window. The process window refers to the range of lithography conditions that can ensure the pattern transfer quality (such as line width, edge roughness, etc.) meets the design requirements, including the fluctuation ranges of parameters such as exposure dose and focal length. The reduction of the process window means that the lithography process is more sensitive to changes in process parameters, and any slight deviation may lead to a decrease in product yield. To effectively address this challenge, the industry widely adopts the sub-resolution assist feature technology.

[0003] Sub-resolution assist features (SRAFs) are auxiliary features located near the main features, which do not directly image on the silicon wafer. Their role is to optimize the light intensity contrast by affecting the light field distribution during the lithography process, thereby reducing the impact of process parameter changes on the pattern transfer quality, and further expanding the process window. The design of sub-resolution assist features usually follows certain rules, such as being placed at a certain distance outside the edge of the main feature, and the shape is mostly a simple parallel strip, in order to maximize the robustness of the lithography process without affecting the final imaging result.

[0004] The addition of sub-resolution assist features usually adopts the method of adding sub-resolution assist features based on rules, and its process is as follows: establish a set of rules for adding sub-resolution assist features, and add sub-resolution assist features around the target feature according to this rule; the other is the addition of sub-resolution assist features based on a model, and after establishing the model, the sub-resolution assist features with the best effect are obtained through iterative fitting operations. Although the traditional method for inserting sub-resolution assist features has been widely used due to its fewer parameters, intuitive design, and relatively simple optimization, its limitations are also becoming increasingly prominent. First, this simple parallel strip structure has poor adaptability to complex features and is difficult to fully cope with process variations in different layouts and directions, resulting in limited improvement of the process window. Second, with the further reduction of the feature size, the physical effects (such as scattering, diffraction) during the lithography process become more complex, and the simple design of sub-resolution assist features has been difficult to meet the increasing accuracy requirements. Summary of the Invention

[0005] The first object of the present invention is to provide an optimization method for sub-resolution assist feature insertion rules in view of the deficiencies of the prior art, which can improve the effect of mask optimization while maintaining a simple form.

[0006] To solve the above technical problems, the present invention adopts the following technical solutions:

[0007] An optimization method for sub-resolution assist feature insertion rules includes the following steps:

[0008] S1. Set sub-resolution assist feature parameters, including the distance d1 between the sub-resolution assist feature and the main feature, the distance d2 between sub-resolution assist features, and the width w of the sub-resolution assist feature. The parameters used in the present invention are similar to those of traditional sub-resolution assist feature insertion methods, but the insertion methods are different. The setting of these parameters depends on the experience of engineers. By setting them within a certain range with reasonable step sizes, the balance between optimization accuracy and optimization effect can be ensured.

[0009] By reasonably setting d1 and d2, sub-resolution assist features can be inserted at appropriate positions, converting isolated features into dense features, thereby optimizing the light intensity contrast at the edge of the main feature, reducing the process variation bandwidth, and increasing the lithography process window. Unreasonable d1 and d2 may insert sub-resolution assist features into forbidden optical periods, weakening the light intensity contrast at the edge of the main feature and having a negative impact on the mask optimization effect. Therefore, careful parameter tuning of d1 and d2 is required.

[0010] Generally, a larger w can provide a more obvious optimization effect on the light intensity contrast at the edge of the main feature. However, an overly large w will bring the risk of imaging sub-resolution assist features on the silicon wafer, so it also needs to be reasonably set.

[0011] S2. According to the given main feature, select a suitable distance metric function, and use the Signed Distance Function (SDF) to represent the distance between each point in the design layout and the boundary of the main feature. SDF is a scalar field, where the value of each point represents the distance from that point to the nearest boundary, and the positive and negative signs indicate whether the point is outside or inside the boundary, respectively. Through SDF, the topological structure of the feature can be conveniently described.

[0012] Furthermore, the distance metric function includes Chebyshev distance, Manhattan distance, Euclidean distance, etc.

[0013] After the calculation of the signed distance function (SDF), the main pattern is converted into a level set representation. The level set is a method for describing the evolution of curves or surfaces, which represents the position and shape of curves or surfaces through an implicit function. By converting the main pattern into a level set representation, it is convenient to control the insertion position and width of the sub-resolution assist features (SRAFs).

[0014] S3. According to the sub-resolution assist feature parameters set in step S1, multiple circles of sub-resolution assist features are inserted around the main pattern. Specifically, the region satisfying the condition "d1 < SDF < d1 + w" is used as the first circle of sub-resolution assist features; the region satisfying the condition "d1 + d2 + w < SDF < d1 + d2 + 2w" is used as the second circle of sub-resolution assist features; the region satisfying the condition "d1 + 2d2 + 2w < SDF < d1 + 2d2 + 3w" is used as the third circle of sub-resolution assist features. And so on, multiple circles of sub-resolution assist features can be inserted.

[0015] Preferably, the number of inserted circles of sub-resolution assist features is three.

[0016] S4. Conflict cleaning is performed on the sub-resolution assist features to ensure that the sub-resolution assist features satisfy the lithography design rules among themselves and between the sub-resolution assist features and the main pattern; after the insertion of the sub-resolution assist features, it is also necessary to consider the conflicts between the sub-resolution assist features and the minimum feature pitch, minimum feature width, and the width w of the sub-resolution assist features. For these problems, the present invention provides a graphic conflict handling mechanism to ensure that the processed sub-resolution assist features meet the preset constraints.

[0017] Among the minimum feature pitch and minimum feature width, the features include the main pattern and the assist features; that is, the minimum feature distance is the minimum value of the pitch between SRAFs and the pitch between SRAF and the main pattern. When designing SRAFs, it is necessary to ensure that the distance between SRAFs and between SRAF and the main pattern is not less than the minimum feature pitch allowed by the manufacturing process, otherwise it may affect the feasibility of lithography manufacturing. The minimum feature width refers to the minimum allowable width that all graphic elements (main pattern and SRAF) must satisfy.

[0018] S5. Chamfering operations are performed on the sub-resolution assist features to complete the optimization of the sub-resolution assist features. Chamfering operations are a commonly used graphic processing means. By performing chamfering operations on the sub-resolution assist features, the degree of the increased corner can be reduced, and the probability of the sub-resolution assist features imaging on the silicon wafer can be reduced. At the same time, it can also make the shape of the sub-resolution assist features closer to a circle, making the distance between its edge and the main pattern more uniform, so as to further improve the mask optimization effect.

[0019] Further, the distance of the chamfering operation can be chamfered at a fixed distance or chamfered according to a certain proportion of the side length.

[0020] S6. Use the lithography model to perform optical proximity effect correction on the lithography patterns inserted with different sub-resolution assist features respectively, and evaluate the mask optimization effect. If the mask optimization effect is better than the previous optimal rule, update the optimal rule.

[0021] Further, the evaluation indicators of the above mask optimization effect include process variation bandwidth, pattern fidelity, pattern edge light intensity contrast, and the number of lithography defects, etc.

[0022] The second object of the present invention is to provide a method for inserting sub-resolution assist features, including the following steps:

[0023] S1. According to the integrated circuit layout design rules and lithography process parameters, design a lithography pattern for testing and evaluation, and fabricate it into a photomask. After the photomask is fabricated, use the photomask to expose the silicon wafer, and collect measurement data to correct the lithography model, laying a foundation for subsequent evaluation of the mask optimization effect;

[0024] S2. Use the optimization method of the above sub-resolution assist feature insertion rules to change the set sub-resolution assist feature parameters, and insert different sub-resolution assist features into the lithography pattern; the above insertion process can be quickly realized through Electronic design automation (EDA) software to shorten the process R & D cycle. Then perform optical proximity effect correction respectively, and evaluate the mask optimization effect under different insertion rules.

[0025] S3. Select the insertion rule with the largest improvement in the mask optimization effect as the final sub-resolution assist feature insertion rule to be used.

[0026] Further, the optimization algorithms that can be adopted in the process of determining the insertion rule of the optimal sub-resolution assist feature include grid search method, experimental design method, genetic algorithm, etc.

[0027] The third object of the present invention is to provide a sub-resolution assist feature insertion device, including:

[0028] A rule optimization module, configured to obtain the optimal insertion rule by using the optimization method of the above sub-resolution assist feature insertion rules;

[0029] A sub-resolution assist feature adding module, configured to insert sub-resolution assist features into the lithography pattern according to the optimal insertion rule.

[0030] The fourth object of the present invention is to provide a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the above method is implemented.

[0031] The fifth object of the present invention is to provide an electronic device, including a processor and a storage medium, the storage medium stores a computer program, and when the processor executes the computer program, the above method is implemented.

[0032] Compared with the prior art, the beneficial effects achieved by the present invention are:

[0033] The present invention proposes an optimization method for sub-resolution assist feature insertion rules and an insertion method thereof. The method converts the main pattern into a level set representation, inserts a ring-shaped sub-resolution assist feature, and introduces a method for handling pattern conflicts and a chamfering operation, making the insertion position of the sub-resolution assist feature more reasonable. The method has the advantages of simple parameters, high mask manufacturability, and outstanding mask optimization effect, and can be widely applied to the field of next-generation integrated circuit manufacturing.

[0034] The present invention can improve the mask optimization effect, enhance the lithography process window, reduce imaging errors, optimize the distribution of sub-resolution assist features, and ensure that the final design complies with manufacturing rules, thereby improving the accuracy and yield of chip manufacturing. Brief Description of the Drawings

[0035] Figure 1 is a schematic flow chart of a method for inserting a sub-resolution assist feature in an embodiment of the present invention.

[0036] Figure 2 is a schematic flow chart of generating a sub-resolution assist feature under specific insertion rules in an embodiment of the present invention.

[0037] Figure 3 is a schematic diagram of inserting multiple circles of sub-resolution assist features according to SDF in an embodiment of the present invention.

[0038] Figure 4 is a schematic diagram of chamfering the sub-resolution assist feature in an embodiment of the present invention. Detailed Description of the Embodiments

[0039] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0040] Figure 1 is a schematic flow chart of a method for inserting a sub-resolution assist feature in an embodiment of the present invention.

[0041] Please refer to Figure 1 , the insertion process of the sub-resolution assist feature includes:

[0042] Step S1: Photomask fabrication and lithography model calibration.

[0043] First, according to the integrated circuit layout design rules and lithography process parameters, a set of lithography patterns for testing and evaluation is designed. Taking the first layer of vias at the 55-nanometer technology node as an example, these patterns contain key features such as isolated vias and dense vias of different sizes to ensure the accuracy and representativeness of the test results. Subsequently, the designed lithography patterns are fabricated into a photomask for subsequent exposure experiments.

[0044] After the photomask is fabricated, the silicon wafer is subjected to an exposure experiment using this photomask, and the measured data after exposure is collected. These data include the measurement values of different key features. Then, these data are used to correct the lithography model to ensure that the model can accurately reflect various effects during the lithography process, laying a foundation for subsequent evaluation of the mask optimization effect.

[0045] Step S2: Design multiple sets of sub-resolution assist feature insertion rules, and perform optical proximity effect correction and mask optimization effect evaluation respectively.

[0046] Next, according to the experience of engineers and the requirements of the lithography process, multiple sets of different sub-resolution assist feature insertion rules are designed to optimize the sub-resolution assist feature insertion rules. Specifically, as Figure 2 shown, it includes the following steps:

[0047] S21. Set the sub-resolution assist feature parameters, including the distance d1 between the sub-resolution assist feature and the main feature, the distance d2 between sub-resolution assist features, and the width w of the sub-resolution assist feature; each set of rules includes parameters such as the distance d1 between the sub-resolution assist feature and the main feature, the distance d2 between sub-resolution assist features, and the width w of the sub-resolution assist feature.

[0048] Taking an isolated square via with a side length of 110 nm as an example, set the distance d1 between the sub-resolution assist feature and the main feature to 110 nm, the distance d2 between sub-resolution assist features to 110 nm, and the width w of the sub-resolution assist feature to 34 nm. Study the improvement effect of this set of insertion rules on the mask optimization effect.

[0049] S22. Select a distance metric function according to the main feature, and use the signed distance function SDF to represent the distance between each point in the lithography pattern and the boundary of the main feature, and convert the main feature into a level set representation;

[0050] The distance metric function adopts the Chebyshev distance, Manhattan distance or Euclidean distance. In this embodiment, the Chebyshev distance is selected as the distance metric function. The signed distance function (SDF) is used to represent the distance between each point and the boundary. A negative distance indicates inside the main pattern, and a positive distance indicates outside the main pattern. This representation method can conveniently control the insertion position and width of the sub-resolution assist patterns.

[0051] S23. According to the set sub-resolution assist pattern parameters, insert multiple circles of sub-resolution assist patterns around the main pattern, as Figure 3 shown;

[0052] The first circle of sub-resolution assist patterns: the area satisfying the condition "110nm < SDF < 144nm".

[0053] The second circle of sub-resolution assist patterns: the area satisfying the condition "254nm < SDF < 288nm".

[0054] The third circle of sub-resolution assist patterns: the area satisfying the condition "398nm < SDF < 432nm".

[0055] By this method, multiple circles of annular sub-resolution assist patterns can be inserted around the main pattern.

[0056] Step S24: Clean up the conflicts of multiple circles of sub-resolution assist patterns;

[0057] After the insertion of the sub-resolution assist patterns is completed, it is also necessary to consider the conflict issues of the sub-resolution assist patterns with the minimum feature pitch, minimum feature width, and the width w of the sub-resolution assist patterns. For this reason, a pattern conflict handling mechanism is proposed. This mechanism detects and processes potential conflicts to ensure that the processed sub-resolution assist patterns meet the design rules, guarantee the manufacturability of the mask, and reduce the risk of the sub-resolution assist patterns imaging on the silicon wafer.

[0058] For the conflict where the pitch between sub-resolution assist patterns violates the minimum feature pitch, if the two are in different circles, keep the inner circle of sub-resolution assist patterns; if the two are in the same circle, randomly keep one of them. For the conflict where the width of the sub-resolution assist pattern violates the minimum feature width, expand the width of the sub-resolution assist pattern outward until it meets the minimum feature width. For the conflict where the width of the sub-resolution assist pattern is greater than the preset parameter w, contract the width of the sub-resolution assist pattern inward to w.

[0059] Step S25: Chamfer the sub-resolution assist patterns after conflict cleaning to complete the optimization of the sub-resolution assist patterns.

[0060] To reduce the probability of sub-resolution assist features imaging on the silicon wafer and further improve the mask optimization effect, chamfering operations were performed on the sub-resolution assist features. The chamfering distance was based on a certain proportion of the side length of the sub-resolution assist features. As Figure 4 shown, for square sub-resolution assist features, chamfers were selected at 29% and 71% of the side length. After chamfering, the outline of the sub-resolution assist features approximated that of a regular octagon. This operation made the outline of the sub-resolution assist features closer to a circle, with a more uniform distance from the main feature edge, thereby enhancing the light intensity contrast at the mask edge. At the same time, increasing the corners of the sub-resolution assist features also helped reduce the risk of their imaging on the silicon wafer.

[0061] Step S26: Optical proximity effect correction and mask optimization effect evaluation.

[0062] For each set of sub-resolution assist feature insertion rules, optical proximity effect correction was performed on the design layout using the calibrated lithography model. The corrected layout fully considered various effects during the lithography process, thus obtaining a silicon wafer pattern closer to the expected design.

[0063] Then, mask correction evaluation metrics were used to evaluate the mask optimization effects of different sub-resolution assist feature insertion rules. The process variation band (PVB) was mainly referred to. During the lithography process, the process variation band refers to the range of pattern size variations caused by various factors. The smaller the PVB, the larger the lithography process window.

[0064] According to the above method, the set sub-resolution assist feature parameters were changed, and sub-resolution assist features under different rules were inserted into the lithography pattern. To ensure a balance between optimization accuracy and optimization effect, a uniform step size was set within a reasonable range. Each insertion rule corresponded to a split. In this experiment, the values of d1 included [90, 100, 110, 120, 130], the values of d2 included [90, 100, 110, 120, 130], and the values of w included [26, 30, 34, 38, 42, 46]. Each insertion rule corresponded to a sub-resolution assist feature split. The above parameters corresponded to a total of 5 * 5 * 6 = 150 sub-resolution assist feature splits, and the best insertion rule needed to be found among them.

[0065] During the design process, electronic design automation (EDA) software was used to quickly implement the insertion of sub-resolution assist features and subsequent evaluations, thus shortening the R & D cycle of the lithography process. Specifically, the design layout was imported through the EDA software, and sub-resolution assist features were automatically inserted around the main features according to the set parameters, and subsequent evaluations were carried out.

[0066] Step S3: Determine the optimal sub-resolution assist feature insertion rule.

[0067] After evaluating the mask optimization effects of different sub-resolution assist feature insertion rules, the insertion rule with the greatest improvement in mask optimization effect is selected as the sub-resolution assist feature insertion rule finally used in the production line. To find the optimal rule, a grid search method is adopted for parameter tuning. The lithography model is used to calculate the final PVB of 150 sub-resolution assist feature splits, and the insertion rule corresponding to the split with the minimum PVB is selected as the sub-resolution assist feature insertion rule finally used in the production line.

[0068] The above are only the preferred embodiments of one or more embodiments of this specification, and are not intended to limit one or more embodiments of this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of one or more embodiments of this specification shall be included within the scope of protection of one or more embodiments of this specification.

Claims

1. An optimization method for sub-resolution assist feature insertion rules, characterized in that It includes the following steps: S1. Set the sub-resolution assist feature parameters, including the distance d1 between the sub-resolution assist feature and the main feature, the distance d2 between sub-resolution assist features, and the width w of the sub-resolution assist feature; S2. Select a distance metric function according to the main feature, and use the signed distance function SDF to represent the distance between each point in the design layout and the boundary of the main feature, and convert the main feature into a level set representation; the distance metric function uses the Chebyshev distance; S3. Insert multiple circles of sub-resolution assist features around the main feature according to the set sub-resolution assist feature parameters; The shape of the sub-resolution assist feature is a square; S4. Clean up the conflicts of multiple circles of sub-resolution assist features; specifically including: (1) Detect the spacing conflict between sub-resolution assist features: If the spacing between adjacent sub-resolution assist features is less than the minimum feature spacing, it is determined that there is a conflict, otherwise there is no conflict; if the conflicting sub-resolution assist features are in different circles, retain the inner circle sub-resolution assist features close to the main feature and delete the conflicting features in the outer circle; If the conflicting sub-resolution assist features are in the same circle, randomly delete one of them to eliminate the conflict; (2) Detect the width conflict of sub-resolution assist features: If the width of the sub-resolution assist feature is less than the minimum feature width, it is determined that there is a conflict, and the width of the sub-resolution assist feature is extended outwards to meet the minimum feature width requirement; otherwise there is no conflict; If the width of the sub-resolution assist feature is greater than the preset width parameter w, it is determined that there is a conflict, and the width of the sub-resolution assist feature is contracted inwards to w; otherwise there is no conflict; S5. Chamfer the multiple circles of sub-resolution assist features after conflict cleaning to obtain octagonal sub-resolution assist features, and complete the optimization of the insertion rules for sub-resolution assist features; perform optical proximity effect correction on the design layout and evaluate the mask optimization effect; S6. Change the sub-resolution assist feature parameters, repeat steps S2 to S5, if the mask optimization effect is better than the previous insertion rules, update the insertion rules until the optimal insertion rules are obtained.

2. The optimization method of the sub-resolution assist feature insertion rule according to claim 1, wherein Step S3 is specifically: Take the area where "d1 < SDF < d1 + w" is satisfied as the first circle of sub-resolution assist features; Take the area where "d1 + d2 + w < SDF < d1 + d2 + 2w" is satisfied as the second circle of sub-resolution assist features; Take the area where "d1 + 2d2 + 2w < SDF < d1 + 2d2 + 3w" is satisfied as the third circle of sub-resolution assist features.

3. The optimization method of sub-resolution assist feature insertion rules according to claim 1, characterized in that The evaluation indexes of the mask optimization effect in step S5 include process variation bandwidth, pattern fidelity, pattern edge light intensity contrast, and the number of lithography defects.

4. A method for inserting sub-resolution assist features, characterized in that, It includes the following steps: S1. Design lithography patterns for testing and evaluation and their corresponding masks, fabricate the lithography patterns into photomasks, and collect measurement data to correct the lithography model; S2. Using the optimization method of the sub-resolution assist feature insertion rule according to any one of claims 1-3, change the set sub-resolution assist feature parameters, insert different sub-resolution assist features in the lithography pattern, and perform optical proximity effect correction respectively to evaluate the mask optimization effect; S3. Select the insertion rule with the greatest improvement in mask optimization effect as the finally used sub-resolution assist feature insertion rule to insert sub-resolution assist features.

5. A sub-resolution assist feature insertion device, characterized in that Including: A rule optimization module for obtaining the optimal insertion rule by using the optimization method of the sub-resolution assist feature insertion rule according to any one of claims 1-3; A sub-resolution assist feature addition module for inserting sub-resolution assist features in the lithography pattern according to the optimal insertion rule.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by a processor, it implements the method according to any one of claims 1-3 or the method according to any one of claims 4.

7. An electronic device, comprising a processor and a storage medium, characterized in that, The storage medium stores a computer program, and when the processor executes the computer program, it implements the method according to any one of claims 1-3 or the method according to any one of claims 4.

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