Methods for optimizing overlay mark signals

Abstract

The present invention discloses a method for optimizing an overlay mark signal, comprising the steps of: forming a filler pattern in a first region of an underlying material layer, wherein the reflectivity of the filler material of the filler pattern is greater than the reflectivity of the underlying material layer, the first region and at least a portion of the region where the overlay mark is formed intersect, and the pattern density of the filler pattern ensures that the top surface of the first region is flat. Forming a front material layer and forming a front-layer overlay mark in the overlay mark formation region of the front material layer. Forming a current material layer and forming a current-layer overlay mark in the overlay mark formation region of the current material layer; the front-layer and current-layer overlay marks form an overlay mark combination structure, and utilizing the flat structure of the top surface of the first region and the high reflectivity of the filler material to improve the overlay mark signal. The present invention can prevent the large area at the bottom of the front-layer overlay mark from adversely affecting the overlay mark signal, thereby optimizing the overlay mark signal and improving the accuracy of overlay measurement.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for optimizing an overlay mark signal. Background Art

[0002] Advanced semiconductor processes have two limiting parameters for photolithography: critical dimension (CD) and overlay. As critical dimensions become smaller and smaller, the requirements for overlay error become increasingly stringent. The pattern remaining in the photoresist after exposure and development must be aligned with the existing pattern on the wafer substrate to prevent short circuits and open circuits in the device. The relative position between the current pattern and the reference pattern is the overlay error. Overlay error is a parameter that measures the alignment quality and directly measures the positional deviation between the current layer and the reference layer. Since the photolithography OVL mark signal is easily affected by the previous layer process, as the precision requirements of advanced technology become higher and higher, the process becomes more and more complex, and the unstable photolithography OVL mark signal introduces overlay error, the OVL mark signal is particularly important for measurement.

[0003] With technological advancements, chip applications are becoming increasingly widespread. As process precision requirements grow, so too do the demands for measurement accuracy and precision. As processes become increasingly complex, the effects of underlying thin films, formed in previous processes, can be mitigated by existing methods, such as by designing various segments. However, these methods cannot completely resolve the mark signal issue.

[0004] Each layer of Mark occupies a position, which can ensure that all Marks do not interfere with each other (except the IMP layer). Therefore, only when the layer has a Mark, the other layers are blank areas, such as a blank area of ​​30 microns * 30 microns. The blank area is an area without graphics. The multiple layers at the bottom of the Mark include stacked layers of photoresist or film.

[0005] like Figure 1 FIG. 1 shows a layout of conventional overlay marks. Overlay marks 102 are typically located within cutting lanes 101. When there is no other overlay mark pattern below the overlay mark 102, there is no blank area. Overlay marks for other layers can be placed in other areas, such as area 103.

[0006] The measurement signal of an overlay mark measurement machine is realized using an optical signal. The diffraction intensity of the optical signal is affected by the sidewall angle of the grating of the underlying overlay mark, which in turn affects the overlay accuracy. The sidewall angle of the grating of the underlying overlay mark needs to undergo processes such as etching, film deposition, and chemical mechanical planarization. The underlying overlay mark here is also called the previous layer overlay mark. It will form an overlay mark combination structure with the current layer overlay mark. By measuring the offset between the previous layer overlay mark and the current layer overlay mark, the overlay mark signal can be obtained.

[0007] The material of the metal wire in the back-end process is often copper, formed by the Damascus process. In the dual Damascus process, through holes and top metal wires are formed at the same time. In the Damascus process, grooves are first carved, then filled with copper, and finally polished. Due to the fluctuation of local polishing rate in chemical mechanical planarization, the fluctuation is more obvious for large areas, resulting in erosion and wear. When the Damascus process is used to form the bottom layer overlay mark at the same time, the bottom layer overlay mark will also be eroded and worn. Figure 2 FIG. 1 is a cross-sectional structural diagram of a front layer overlay mark in an existing overlay mark combination, including:

[0008] The bottom substrate 201 and the front material layer 203 corresponding to the front overlay mark. The material of the front material layer 203 includes a low dielectric constant material, and a nitrogen-doped silicon nitride (NDC) layer 202 is also formed at the bottom of the front material layer 203. A plurality of copper strips 204 are used to form the front overlay mark. The copper strips 204 are all formed using the Damascene process, so they will form erosion defects shown in the dotted circle 206 and wear defects shown in the dotted circle 207. Erosion and wear defects will lead to the following: when measuring the overlay mark, the unevenness of the lower layer pattern will cause the reflected light to be disordered, or even asymmetric. The left-right asymmetry introduced by the reflected light will cause deviation in the overlay measurement.

[0009] In the prior art, the bottom layers of the previous layer with the overlay mark are all blank structures. Figure 3 The figure shows a cross-sectional structure diagram of the existing overlay mark combination structure after formation. The overlay marks corresponding to the metal lines and the bottom through holes include:

[0010] The bottom substrate 201 includes a bottom structure 301 , an NDC layer 302 and a bottom interlayer film 303 . Figure 3 Only the area where the overlay mark is formed is shown. It can be seen that no pattern structure is formed in the bottom interlayer film 303, which is a blank area.

[0011] The front material layer 203 includes an interlayer film 305 , an NDC layer 306 , an NFDARC layer 307 , a TiN layer 308 and an oxide layer 309 . Figure 3 In the embodiment, the patterned TiN layer 308 and the oxide layer 309 are used as front layer overlay marks. Figure 3 The structure shown is the structure in the dual damascene process. If the single damascene process is used, Figure 2 The copper stripe 204 shown constitutes the front layer overlay mark.

[0012] The current material layer includes a SOC layer 310 , a silicon bottom anti-reflective coating 311 and a photoresist 304 .

[0013] The photoresist 304 of the current material layer is patterned, and the current layer overlay mark is composed of the patterned photoresist 304 . Summary of the Invention

[0014] The technical problem to be solved by the present invention is to provide a method for optimizing the overlay mark signal, which can prevent the large area at the bottom of the front layer overlay mark from adversely affecting the overlay mark signal, thereby optimizing the overlay mark signal and improving the accuracy of overlay measurement.

[0015] To solve the above technical problems, the present invention provides a method for optimizing an overlay mark signal, comprising the steps of:

[0016] A bottom material layer is provided, and a filler pattern is formed in a first area of ​​the bottom material layer. The reflectivity of the filling material of the filler pattern is greater than the reflectivity of the bottom material layer. The first area intersects with at least a portion of the area where the overlay mark is formed. The pattern density of the filler pattern meets the requirements of plasma etching and chemical mechanical polishing processes for pattern density to ensure that the top surface of the first area is flat. The top surface of the first area includes the top surface of the bottom material layer and the top surface of the filler pattern.

[0017] A front material layer is formed and a front layer overlay mark is formed in the overlay mark formation region of the front material layer.

[0018] A current material layer is formed and a current layer overlay mark is formed in the overlay mark formation area of ​​the current layer material layer; the front layer overlay mark and the current layer overlay mark form an overlay mark combination structure, and the flat structure of the top surface of the first area and the high reflectivity of the filling material are used to improve the overlay mark signal.

[0019] A further improvement is that the material of the bottom material layer includes a low dielectric constant material; and the filling material includes metal.

[0020] A further improvement is that the material of the front material layer includes a low dielectric constant material, and the front material layer is used to form a through hole or a metal line.

[0021] The front layer overlay mark and through hole pattern are defined simultaneously.

[0022] A further improvement is that a metal hard mask layer is formed on the top surface or inside the front material layer, and the front overlay mark is composed of the patterned metal hard mask layer or the front overlay mark is composed of a through hole in the formation area of ​​the overlay mark.

[0023] A further improvement is that the material of the metal hard mask layer includes TiN.

[0024] A further improvement is that the underlying material layer includes photoresist, and the underlying overlay marks and metal line patterns are defined simultaneously.

[0025] The current layer overlay mark is composed of the patterned current layer material layer.

[0026] A further improvement is that the current material layer further includes a SOC layer and a silicon bottom anti-reflection coating.

[0027] A further improvement is that the metal material of the filling material, the through hole and the metal line is the same.

[0028] A further improvement is that the metal material of the filling material includes copper.

[0029] A further improvement is that the filler pattern is formed by densely arranging first strips, the size of which meets the requirements of the design rules and is smaller than the minimum wavelength of the signal received by the measuring machine of the overlay mark, so as to ensure that the signal of the bottom material layer will not be absorbed by the measuring machine, thereby avoiding interference with the measurement result of the overlay mark signal.

[0030] This avoids interference with the measurement result of the overlay mark signal.

[0031] A further improvement is that the wavelength range of the signal received by the overlay mark measuring machine is 300 nm to 700 nm, and the width of the first strip is less than 300 nm.

[0032] A further improvement is that the first stripe and the pattern of the front layer overlay mark are perpendicular.

[0033] A further improvement is that the first area is completely located directly below the area where the overlay mark is formed.

[0034] A further improvement is that the first region and the region where the overlay mark is formed are located within a dicing street or within a chip.

[0035] A further improvement is that the maximum size of the formation area of ​​the overlay mark is greater than 30 microns*30 microns.

[0036] Unlike the prior art, in which the bottom layers of the front-layer overlay marks constituting the overlay mark combination structure are all large blank areas, in the present invention, a filler pattern is set in the underlying material layer at the bottom of the front-layer overlay mark, and the pattern density of the existing large blank area and the reflectivity of the material are changed by the filler pattern. The setting of the pattern density of the filler pattern is compatible with the requirements of the plasma etching and chemical mechanical polishing processes for pattern density. Combined with the setting of the width of the line of the filler pattern, i.e., the first bar, it can improve the ability to suppress random noise, which is beneficial to improve the tolerance to flattening of the etching or chemical mechanical polishing process in the process of forming the front-layer overlay mark, and prevent the pattern of the front-layer overlay mark from erosion or wear defects, thereby preventing the reflected light of the overlay mark measurement caused by erosion and wear defects from being disorderly or even asymmetric left and right, thereby preventing the disorder or asymmetry of the reflected light used for measurement from adversely affecting the overlay measurement accuracy.

[0037] The material of the filler pattern of the present invention has a higher reflectivity, so it can prevent the measurement signal from being transmitted through the underlying material layer, thereby preventing the measurement signal from being reduced, that is, increasing the measurement signal, thereby further optimizing the overlay mark signal and improving measurement accuracy.

[0038] In addition, since the size of the filler pattern of the present invention is set independently, the size of the filler pattern can be set relatively small, such as less than 300 nm. In this way, the substrate signal, i.e., the signal of the underlying material layer and the bottom of the underlying material layer, will not be absorbed by the measuring machine, thereby preventing the substrate signal from interfering with the measurement signal, thereby further improving the measurement results.

[0039] Therefore, the present invention can prevent the large area of ​​the bottom of the front layer overlay mark from adversely affecting the overlay mark signal, thereby optimizing the overlay mark signal and improving the accuracy of overlay measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0041] Figure 1 It is a layout of existing overlay marks;

[0042] Figure 2 It is a cross-sectional structural diagram of a front layer overlay mark in an existing overlay mark combination;

[0043] Figure 3 It is a cross-sectional structural diagram of the existing overlay mark combination structure after formation;

[0044] Figure 4 is a flow chart of a method for optimizing an overlay mark signal according to an embodiment of the present invention;

[0045] Figure 5It is a cross-sectional structural diagram of an overlay mark combination structure formed by the method for optimizing overlay mark signals according to an embodiment of the present invention. DETAILED DESCRIPTION

[0046] like Figure 4 FIG. 1 is a flow chart of a method for optimizing an overlay mark signal according to an embodiment of the present invention; FIG. Figure 5 FIG. 1 is a cross-sectional structural diagram of an overlay mark combination structure formed by a method for optimizing an overlay mark signal according to an embodiment of the present invention. The method for optimizing an overlay mark signal according to an embodiment of the present invention includes the following steps:

[0047] Step S101: provide a bottom material layer 403, and form a filler pattern 413 in a first area of ​​the bottom material layer 403. The reflectivity of the filling material of the filler pattern 413 is greater than the reflectivity of the bottom material layer 403. The first area intersects with at least part of the area where the overlay mark is formed. The pattern density of the filler pattern 413 meets the requirements of the plasma etching and chemical mechanical polishing processes for pattern density to ensure that the top surface of the first area is flat. The top surface of the first area includes the top surface of the bottom material layer 403 and the top surface of the filler pattern 413.

[0048] In the embodiment of the present invention, the material of the bottom material layer 403 includes a low dielectric constant material; and the filling material includes metal.

[0049] The filler pattern 413 is formed by densely arranged first bars 414. The size of the first bars 414 meets the requirements of the design rules and is smaller than the minimum wavelength of the signal received by the measurement machine of the overlay mark, so as to ensure that the signal of the underlying material layer 403 will not be absorbed by the measurement machine, thereby avoiding interference with the measurement result of the overlay mark signal.

[0050] The first area is completely located directly below the area where the overlay mark is formed.

[0051] The first region and the overlay mark formation region are located within the dicing street or within the chip. When located within the dicing street, the overlay mark does not occupy the chip area. However, when the chip is large, the dicing street is too small to accommodate sufficient overlay marks. In this case, a portion of the overlay mark can be placed within the chip.

[0052] In some embodiments, the wavelength of the signal received by the overlay mark measuring machine is in the range of 300 nm to 700 nm, and the width of the first stripe 414 is less than 300 nm.

[0053] In some embodiments, the maximum size of the formation area of ​​the overlay mark is greater than 30 micrometers*30 micrometers.

[0054] Figure 5 In the embodiment, an NDC layer 402 and a bottom structure 401 are formed at the bottom of the bottom material layer 403. The bottom structure 401 can include a semiconductor substrate and a multi-layer interlayer film formed on top of the semiconductor substrate.

[0055] Step S102 : forming a front material layer and forming a front layer overlay mark in the overlay mark formation region of the front material layer.

[0056] In an embodiment of the present invention, the material of the front material layer includes a low dielectric constant material. Figure 5 In the figure, the low-k material layer of the front material layer is indicated by reference numeral 405. A nitrogen-doped silicon carbide (NDC) layer 404 is formed at the bottom of the low-k material layer 405 to prevent the bottom metal layer from adversely affecting the low-k layer 405. An NDC layer 406 and an NFDARC layer 407 are formed on top of the low-k layer 405. NFDARC stands for fluorine-free DARC.

[0057] The front material layer is used to form through holes or metal lines.

[0058] The front layer overlay mark and through hole pattern are defined simultaneously.

[0059] In an embodiment of the present invention, a metal hard mask layer is formed on the top surface or within the front material layer, and the front overlay mark is formed by the patterned metal hard mask layer. In other embodiments, the front overlay mark may be formed by a through hole in the overlay mark formation area.

[0060] The metal hard mask layer includes a TiN layer 408 and an oxide layer 409 formed on top of the TiN layer 408 . Figure 5 The structure of the formation area of ​​the overlay mark is shown in FIG. 1 . No chip structure is formed in the formation area of ​​the overlay mark, so the through hole pattern is not shown. Figure 5 It can be seen that the TiN layer 408 and the oxide layer 409 of the metal hard mask layer have been patterned, and these patterned structures serve as the front layer overlay marks.

[0061] In embodiments of the present invention, the first stripe 414 and the pattern of the front-layer overlay mark can be at any angle, and the measurement signal can be optimized when the first stripe 414 is provided. In some preferred embodiments, the first stripe 414 and the pattern of the front-layer overlay mark are perpendicular, which can achieve optimal optimization of the measurement signal.

[0062] Step S103, forming a current layer material layer and forming a current layer overlay mark in the formation area of ​​the overlay mark of the current layer material layer; the front layer overlay mark and the current layer overlay mark form an overlay mark combination structure, and the flat structure of the top surface of the first area and the high reflectivity of the filling material are used to improve the overlay mark signal.

[0063] In the embodiment of the present invention, the current material layer includes photoresist 412 .

[0064] The layer material layer also includes a SOC layer 410 and a silicon bottom anti-reflective coating 411. The layer overlay mark and the metal line pattern are defined at the same time. Figure 5 Only the formation area of ​​the overlay mark is shown, and the chip structure is not shown, so the metal line pattern is not shown.

[0065] The current layer overlay mark is composed of the patterned current layer material layer. Figure 5 In the embodiment, the photoresist 412 of the current material layer is patterned, and the current layer overlay mark is composed of the patterned photoresist 412.

[0066] In an embodiment of the present invention, the metal material of the filling material, the through hole and the metal wire is the same.

[0067] The metal material of the filling material includes copper.

[0068] In some embodiments, the through hole and the metal line on the top layer are formed simultaneously using a dual damascene process.

[0069] Unlike the prior art, in which the bottom layers of the front-layer overlay marks constituting the overlay mark combination structure are all large blank areas, in the embodiment of the present invention, a filler pattern 413 is provided in the underlying material layer 403 at the bottom of the front-layer overlay mark. The filler pattern 413 is used to change the pattern density of the existing large blank area and the reflectivity of the material. The setting of the pattern density of the filler pattern 413 is compatible with the requirements of the plasma etching and chemical mechanical polishing processes for pattern density. Combined with the setting of the width of the line of the filler pattern 413, i.e., the first bar 414, the ability to suppress random noise can be improved, which is beneficial to improving the tolerance to flattening of the etching or chemical mechanical polishing process in the process of forming the front-layer overlay mark, preventing the pattern of the front-layer overlay mark from erosion or wear defects, thereby preventing the reflected light of the overlay mark measurement caused by erosion and wear defects from being disordered or even asymmetric, thereby preventing the disorder or asymmetry of the reflected light used for measurement from adversely affecting the overlay measurement accuracy.

[0070] The material of the filler pattern 413 of the embodiment of the present invention has a higher reflectivity, so it can prevent the measurement signal from being transmitted through the underlying material layer 403, thereby preventing the measurement signal from being reduced, that is, increasing the measurement signal, thereby further optimizing the overlay mark signal and improving measurement accuracy.

[0071] In addition, since the size of the filler pattern 413 in the embodiment of the present invention is independently set, the size of the filler pattern 413 can be set relatively small, such as less than 300 nm. In this way, the substrate signal, i.e., the signal of the underlying material layer 403 and the bottom of the underlying material layer 403, will not be absorbed by the measurement machine, thereby preventing the substrate signal from interfering with the measurement signal, thereby further improving the measurement result.

[0072] Therefore, the embodiment of the present invention can prevent the large area at the bottom of the front layer overlay mark from adversely affecting the overlay mark signal, thereby optimizing the overlay mark signal and improving the accuracy of overlay measurement.

[0073] The Damascus process results in large areas of unevenness and even left-right asymmetry, which leads to deviations in overlay measurement. In order to improve the asymmetry of overlay marks in large areas introduced in the process, a filler substrate is added to the front layer in the embodiment of the present invention. The bottom layer of the front layer is a low-dielectric constant material. In order to improve the reflectivity of the bottom layer, a dense line pattern is used in the front layer lithography to replace the original photoresist-completely covered area. The original photoresist-completely covered area is a blank area, which is subsequently etched, filled with copper and polished to form a blank area. Figure 5 The filler pattern 413 in the image is densely packed with lines that are compatible with the pattern density requirements of many plasma etching and chemical mechanical planarization processes. By improving the filler line width, random noise suppression is improved, while also enhancing its resistance to etching and chemical mechanical planarization. The filler design utilizes minimum specifications, meeting the minimum design dimensions and remaining close to chip specifications. With a pattern width less than 300nm, the substrate signal is not absorbed by the measurement equipment, and therefore, designs smaller than 300nm do not interfere with measurement signals.

[0074] Using ASML D4C (design for control) analog signal to add filler Figure 5 The contrast signal of the filler pattern 413 shown, for example, shows how the signal strength (SS) of the fourth-layer via (Via4) to the fifth-layer metal line (M5) varies with wavelength. It can be seen that inserting dense lines or a DBO-style filler significantly increases the SS. When the first stripe 414 is perpendicular to the pattern of the previous-layer overlay mark, the corresponding SS increases from 0.2 to approximately 1.0, and the wavelength also varies significantly. A larger SS indicates greater measurement sensitivity, so inserting fillers can improve detection sensitivity in the via layer.

[0075] The SS measurement on the product's V4 (Via4) is affected by different wavelengths. Combining actual measurement data with analysis of other important parameters shows that the 90-degree polarization measurement condition is more advantageous. Its SS increases from the original 0.2 to 0.8, and the wavelength also fluctuates slightly, but the SS shows obvious peaks and troughs, which means it is more sensitive to detection.

[0076] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A method for optimizing an overlay mark signal, characterized in that: Including steps: Providing an underlying material layer, forming a filler pattern in a first region of the underlying material layer, wherein the reflectivity of the filler material of the filler pattern is greater than the reflectivity of the underlying material layer, and the first region and at least a portion of the region where the overlay mark is formed intersect; the pattern density of the filler pattern meets the pattern density requirements of plasma etching and chemical mechanical polishing processes to ensure that the top surface of the first region is flat, and the top surface of the first region includes the top surface of the underlying material layer and the top surface of the filler pattern; forming a front material layer and forming a front layer overlay mark in the overlay mark formation region of the front material layer; forming a current material layer and forming a current overlay mark in a formation region of the overlay mark of the current material layer; The front layer overlay mark and the current layer overlay mark form an overlay mark combination structure, and the flat structure of the top surface of the first region and the high reflectivity of the filling material are used to improve the overlay mark signal.

2. The method for optimizing an overlay mark signal according to claim 1, wherein: The material of the bottom material layer includes a low dielectric constant material; and the filling material includes metal.

3. The method for optimizing an overlay mark signal according to claim 2, wherein: The material of the front material layer includes a low dielectric constant material, and the front material layer is used to form a through hole or a metal line; The front layer overlay mark and through hole pattern are defined simultaneously.

4. The method for optimizing an overlay mark signal according to claim 3, wherein: A metal hard mask layer is formed on the top surface or inside of the front material layer, and the front overlay mark is composed of the patterned metal hard mask layer or the front overlay mark is composed of a through hole in the overlay mark formation area.

5. The method for optimizing an overlay mark signal according to claim 4, wherein: The material of the metal hard mask layer includes TiN.

6. The method for optimizing an overlay mark signal according to claim 4, wherein: The layer material layer includes photoresist, and the layer overlay mark and metal line pattern are defined simultaneously; The current layer overlay mark is composed of the patterned current layer material layer.

7. The method for optimizing an overlay mark signal according to claim 6, wherein: The current material layer further includes a SOC layer and a silicon bottom anti-reflection coating layer.

8. The method for optimizing an overlay mark signal according to claim 6, wherein: The filling material, the through hole and the metal line are made of the same metal material.

9. The method for optimizing an overlay mark signal according to claim 8, wherein: The metal material of the filling material includes copper.

10. The method for optimizing an overlay mark signal according to claim 1, wherein: The filler pattern is formed by densely arranged first bars, the size of which meets the requirements of the design rules and is smaller than the minimum wavelength of the signal received by the measuring machine of the overlay mark, so as to ensure that the signal of the underlying material layer will not be absorbed by the measuring machine, thereby avoiding interference with the measurement result of the overlay mark signal.

11. The method for optimizing an overlay mark signal according to claim 10, wherein: The wavelength range of the signal received by the overlay mark measuring machine is 300nm to 700nm, and the width of the first stripe is less than 300nm.

12. The method for optimizing an overlay mark signal according to claim 10, wherein: The first stripe is perpendicular to the pattern of the front layer overlay mark.

13. The method for optimizing an overlay mark signal according to claim 1, wherein: The first area is completely located directly below the area where the overlay mark is formed.

14. The method for optimizing an overlay mark signal according to claim 13, wherein: The first region and the region where the overlay mark is formed are located within a dicing street or within a chip.

15. The method for optimizing an overlay mark signal according to claim 14, wherein: The maximum value of the formation area of ​​the overlay mark is 30 micrometers*30 micrometers or more.

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