A method, device and electronic device for processing locked-step faults

Abstract

An embodiment of the present application provides a method, device, and electronic device for handling lockstep faults, belonging to the technical field of processors. The method includes: during the process of the first core and the second core of the processor running the same application program, establishing a first checkpoint; obtaining a first operation result of the first core at the currently established first checkpoint and a second operation result of the second core at the first checkpoint; selecting a target core that needs to be rolled back from the first core and the second core according to the historical operation information of the first core and the historical operation information of the second core; and rolling back the target core when the first operation result is inconsistent with the second operation result. Therefore, the embodiment of the present application can, to a certain extent, solve the problem in the existing dual-core lockstep security architecture that when the operation results of the main core and the check core are inconsistent, the states of both cores are rolled back, resulting in the loss of the work progress of the processor core with the correct working state and a large recovery cost.

Description

Technical Field

[0001] This application relates to the technical field of processors, and in particular, to a lockstep fault handling method, apparatus, and electronic device. Background Art

[0002] With the development of modern integrated circuit technology, the reduction of the critical dimension of integrated circuits increases the probability of single event upsets (SEUs) in chips caused by cosmic rays. The reliability enhancement of processors has become an important research direction in the field of integrated circuits.

[0003] Currently, the main direction for enhancing the reliability of multi-core processors relies on resource redundancy. Among them, dual-core lockstep (DCLS) is a highly reliable security architecture. By configuring two identical processor cores in parallel, namely the main core and the check core, the main core and the check core independently execute the same instruction set, and then detect the error states caused by single event events in the chip by comparing the output results of the main core and the check core.

[0004] Currently, in the security architecture of dual-core lockstep, the main core and the check core need to execute the application program synchronously. When the results are inconsistent, the states of both cores need to be rolled back, which loses the progress of the processor core with the correct working state, and the cost of recovery is relatively high. Summary of the Invention

[0005] Embodiments of this application provide a lockstep fault handling method, apparatus, and electronic device to solve, to a certain extent, the problem in the existing dual-core lockstep security architecture that when the running results of the main core and the check core are inconsistent, the states of both cores are rolled back, resulting in the loss of the progress of the processor core with the correct working state and a relatively high recovery cost.

[0006] In a first aspect, embodiments of this application provide a lockstep fault handling method, including:

[0007] During the process of the first core and the second core of the processor running the same application program, establish a first checkpoint;

[0008] Obtain the first running result of the first core at the currently established first checkpoint and the second running result of the second core at the first checkpoint;

[0009] According to the historical running information of the first core and the historical running information of the second core, select the target core that needs to be rolled back among the first core and the second core;

[0010] In the case where the first running result is inconsistent with the second running result, roll back the target core.

[0011] In a second aspect, an embodiment of the present application provides a lockstep fault handling device, which includes:

[0012] A checkpoint establishment module, configured to establish a first checkpoint during the process of the first core and the second core of the processor running the same application program;

[0013] An acquisition module, configured to acquire a first operation result of the first checkpoint currently established by the first core, and a second operation result of the second core at the first checkpoint;

[0014] A selection module, configured to select a target core to be rolled back from the first core and the second core according to the historical operation information of the first core and the historical operation information of the second core;

[0015] A rollback module, configured to roll back the target core when the first operation result is inconsistent with the second operation result.

[0016] In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete communication with each other through the communication bus;

[0017] The memory is used to store a computer program;

[0018] The processor is configured to implement the steps in the above lockstep fault handling method when executing the program stored on the memory.

[0019] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above lockstep fault handling method are implemented.

[0020] The embodiments of the present application at least include the following technical effects:

[0021] The technical solution of the embodiment of the present application can establish a first checkpoint during the process of the first core and the second core of the processor running the same application program, and obtain the first running result of the first core at the first checkpoint established currently, and the second running result of the second core at the first checkpoint. According to the historical running information of the first core and the historical running information of the second core, the target core to be rolled back is selected from the first core and the second core, so as to roll back the target core in the case where the first running result and the second running result are inconsistent. It can be seen that in the embodiment of the present application, the core that goes wrong can be more likely to be identified according to the historical running information of the two cores of the processor. Therefore, when the running results of the two cores are inconsistent at the first checkpoint established currently, the core that may go wrong can be rolled back. In this way, the execution progress of the core with the correct working state can be retained as much as possible, and the performance loss caused by the dual-core rollback after a failure can be reduced. Therefore, the embodiment of the present application can, to a certain extent, solve the problem in the existing security architecture of dual-core lockstep that when the running results of the main core and the check core are inconsistent, the states of the two cores are rolled back, resulting in the loss of the working progress of the processor core with the correct working state and a large recovery cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for description in the embodiments or the prior art.

[0023] Figure 1 is a schematic flowchart of a lockstep fault handling method provided by an embodiment of the present application;

[0024] Figure 2 is a block diagram of a lockstep fault handling system in the specific embodiment of the present application;

[0025] Figure 3 is a schematic diagram of the order of swapping out pages of processor core A and processor core R in the specific embodiment of the present application;

[0026] Figure 4 is a block diagram of a lockstep fault handling device provided by an embodiment of the present application;

[0027] Figure 5 is a block diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments in the present application belong to the scope of protection of the present application.

[0029] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, the "in one embodiment" or "in an embodiment" that appears throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner.

[0030] In various embodiments of the present application, it should be understood that the magnitude of the serial numbers of the following processes does not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0031] In a first aspect, referring to Figure 1 , a step flowchart of a lockstep fault handling method in an embodiment of the present application is shown. The method may include the following steps 101 to 104:

[0032] Step 101: Establish a first checkpoint during the process of running the same application program on the first core and the second core of the processor.

[0033] Wherein, the first core and the second core are two cores of the processor. In the embodiments of the present application, a first checkpoint is established during the process of running the same application program on these two cores. For example, during the process of running the same application program on the first core and the second core, when it is detected that the first core and the second core swap out the pages with the same serial number of the application program, a first checkpoint corresponding to the page is established. It should be noted that the serial number refers to the serial number of the sorted swapped-out pages of the application program.

[0034] That is, it can be understood that the first checkpoint refers to the point at which one of the first core and the second core is about to compare the running result at the same position with the other core when executing the application program to a certain position.

[0035] Optionally, in step 101, establishing a first checkpoint during the process of running the same application program on the first core and the second core of the processor includes:

[0036] During the process of running the same application program on the first core and the second core with a first time difference, when it is monitored that both the first core and the second core have swapped out the pages with the same first serial number of the application program, establish a first checkpoint corresponding to the pages with the first serial number.

[0037] In some embodiments, the first core and the second core may run the same application program with a certain time difference, that is, the two cores are allowed to asynchronously execute the same application program, so as to reduce the impact of instantaneous pulses and further reduce the common mode failure probability.

[0038] It should be noted that when the first core and the second core run the same application program simultaneously (or synchronously), if the processor is affected by an interference event in a certain state at a certain time, then at this time, both the first core and the second core will be affected simultaneously. The running results caused by the interference may be the same, so it is impossible to detect whether there is a fault. In the embodiments of the present application, the first core and the second core asynchronously execute the same application program, so that the influence of the interference event on the first core and the second core can be staggered, thereby reducing the common mode failure probability.

[0039] Wherein, the interference event refers to an event that may cause system failure in terms of force, heat, electricity, etc., such as a single particle event.

[0040] Step 102: Obtain the first running result of the first core at the first checkpoint established currently, and the second running result of the second core at the first checkpoint.

[0041] Wherein, the running result of the core at the first checkpoint may include the page content of the page corresponding to the first checkpoint swapped out by the core, and the context state when the core swaps out the page corresponding to the first checkpoint.

[0042] It should be noted that the context state refers to a key set of hardware required for the core of the processor to run tasks, and may include the following core components: a register set (including general-purpose registers, floating-point registers, status registers, used to store intermediate operation results and control flags), a program counter, a stack pointer, etc.

[0043] Step 103: Select a target core to be rolled back from the first core and the second core according to the historical running information of the first core and the historical running information of the second core.

[0044] Among them, selecting a target core to be rolled back from the first core and the second core according to the historical running information of the first core and the historical running information of the second core can be understood as: selecting a core that may go wrong (or the probability of going wrong is greater than a third threshold) from the first core and the second core according to the historical running information of the first core and the historical running information of the second core. That is, the target core can be understood as: a core that may go wrong (or the probability of going wrong is greater than a third threshold) among the first core and the second core.

[0045] In addition, it should be noted that for the process of comparing the first running result and the second running result and the process of step 103, the embodiments of the present application do not limit the sequence of these two processes.

[0046] For example, in some embodiments, the target core to be rolled back can be selected from the first core and the second core according to the historical running information of the first core and the historical running information of the second core; thus, when it is determined that the first running result is inconsistent with the second running result after comparing the first running result and the second running result, the most recently selected target core is used.

[0047] Or, for example, in some embodiments, after comparing the first running result and the second running result and determining that the first running result is inconsistent with the second running result, the target core to be rolled back can be selected from the first core and the second core according to the historical running information of the first core and the historical running information of the second core.

[0048] In addition, the historical running information of the core represents the running situation of the core in the past period of time, and the running situation of the core in the past period of time can represent the error situation of the core, so that it can be known whether the core belongs to the core with a relatively high error probability.

[0049] Step 104: Roll back the target core in the case where the first running result is inconsistent with the second running result.

[0050] Among them, the first running result may include: the first page content of the first core swapping out the page corresponding to the first checkpoint, and the first context state when the first core swaps out the page corresponding to the first checkpoint; the second running result may include: the second page content of the second core swapping out the page corresponding to the first checkpoint, and the second context state when the second core swaps out the page corresponding to the first checkpoint;

[0051] Correspondingly, if the first page content is consistent with the second page content and the first context state is consistent with the second context state, it means that the first running result is consistent with the second running result;

[0052] If the first page content is inconsistent with the second page content or the first context state is inconsistent with the second context state, it means that the first running result is inconsistent with the second running result.

[0053] As can be seen from the above steps 101 to 104, in the embodiment of the present application, during the process of running the same application program on the first core and the second core of the processor, a first checkpoint can be established, and the first running result of the first core at the currently established first checkpoint can be obtained, as well as the second running result of the second core at the first checkpoint. According to the historical running information of the first core and the historical running information of the second core, the target core to be rolled back is selected from the first core and the second core, so that when the first running result and the second running result are inconsistent, the target core is rolled back. It can be seen that in the embodiment of the present application, the core that goes wrong can be more likely identified according to the historical running information of the two cores of the processor. Thus, when the running results of the two cores are inconsistent at the currently established first checkpoint, the core that may go wrong can be rolled back. In this way, the execution progress of the core with the correct working state can be retained as much as possible, and the performance loss caused by the dual-core rollback after a failure can be reduced. Therefore, the embodiment of the present application can, to a certain extent, solve the problem in the existing secure architecture of dual-core lockstep that when the running results of the main core and the check core are inconsistent, the states of the two cores are rolled back, resulting in the loss of the working progress of the processor core with the correct working state and a large recovery cost.

[0054] In some embodiments of the present application, the method further includes the following step A-1:

[0055] Step A-1: During the process of running the same application program on the first core and the second core, record the page addresses of the pages swapped out by the first core and the second core, and the context states when the first core and the second core swap out the pages.

[0056] In the above step 102, obtaining the first running result of the first core at the currently established first checkpoint and the second running result of the second core at the first checkpoint includes the following steps B-1 to B-2:

[0057] Step B-1: According to the recorded page address of the page swapped out by the first core corresponding to the first checkpoint, obtain the first page content of the page swapped out by the first core corresponding to the first checkpoint, and determine the first page content and the first context state when the first core swapped out the page corresponding to the first checkpoint as the first running result.

[0058] Step B-2: According to the recorded page address of the page swapped out by the second core corresponding to the first checkpoint, obtain the second page content of the page swapped out by the second core corresponding to the first checkpoint, and determine the second page content and the second context state when the second core swapped out the page corresponding to the first checkpoint as the second running result.

[0059] As can be seen from the above step A-1, in some embodiments, during the process of running the same application program on the first core and the second core, when the first core swaps out a page, the page address of the page swapped out by the first core and the context state at this time are recorded; similarly, when the second core swaps out a page, the page address of the page swapped out by the second core and the context state at this time are recorded.

[0060] Optionally, the page address of the page swapped out by the first core and the corresponding context state can be stored in the cache unit corresponding to the first core; the page address of the page swapped out by the second core and the corresponding context state can be stored in the cache unit corresponding to the second core.

[0061] Among them, through the above step A-1, the page addresses of the pages swapped out by the first core and the second core can be recorded, and based on the page addresses, the corresponding page content can be obtained. In this way, the first running result of the first core at the first checkpoint (that is, the first page content of the page corresponding to the first checkpoint swapped out by the first core, and the first context state when the first core swaps out the page corresponding to the first checkpoint) and the second running result of the second core at the first checkpoint (that is, the second page content of the page corresponding to the first checkpoint swapped out by the second core, and the second context state when the second core swaps out the page corresponding to the first checkpoint) can be obtained.

[0062] It should be noted that in the case where the first core and the second core run the same application program with a first time difference (that is, the first core and the second core execute the same application program asynchronously), the progress of the two cores is different. Then, if it is necessary to establish the first checkpoint corresponding to the page when it is monitored that both the first core and the second core have swapped out the pages with the same serial number of the application program, it is necessary to record the page address of the page and the corresponding context state when each core swaps out the page, so as to match the pages with the same serial number swapped out by the two cores in the application program. Thus, when establishing the first checkpoint, the running results corresponding to the currently matched page can be extracted, and then the running results can be compared to determine whether there is a fault.

[0063] In some embodiments of the present application, the method further includes the following steps C-1 to C-2:

[0064] Step C-1: When the absolute value of the difference between the first result quantity of the pages swapped out by the first core and the second result quantity of the pages swapped out by the second core is equal to the first threshold, pause the core to which the larger one of the first result quantity and the second result quantity belongs;

[0065] Step C-2: When the first running result is consistent with the second running result and there is a paused core, resume the operation of the paused core.

[0066] It should be noted that when the space of the cache unit for storing the page addresses and corresponding context states of the pages swapped out by the first core and the second core is limited. For example, after the first cache unit for storing the page addresses and corresponding context states of the pages swapped out by the first core is full, if the page addresses and corresponding context states of the pages swapped out by the first core subsequently overwrite the earliest record in the first cache unit, then there will be a situation where the overwritten record has not been used for comparing the running results but is overwritten.

[0067] In some embodiments of the present application, the progress of the two cores can be controlled by monitoring the number of pages swapped out by the two cores. That is, when the progress of the two cores differs greatly, the faster one can be paused to prevent the cache unit of the faster one from being filled too early. Therefore, through the above steps C-1 and C-2, the situation of "the overwritten record has not been used for comparing the running results but is overwritten" can be avoided.

[0068] In some embodiments of the present application, the method further includes:

[0069] When the first running result is consistent with the second running result, delete the page addresses of the recorded first page content, the first context state, the page addresses of the second page content, and the second context state.

[0070] It can be seen that in some embodiments, the records corresponding to the running results with consistent comparison (i.e., page addresses and context states) can also be deleted, so as to make room for the records of newly swapped out pages.

[0071] It should be noted that when the first cache unit (i.e., the cache unit for storing the page addresses and corresponding context states of the pages swapped out by the first core) adopts the form of a first circular queue, and the second cache unit (i.e., the cache unit for storing the page addresses and corresponding context states of the pages swapped out by the second core) adopts the form of a second circular queue, since the first circular queue and the second circular queue can store new records in a covering manner, when the first running result is consistent with the second running result, it is not necessary to delete the page addresses of the recorded first page content and the first context state in the first circular queue, nor to delete the page addresses of the recorded second page content and the second context state in the second circular queue.

[0072] Optionally, the storage spaces of the first cache unit and the second cache unit are the same, and the first threshold is equal to the size of the storage space of the first cache unit or the second cache unit. That is, in some embodiments, the progress difference between the two cores can be adjusted through the above steps C-1 and C-2 so that the progress difference does not exceed the size of the storage space of the cache unit.

[0073] Exemplarily, when the first cache unit adopts the form of a first circular queue and the second cache unit adopts the form of a second circular queue, the depths of the first circular queue and the second circular queue are the same, and the first threshold is equal to the depth of the first circular queue or the second circular queue. That is, in some embodiments, the progress difference between the two cores can be adjusted through the above steps C-1 and C-2 so that the progress difference does not exceed the depth of the circular queue.

[0074] In some embodiments of the present application, the method further includes the following step D-1:

[0075] Step D-1: When the first operation result is inconsistent with the second operation result (that is, the first page content is inconsistent with the second page content, or the first context state is inconsistent with the second context state), delete the page address and the corresponding context state of the page with the second serial number that have been recorded;

[0076] Wherein, the second serial number includes: the serial number of the page corresponding to the first checkpoint to the serial number of the page that the target core most recently swapped out when establishing the first checkpoint.

[0077] For example, if the serial number of the page corresponding to the first checkpoint is 02, and when establishing the first checkpoint, the target core has swapped out to the page with the serial number 05. Then, if the page content of the page with the serial number 02 swapped out by the first core is inconsistent with the page content of the page with the serial number 02 swapped out by the second core, or the context state when the first core swapped out the page with the serial number 02 is inconsistent with the context state when the second core swapped out the page with the serial number 02, it means that an error occurred after the page with the serial number 01 for the target core, that is, the page addresses and the corresponding context states of the pages with the serial numbers 02 to 05 swapped out by the target core are all invalid and can be deleted.

[0078] In some embodiments of the present application, the historical operation information includes at least one of the following: historical rollback information, historical jump address exception information, and historical page swap-out frequency information.

[0079] Among them, the historical rollback information indicates the situation where the core was rolled back during historical operation;

[0080] The historical jump address exception information represents the characteristic information of the code executed during the historical operation of the core, such as whether there is a jump address and the relevant information of the code segment associated with the jump address;

[0081] The historical page eviction frequency information represents the magnitude of the frequency of page eviction by the core during historical operation.

[0082] In some embodiments of the present application, in step 103 above, according to the historical operation information of the first core and the historical operation information of the second core, selecting the target core that needs to be rolled back between the first core and the second core includes the following steps E-1:

[0083] Step E-1: Select the core that meets the first condition as the target core between the first core and the second core;

[0084] Wherein, the first condition includes at least one of the following F-1 to F-3:

[0085] Item F-1: The historical rollback information indicates that it has not been rolled back within the first time period;

[0086] Among them, the core that has been recently rolled back is more likely to be in a safe state. Therefore, if the historical rollback information of a certain core among the first core and the second core indicates that it has been rolled back within the first time period, it means that this core is more likely to be in a safe state; on the contrary, if it indicates that it has not been rolled back within the first time period, it means that this core is more likely to have problems.

[0087] In addition, the first time period can be understood as: the fault-free execution time of the core.

[0088] Item F-2: The historical jump address exception information indicates that there is a jump address in the executed code, and the code segment associated with the jump address does not have access permission in the application program;

[0089] Among them, if there is a jump address in the code executed by a core, but the code segment associated with the jump address does not have access permission in the application program run by this core, it means that this core is more likely to have problems.

[0090] Item F-3: The historical page eviction frequency information indicates that the frequency of page eviction within the second time period is greater than the second threshold.

[0091] Among them, if the frequency of page eviction of a core within the second time period is greater than the second threshold, it means that the frequency of page eviction of this core within the second time period is too high, which belongs to an abnormal situation, indicating that this core is more likely to have problems.

[0092] In addition, the second time period can be understood as a time window for recording page swapping out.

[0093] Therefore, if a core meets at least one of the above F-1 to F-3, it indicates that the core is more likely to be a faulty core, that is, a core that needs to be rolled back.

[0094] In some embodiments of the present application, in the above step 103, according to the historical operation information of the first core and the historical operation information of the second core, selecting a target core to be rolled back from the first core and the second core includes the following steps H-1:

[0095] Step H-1: In the case of not receiving the first signal, select the target core from the first core and the second core according to the historical operation information of the first core and the historical operation information of the second core;

[0096] Wherein, the first signal is used to indicate the core to be rolled back.

[0097] In some embodiments of the present application, the method further includes the following steps H-2:

[0098] Step H-2: In the case of receiving the first signal, select the target core from the first core and the second core according to the indication of the first signal.

[0099] Wherein, the first signal can be input by an external system, for example, sent by the host computer of the processor. That is, the first signal can be understood as an external signal.

[0100] It can be seen from steps H-1 and H-2 that the external system (such as the host computer) can indicate the processor which core in the first core and the second core to roll back; if the external system does not indicate the processor which core to roll back to, the target core to be rolled back can be selected from the first core and the second core according to the historical operation information of the first core and the historical operation information of the second core.

[0101] In some embodiments of the present application, in the above step 104, rolling back the target core includes the following steps L-1:

[0102] Step L-1: According to the recorded operation result of the first core or the second core at the second checkpoint, roll back the target core to the nearest second checkpoint.

[0103] Wherein, the second checkpoint includes: a checkpoint where the operation result of the first core is consistent with the operation result of the second core; that is, the operation result of the first core at the second checkpoint is consistent with the operation result of the second core at the second checkpoint.

[0104] It should be noted that the first checkpoint refers to a checkpoint where the running result needs to be subjected to consistency detection or a checkpoint where the consistency detection of the running result is being performed; after the consistency detection of the running result is performed at the first checkpoint, if the detection passes (i.e., the running results of the first core and the second core are the same at the first checkpoint), then this first checkpoint becomes the second checkpoint.

[0105] From this, it can be seen that during the process of the first core and the second core running the same application program, after each comparison of the running results, the running results corresponding to the second checkpoint with consistent comparison can be sequentially recorded (for example, recorded in the order of the page numbers). In this way, when rolling back the target core, the target core can be rolled back to the nearest second checkpoint based on this record.

[0106] Optionally, the method further includes:

[0107] When the first running result is the same as the second running result, store the first running result or the second running result in the storage unit of single-particle immunity.

[0108] It can be seen that in some embodiments, every time a running result with consistent comparison is obtained, the running result with consistent comparison can be stored in the storage unit of single-particle immunity, that is, the stored content in the storage unit of single-particle immunity is updated.

[0109] That is, the running result corresponding to the second checkpoint with consistent comparison can be stored in the storage unit of single-particle immunity to reduce the probability that the result with consistent comparison is affected by a single-particle event.

[0110] In addition, step L-1 may specifically include: setting the memory page of the target core to an invalid state, and overwriting the memory space of the target core with the running result of the first core or the second core recorded at the second checkpoint.

[0111] In some embodiments of the present application, the method further includes the following steps K-1 to K-2:

[0112] Step K-1: When the first running result is the same as the second running result, reset the system timer;

[0113] Step K-2: When the system timer times out, instruct the first core and the second core to re-run the application program.

[0114] It can be seen that when the comparison results of the running results are consistent, the system timer is reset once. If, after a certain reset of the system timer, until the system timer times out, a consistent comparison result of the running results (i.e., the second checkpoint is not obtained) is still not obtained, then a restart is required, that is, the first core and the second core need to run the same application again. That is, it can be understood that if the program execution progress cannot be advanced by the recovery method of rolling back to the nearest second checkpoint, the entire system can be restarted.

[0115] It can be seen that in some embodiments, if the system timer is not reset for a long time, that is, the second checkpoint is not obtained for a long time (i.e., a consistent comparison result of the running results is not obtained for a long time), an exception will be caused by the overflow of the system timer, and the entire system will be restarted. Among them, the system timer overflow event can be recorded in the log so that the user can view the restart reason based on the log record.

[0116] In some embodiments of the present application, the method further includes the following step P-1:

[0117] Step P-1: When establishing the first checkpoint, mark the page corresponding to the established first checkpoint as read-only.

[0118] Among them, when establishing the first checkpoint, it is necessary to compare the running results (that is, compare the page content and the corresponding context state of the page corresponding to the first checkpoint swapped out by the first core, and the page content and the corresponding context state of the page corresponding to the first checkpoint swapped out by the second core); when establishing the first checkpoint, marking the page corresponding to the first checkpoint as read-only can avoid the page being modified during the comparison of the running results, thereby causing inaccurate comparison results.

[0119] In some embodiments of the present application, the method is applied to a programmable logic terminal, and the programmable logic terminal is arranged outside the processor; in this way, the establishment of the first checkpoint is completed by the programmable logic terminal outside the processor, so there is no need to freeze the memory and it does not affect the continuous execution of the processor, and the performance loss of the processor is smaller.

[0120] In summary, the specific implementation of the lockstep fault handling method in the embodiments of the present application can be described as follows:

[0121] Among them, the lockstep fault handling method can be applied to a Figure 2 lockstep fault handling system as shown. The system includes a processor and a programmable logic terminal. Among them, the processor includes processor core A and processor core R; the programmable logic terminal includes: a result monitoring unit, a cache unit of processor core A, a cache unit of processor core R, a result comparison unit, a single-event immune storage unit, a fault detection unit, and a system timer.

[0122] Two cores of the processor execute the same application program at uncertain time intervals. Inside the operating system, a suspension interrupt handler for processor core A, a fallback interrupt handler for processor core A, a suspension interrupt handler for processor core R, and a fallback interrupt handler for processor core R are defined.

[0123] The following specifically introduces the specific process of the lockstep fault handling system executing the lockstep fault handling method:

[0124] (1) Monitoring: During the asynchronous execution of the same application program by processor core A and processor core R, the result monitoring unit monitors the page replacement events of processor core A and processor core R through the debug interface. Among them, when it is monitored that processor core A replaces a page, the page information of the page replaced by processor core A (including the belonging application, page number, page address, and the context state at this time) is stored in the cache unit of processor core A; when it is monitored that processor core R replaces a page, the page information of the page replaced by processor core R (including the belonging application, page number, page address, and the context state at this time) is stored in the cache unit of processor core R.

[0125] It should be noted that the cache unit stores the page information of each page in the order of page replacement (i.e., the order of page numbers).

[0126] (2) Progress monitoring and suspension: The result comparison unit determines that the difference in the number of page replacements between processor core A and processor core R is not greater than the first threshold based on the number of page information records in the cache unit corresponding to processor core A and the number of page information records in the cache unit corresponding to processor core R. When the difference is equal to the first threshold, a suspension interrupt signal is sent to the processor core with a faster progress among processor core A and processor core R to suspend this processor core.

[0127] Among them, after the processor core is suspended, it polls and waits for a continue execution signal.

[0128] (3) Establishing the first checkpoint: When pages with the same execution order (that is, pages with the same replacement order label, i.e., pages with the same page number) are all replaced, the result comparison unit establishes the first checkpoint corresponding to this page. Among them, since establishing the first checkpoint only requires the processor memory to perform read operations and does not damage the execution states of the two processor cores, the performance loss is reduced.

[0129] Among them, if a first checkpoint corresponding to a page is established, the result comparison unit reads the page address and context state of the page from the cache unit of processor core A, and reads the page address and context state of the page from the cache unit of processor core R, so as to obtain the corresponding page content based on the read page address, and then compare whether the page content of processor core A is consistent with the page content of processor core R, and compare whether the context state of processor core A is consistent with the context state of processor core R; if the page content of processor core A is consistent with the page content of processor core R, and the context state of processor core A is consistent with the context state of processor core R, it means that the running results of processor core A and processor core R at the currently established first checkpoint are consistent; if the page content of processor core A is inconsistent with the page content of processor core R, or the context state of processor core A is inconsistent with the context state of processor core R, it means that the running results of processor core A and processor core R at the currently established first checkpoint are inconsistent, and the target core with a higher error probability needs to be rolled back.

[0130] It should be noted that when establishing the first checkpoint, the page swapped out can be marked as read-only to avoid inaccurate comparison caused by page modification when comparing the page content corresponding to the first checkpoint; after the comparison is completed, the read-only state mark can be removed to continue executing the subsequent program.

[0131] In the first aspect, if the running results of processor core A and processor core R at the currently established first checkpoint are inconsistent, it means that the processor execution is affected by an interference event (such as a single particle event) and an error occurs, and the result comparison unit sends a rollback signal to the processor.

[0132] Among them, the fault detection unit may have a first port 201, a second port 202, and a third port 203. The signal of the first port 201 represents an external enable signal, the signal of the second port 202 represents a signal to roll back processor core A, and the signal of the third port 203 represents a signal to roll back processor core R. Among them, these three ports can be controlled by the host computer, that is, the host computer can input the processor core to be rolled back to the fault detection unit. For example, when the signal of the first port 201 is at a high level, the second signal sent by the fault detection unit to indicate the processor core to be rolled back is determined by the signals of the second port 202 and the third port 203 (that is, the host computer determines which processor core to roll back); when the signal of the first port 201 is at a low level, the second signal sent by the fault detection unit to indicate the processor core to be rolled back is determined according to the historical running information of processor core A and processor core R (that is, which processor core to roll back is selected according to the historical running information of processor core A and processor core R).

[0133] It should be noted that the fault detection unit can periodically select the processor core that needs to be rolled back according to the historical operation information of processor core A and processor core R (including at least one of historical rollback information, historical jump address exception information, and historical page eviction frequency information); it can be understood that the specific selection process here can be referred to the foregoing, and will not be elaborated here. It should also be noted that the rollback signal sent by the result comparison unit and the second signal sent by the fault detection unit are subjected to a logical AND operation and then input to the processor.

[0134] In the second aspect, if the operation results of processor core A and processor core R are the same at the first checkpoint established currently, the page information of the page corresponding to the first checkpoint recorded in the cache unit of processor core A is deleted, and the page information of the page corresponding to the first checkpoint recorded in the cache unit of processor core R is deleted, and the page content and context state of the page corresponding to the first checkpoint are stored in the single-particle immune storage unit; further, if there is a suspended processor core currently, a continue execution signal is sent to the processor to resume the operation of the suspended processor core.

[0135] In addition, every time a second checkpoint with the same operation result is obtained, the system timer is reconfigured; when the system timer times out, a restart signal is sent to the processor core. It can be seen that if the system timer is not reset for a long time, that is, no second checkpoint with the same operation result is obtained for a long time, an exception will be caused due to the overflow of the system timer, and the entire system will be restarted and a global timer overflow event will be recorded in the log.

[0136] For the convenience of understanding the content introduced in the above (2) to (3), the following is an example for illustration:

[0137] For example, processor core A runs the same application later than processor core R by a first time difference That is, the progress of processor core A is slower and the progress of processor core R is faster. As Figure 3 shown, when processor core A evicts page -1, processor core R evicts page -5. At this time, the absolute value of the difference in the number of pages that have been evicted by processor core A and processor core R reaches the predetermined first threshold "4", then processor core R is suspended (that is, after suspension, processor core R has not successfully evicted page -5);

[0138] And, in this case, the page address of page -1 and the context state when processor core R evicts page -1 have been stored in the cache unit of processor core R; then, after processor core A evicts page -1, the page address of page -1 and the context state when processor core A evicts page -1 are stored in the cache unit of processor core A;

[0139] In this way, since both the processor core A and the processor core R have swapped out page - 1, a first checkpoint corresponding to page - 1 is established. Thus, based on the page address of page - 1 in the cache unit of the processor core A, the page content of page - 1 swapped out by the processor core A is obtained. Based on the page address of page - 1 in the cache unit of the processor core R, the page content of page - 1 swapped out by the processor core R is obtained. Furthermore, it is compared whether the page content of page - 1 swapped out by the processor core A is consistent with the page content of page - 1 swapped out by the processor core R, and whether the context state when the processor core A swapped out page - 1 is consistent with the context state when the processor core R swapped out page - 1. If both are consistent, the serial number, page content, and corresponding context state of page - 1 are stored in the single - particle immune storage unit, and the system timer is reset; the addresses and corresponding context states of page - 1 in the cache units of the processor core A and the processor core R are deleted, and the processor core R is restored.

[0140] After that, when the processor core A swaps out page - 2, the page address of page - 2 and the context state when the processor core A swaps out page - 2 are stored in the cache unit of the processor core A; in this case, since both the processor core A and the processor core R have swapped out page - 2, a first checkpoint corresponding to page - 2 is established. Thus, based on the page address of page - 2 in the cache unit of the processor core A, the page content of page - 2 swapped out by the processor core A is obtained. Based on the page address of page - 2 in the cache unit of the processor core R, the page content of page - 2 swapped out by the processor core R is obtained. Furthermore, it is compared whether the page content of page - 2 swapped out by the processor core A is consistent with the page content of page - 2 swapped out by the processor core R, and whether the context state when the processor core A swapped out page - 2 is consistent with the context state when the processor core R swapped out page - 2. If both are consistent, the serial number, page content, and corresponding context state of page - 2 are stored in the single - particle immune storage unit (at this time, the single - particle immune storage unit already stores the relevant information of page - 1 and page - 2), and the system timer is reset; the addresses and corresponding context states of page - 2 in the cache units of the processor core A and the processor core R are deleted.

[0141] After that, when the processor core A evicts page - 3, it stores the page address of page - 3 and the context state when the processor core A evicts page - 3 in the cache unit of the processor core A; in this case, both the processor core A and the processor core R have evicted page - 3, then a first checkpoint corresponding to page - 3 is established, so that based on the page address of page - 3 in the cache unit of the processor core A, the page content of page - 3 evicted by the processor core A is obtained, and based on the page address of page - 3 in the cache unit of the processor core R, the page content of page - 3 evicted by the processor core R is obtained, and then it is determined whether the page content of page - 3 evicted by the processor core A is consistent with the page content of page - 3 evicted by the processor core R, and whether the context state when the processor core A evicts page - 3 is consistent with the context state when the processor core R evicts page - 3. If the comparison result of at least one of the page content and the context state is inconsistent, a rollback signal is issued.

[0142] Among them, if it is the processor core R that is rolled back, then, according to the content stored in the single - particle - immune storage unit (i.e., the relevant content of page - 1 and page - 2), the processor core R can be rolled back to page - 2, and the page addresses and corresponding context states of the pages after page - 2 in the cache unit of the processor core R are deleted.

[0143] (4)Rollback process:

[0144] After the processor core enters the rollback processing program, the memory pages belonging to this processor core are set to the invalid state, the relevant information of the pages in the single - particle - immune storage is read to overwrite the corresponding memory space, the context state is restored, and the execution is restarted from the second checkpoint corresponding to the restored page.

[0145] As can be seen from the above, in this embodiment, the two processor cores execute in lock - step in a loosely - coupled manner, cache the processing results, and after comparing that the running results of the two processor cores are inconsistent, one or two processor cores with a greater probability of error are rolled back according to the intelligent diagnosis of the fault detection unit; and the interface for processor fault rollback can be opened, and the user can customize the selection mode and algorithm for rolling back the processor, making the application scope of this lock - step fault - handling system wider. When a fault occurs, the running state of the processor core most likely to have a single - particle event is rolled back to the nearest second checkpoint. Since the recovery mode retains the work progress of the other normally - operating processor core in most scenarios, the performance cost during fault recovery is reduced.

[0146] In summary, this embodiment has the following advantages:

[0147] 1. It allows the two processor cores to execute asynchronously, reduces the impact of transient pulses on the system, and reduces the common - mode fault probability;

[0148] 2. When a processor core with a higher error probability can be identified, back out the processor core with a higher error probability, and as much as possible retain the execution progress of the processor core with correct results, so as to avoid the performance loss caused by the dual-core backout after a failure.

[0149] 3. The check in the first point is completed by the programmable logic terminal outside the processor, without the need to freeze the memory and without affecting the continued execution of the processor, resulting in less performance loss of the processor.

[0150] 4. After obtaining the second checkpoint with consistent running results, reset the system timer. If the processor core cannot advance the program execution progress using the checkpoint recovery method (that is, when the system timer times out, which can also be understood as not obtaining a new second checkpoint with consistent running results for a long time), then restart the entire system.

[0151] 5. The maximum distance of the execution progress gap between the two cores can be adjusted by adjusting the size of the cache unit, which is applicable to multiple operating systems and has better compatibility.

[0152] The above introduces the lockstep fault handling method provided by the embodiments of the present application. Next, the lockstep fault handling device provided by the embodiments of the present application will be introduced.

[0153] In a second aspect, an embodiment of the present application provides a lockstep fault handling device, as Figure 4 shown, the device includes:

[0154] A checkpoint establishment module 401, configured to establish a first checkpoint during the process of the first core and the second core of the processor running the same application program.

[0155] An acquisition module 402, configured to acquire a first running result of the first core at the currently established first checkpoint, and a second running result of the second core at the first checkpoint.

[0156] A selection module 403, configured to select a target core that needs to be backed out from the first core and the second core according to the historical running information of the first core and the historical running information of the second core.

[0157] A backout module 404, configured to back out the target core in the case where the first running result is inconsistent with the second running result.

[0158] Optionally, the checkpoint establishment module 401 is specifically configured to:

[0159] During the process of the first core and the second core running the same application program with a first time difference, when it is monitored that both the first core and the second core have swapped out the same first-sequence page of the application program, establish the first checkpoint corresponding to the first-sequence page.

[0160] Optionally, the device further includes:

[0161] A recording module, configured to record the page addresses of the pages swapped out by the first core and the second core, and the context states when the first core and the second core swap out pages, during the process that the first core and the second core run the same application;

[0162] The obtaining module 402 is specifically configured to:

[0163] Obtain the first page content of the page corresponding to the first checkpoint swapped out by the first core according to the recorded page address of the page corresponding to the first checkpoint swapped out by the first core, and determine the first page content and the first context state when the first core swapped out the page corresponding to the first checkpoint as the first running result;

[0164] Obtain the second page content of the page corresponding to the first checkpoint swapped out by the second core according to the recorded page address of the page corresponding to the first checkpoint swapped out by the second core, and determine the second page content and the second context state when the second core swapped out the page corresponding to the first checkpoint as the second running result.

[0165] Optionally, the device further includes:

[0166] A pause processing module, configured to pause the core to which the larger one of the first result quantity and the second result quantity belongs, when it is monitored that the absolute value of the difference between the first result quantity of the pages swapped out by the first core and the second result quantity of the pages swapped out by the second core is equal to a first threshold;

[0167] A resume processing module, configured to resume the operation of the paused core when the first running result is consistent with the second running result and there is a paused core.

[0168] Optionally, the device further includes:

[0169] A deletion module, configured to delete the page addresses of the recorded first page content, the first context state, the page addresses of the second page content, and the second context state when the first running result is consistent with the second running result.

[0170] Optionally, the device further includes:

[0171] A deletion module, configured to delete the page addresses of the pages with the second serial number and the corresponding context states when the first running result is inconsistent with the second running result;

[0172] Wherein, the second serial number includes: the serial number of the page corresponding to the first checkpoint to the serial number of the page that was last swapped out by the target core when the first checkpoint was established.

[0173] Optionally, the historical operation information includes at least one of the following: historical rollback information, historical jump address exception information, and historical page swap-out frequency information.

[0174] Optionally, the selection module 403 selects the target core that needs to be rolled back from the first core and the second core according to the historical operation information of the first core and the historical operation information of the second core, including:

[0175] Select the core that meets the first condition as the target core from the first core and the second core;

[0176] Wherein, the first condition includes at least one of the following:

[0177] The historical rollback information indicates that it has not been rolled back within the first time period;

[0178] The historical jump address exception information indicates that there is a jump address in the executed code, and the code segment associated with the jump address does not have access permission in the application;

[0179] The historical page swap-out frequency information indicates that the frequency of page swap-out within the second time period is greater than the second threshold.

[0180] Optionally, the selection module 403 selects the target core that needs to be rolled back from the first core and the second core according to the historical operation information of the first core and the historical operation information of the second core, including:

[0181] In the case of not receiving the first signal, select the target core from the first core and the second core according to the historical operation information of the first core and the historical operation information of the second core;

[0182] Wherein, the first signal is used to indicate the core that needs to be rolled back.

[0183] Optionally, the selection module 403 is further configured to: in the case of receiving the first signal, select the target core from the first core and the second core according to the indication of the first signal.

[0184] Optionally, the rollback module 404 is specifically configured to:

[0185] According to the running results of the recorded first core or the second core at the second checkpoint, roll back the target core to the nearest second checkpoint;

[0186] Wherein, the second checkpoint includes: a checkpoint where the running results of the first core are consistent with the running results of the second core.

[0187] Optionally, the device further includes:

[0188] A timer reset module, configured to reset the system timer when the first running result is consistent with the second running result;

[0189] A restart module, configured to instruct the first core and the second core to re-run the application when the system timer times out.

[0190] Optionally, the device further includes:

[0191] A marking module, configured to mark the page corresponding to the established first checkpoint as read-only when establishing the first checkpoint.

[0192] Optionally, the device is applied to a programmable logic device, and the programmable logic device is disposed outside the processor.

[0193] Optionally, the device further includes:

[0194] A single-event immune storage unit, configured to store the first running result or the second running result when the first running result is consistent with the second running result.

[0195] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For related parts, please refer to the partial description of the method embodiment.

[0196] In a third aspect, an embodiment of the present application further provides an electronic device, as Figure 5 shown. The electronic device may include: a processor 510, a communication interface 520, a memory 530, and a communication bus 540. Among them, the processor 510, the communication interface 520, and the memory 530 communicate with each other through the communication bus 540. The processor 510 may call logic instructions in the memory 530, and the processor 510 is configured to execute the steps of the above-mentioned lockstep fault handling method.

[0197] In addition, when the logical instructions in the above-mentioned memory 530 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0198] The embodiments of this application also provide a computer-readable storage medium. A computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, it implements each process of the above-mentioned lockstep fault handling method embodiment and can achieve the same technical effects. To avoid repetition, it will not be elaborated here.

[0199] In the above embodiments, it can be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired manner (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or a wireless manner (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more integrated available media. The available medium can be a magnetic medium (for example, floppy disks, hard disks, magnetic tapes), an optical medium (for example, DVDs), or a semiconductor medium (for example, solid state disks (SSDs)).

[0200] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0201] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other, and the key point of each embodiment is to illustrate the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for the relevant parts, reference can be made to the partial description of the method embodiment.

[0202] The above are only the preferred embodiments of the present application and are not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A method for handling locked-step faults, characterized in that, The method includes: During the process of running the same application on the first core and the second core of the processor, establishing a first checkpoint; Obtaining a first running result of the first core at the currently established first checkpoint and a second running result of the second core at the first checkpoint; Selecting a target core to be rolled back from the first core and the second core according to the historical running information of the first core and the historical running information of the second core; Rolling back the target core when the first running result is inconsistent with the second running result; Wherein, the method further includes: During the process of running the same application on the first core and the second core, recording the page addresses of the pages swapped out by the first core and the second core, and the context states when the first core and the second core swap out the pages; The obtaining the first running result of the first core at the currently established first checkpoint and the second running result of the second core at the first checkpoint includes: According to the page address of the page swapped out by the first core corresponding to the first checkpoint that has been recorded, obtaining the first page content of the page swapped out by the first core corresponding to the first checkpoint, and determining the first page content and the first context state when the first core swapped out the page corresponding to the first checkpoint as the first running result; According to the page address of the page swapped out by the second core corresponding to the first checkpoint that has been recorded, obtaining the second page content of the page swapped out by the second core corresponding to the first checkpoint, and determining the second page content and the second context state when the second core swapped out the page corresponding to the first checkpoint as the second running result.

2. The method according to claim 1, wherein The establishing a first checkpoint during the process of running the same application on the first core and the second core of the processor includes: During the process of running the same application on the first core and the second core with a first time difference, when it is monitored that both the first core and the second core have swapped out the pages with the same first serial number of the application, establishing the first checkpoint corresponding to the pages with the first serial number.

3. The method according to claim 1, characterized in that, The method further includes: When the absolute value of the difference between the first result quantity of the pages swapped out by the first core and the second result quantity of the pages swapped out by the second core is equal to a first threshold, pausing the core to which the larger one of the first result quantity and the second result quantity belongs; When the first running result is consistent with the second running result and there is a paused core, resuming the operation of the paused core.

4. The method according to claim 3, wherein The method further includes: When the first running result is consistent with the second running result, deleting the page addresses of the recorded first page content, the first context state, the page addresses of the second page content, and the second context state.

5. The method according to claim 1, characterized in that, The method further includes: In the case where the first operation result is inconsistent with the second operation result, delete the page address of the page with the second serial number that has been recorded and the corresponding context state; Wherein, the second serial number includes: the serial number of the page corresponding to the first checkpoint to the serial number of the page that was most recently swapped out by the target core when the first checkpoint was established.

6. The method according to claim 1, wherein The historical operation information includes at least one of the following: historical rollback information, historical jump address exception information, and historical page swap frequency information.

7. The method according to claim 6, wherein The selecting the target core that needs to be rolled back from the first core and the second core according to the historical operation information of the first core and the historical operation information of the second core includes: Selecting the core that meets the first condition as the target core from the first core and the second core; Wherein, the first condition includes at least one of the following: The historical rollback information indicates that it has not been rolled back within the first time period; The historical jump address exception information indicates that there is a jump address in the executed code, and the code segment associated with the jump address does not have access permission in the application; The historical page swap frequency information indicates that the frequency of swapping out pages within the second time period is greater than the second threshold.

8. The method according to claim 1 or 7, characterized in that, The selecting the target core that needs to be rolled back from the first core and the second core according to the historical operation information of the first core and the historical operation information of the second core includes: In the case where the first signal is not received, selecting the target core from the first core and the second core according to the historical operation information of the first core and the historical operation information of the second core; Wherein, the first signal is used to indicate the core that needs to be rolled back.

9. The method according to claim 8, wherein The method further includes: In the case where the first signal is received, selecting the target core from the first core and the second core according to the indication of the first signal.

10. The method according to claim 1, characterized in that The rolling back of the target core includes: Rolling back the target core to the nearest second checkpoint according to the operation result of the first core or the second core recorded at the second checkpoint; Wherein, the second checkpoint includes: the checkpoint where the operation result of the first core is consistent with the operation result of the second core.

11. The method according to claim 1, characterized in that The method further includes: In the case where the first operation result is consistent with the second operation result, reset the system timer; When the system timer times out, instruct the first core and the second core to re-run the application.

12. The method according to claim 1, characterized in that, The method further includes: When the first checkpoint is established, mark the page corresponding to the established first checkpoint as read-only.

13. The method according to claim 1, wherein The method is applied to a programmable logic device, and the programmable logic device is arranged outside the processor.

14. The method according to claim 1, wherein The method further includes: In the case where the first operation result is consistent with the second operation result, store the first operation result or the second operation result in a single-event immune storage unit.

15. A lockstep fault handling device, characterized in that, The device includes: A checkpoint establishment module, configured to establish a first checkpoint during the process of the first core and the second core of the processor running the same application; An acquisition module, configured to acquire a first running result of the first core at a first checkpoint established currently, and a second running result of the second core at the first checkpoint; A selection module, configured to select a target core to be rolled back from the first core and the second core according to historical running information of the first core and historical running information of the second core; A rollback module, configured to roll back the target core when the first running result is inconsistent with the second running result; Wherein, the apparatus further includes: A recording module, configured to record page addresses of pages swapped out by the first core and the second core, and context states when the first core and the second core swap out pages during the process that the first core and the second core run the same application; The acquisition module is specifically configured to: According to the page address of the page swapped out by the first core corresponding to the first checkpoint that has been recorded, acquire a first page content of the page swapped out by the first core corresponding to the first checkpoint, and determine the first page content and the first context state when the first core swapped out the page corresponding to the first checkpoint as the first running result; According to the page address of the page swapped out by the second core corresponding to the first checkpoint that has been recorded, acquire a second page content of the page swapped out by the second core corresponding to the first checkpoint, and determine the second page content and the second context state when the second core swapped out the page corresponding to the first checkpoint as the second running result.

16. The device according to claim 15, characterized in that, The checkpoint establishment module is specifically configured to: During the process that the first core and the second core run the same application with a first time difference, when it is monitored that both the first core and the second core have swapped out pages with the same first serial number of the application, establish a first checkpoint corresponding to the pages with the first serial number.

17. The device according to claim 15, characterized in that The apparatus further includes: A pause processing module, configured to pause the core to which the larger one of the first result quantity and the second result quantity belongs when the absolute value of the difference between the first result quantity of the pages swapped out by the first core and the second result quantity of the pages swapped out by the second core is equal to a first threshold; A resume processing module, configured to resume the operation of the paused core when the first running result is consistent with the second running result and there is a paused core.

18. The device according to claim 17, wherein The apparatus further includes: A deletion module, configured to delete the page address of the recorded first page content, the first context state, the page address of the second page content, and the second context state when the first running result is consistent with the second running result.

19. The device according to claim 15, characterized in that, The apparatus further includes: A deletion module, configured to delete the page address of the page with the second serial number and the corresponding context state when the first running result is inconsistent with the second running result. Among them, the second serial number includes: the serial number of the page corresponding to the first checkpoint to the serial number of the page that was last swapped out by the target core when the first checkpoint was established.

20. The device according to claim 15, characterized in that, The historical running information includes at least one of the following: historical rollback information, historical jump address exception information, and historical page swap-out frequency information.

21. The device according to claim 20, characterized in that, The selection module selects the target core that needs to be rolled back from the first core and the second core according to the historical running information of the first core and the historical running information of the second core, including: Among the first core and the second core, select the core that meets the first condition as the target core; Among them, the first condition includes at least one of the following: The historical rollback information indicates that it has not been rolled back within the first time period; The historical jump address exception information indicates that there is a jump address in the executed code, and the code segment associated with the jump address does not have access permission in the application; The historical page swap-out frequency information indicates that the frequency of page swap-out within the second time period is greater than the second threshold.

22. The device according to claim 15 or 21, characterized in that, The selection module selects the target core that needs to be rolled back from the first core and the second core according to the historical running information of the first core and the historical running information of the second core, including: In the case where the first signal is not received, select the target core from the first core and the second core according to the historical running information of the first core and the historical running information of the second core; Among them, the first signal is used to indicate the core that needs to be rolled back.

23. The device according to claim 22, wherein The selection module is further used for: In the case where the first signal is received, select the target core from the first core and the second core according to the indication of the first signal.

24. The device according to claim 15, characterized in that The rollback module is specifically used for: According to the recorded running result of the first core or the second core at the second checkpoint, roll back the target core to the nearest second checkpoint; Among them, the second checkpoint includes: the checkpoint where the running result of the first core is consistent with the running result of the second core.

25. The device according to claim 15, characterized in that The device further includes: A timer reset module, used to reset the system timer when the first running result is consistent with the second running result; A restart module, used to indicate the first core and the second core to re-run the application when the system timer times out.

26. The device according to claim 15, characterized in that, The device further includes: A marking module, used to mark the page corresponding to the established first checkpoint as read-only when the first checkpoint is established.

27. The device according to claim 15, characterized in that, The device is applied to an editable logic terminal, and the editable logic terminal is arranged outside the processor.

28. The device according to claim 15, characterized in that The device further includes: A single-particle immune storage unit, used to store the first running result or the second running result when the first running result is consistent with the second running result.

29. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete mutual communication through the communication bus; The memory is used to store computer programs; A processor, when executing a program stored in a memory, implements the steps in the steps of the lockstep fault handling method according to any one of claims 1 to 14.

30. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the lockstep fault handling method according to any one of claims 1 to 14 are implemented.

Images