Interface device and operating method thereof

Abstract

The invention relates to an interface device and an operation method thereof. A device for communicating with a host device through an interface according to the present disclosure comprises: a clock signal generator configured to generate a first reference clock signal to be used by the device; and a reference clock signal selection circuit coupled to communicate with the clock signal generator to receive a first reference clock signal, and configured to receive a second reference clock signal from a host device, and configured to select a reference clock signal in response to a first reset signal received first among a plurality of reset signals from the host device, one of the first reference clock signal and the second reference clock signal is selected according to whether the second reference clock signal is provided from the host device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2023-0153478, filed on November 8, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The disclosed technology generally relates to a semiconductor device, and more particularly, to an interface device and a method of operating the interface device. Background Art

[0004] The Peripheral Component Interconnect (PCI) bus standard may define a bus protocol that may be used to connect a host device (e.g., one or more CPUs) to one or more peripheral devices (e.g., data storage devices) to perform various operations including those initiated and / or controlled by the host device. The PCI Express (PCIe) bus standard may be defined by the PCI standard and may include a physical communication layer defined as a high-speed serial interface for host devices and peripheral devices. Summary of the invention

[0005] The disclosed technology can be implemented in some embodiments to provide an interface device (e.g., a PCIe device) and a method of operating the interface device (e.g., a PCIe device), which can automatically select a clock mode between a common clock mode and a separate clock mode when multiple reset signals are enabled.

[0006] In addition, various embodiments also provide a PCIe device capable of automatically determining whether to apply spread spectrum clocking and a method of operating the PCIe device.

[0007] In an embodiment, an interface device (e.g., a PCIe device) that communicates with a host device via an interface may include: a clock signal generator configured to generate a first reference clock signal to be used by the interface device; and a reference clock signal selection circuit connected to communicate with the clock signal generator to receive the first reference clock signal, and configured to receive a second reference clock signal from the host device, and configured to select one of the first reference clock signal and the second reference clock signal according to whether the second reference clock signal is provided from the host device in response to a first reset signal that is first received among multiple reset signals from the host device.

[0008] In an embodiment, an interface device for communicating with a host device may include: a receiver configured to receive a data set and a skip ordered set (SKPOS) from the host device based on a first reference clock signal; an elastic buffer connected to the receiver and configured to store the data set and the skip ordered set; a buffer status detector connected to the elastic buffer and configured to detect the status of the elastic buffer; and a spread spectrum clock selection circuit connected to the receiver and configured to determine whether to activate a spread spectrum clock (SSC) based on a reception interval of a received skip ordered set and the status of the elastic buffer.

[0009] In an embodiment, a method of operating an interface device that communicates with a host device may include: generating a first reference clock signal; selecting one of a common clock mode and a separate clock mode based on a comparison result between the first reference clock signal generated by the interface device and a second clock signal received from the host device; receiving a data set and a jump ordered set (SKPOS) from the host device based on the first reference clock signal according to the separate clock mode; storing the data set and the jump ordered set in an elastic buffer; and determining whether to apply spread spectrum clocking (SSC) to the first reference clock signal based on a reception interval of the received jump ordered set and a state of the elastic buffer.

[0010] In an embodiment, a PCIe controller may include: a reference clock signal selection circuit configured to detect a first clock mode; a spread spectrum clock (SSC) selection circuit configured to output a clock mode selection signal by detecting a second clock mode based on the first clock mode; and a physical layer configured to determine a final clock mode based on the clock mode selection signal.

[0011] The first clock mode may include a common clock mode and a separate clock mode, and wherein the second clock mode includes a separate reference clock with independent SSC (SRIS) mode and a separate reference clock without SSC (SRNS) mode.

[0012] The reference clock signal selection circuit may determine the first clock mode by detecting whether the reference clock signal is provided from the host device.

[0013] The physical layer further includes a reference clock signal detector, which is configured to detect a reference clock signal, and wherein the reference clock signal selection circuit is configured to: receive a signal from the reference clock signal detector indicating whether the reference clock signal is detected; and based on the received signal, output a signal indicating whether the reference clock signal is provided.

[0014] When receiving a signal indicating whether the reference clock signal is detected from the reference clock signal detector, the reference clock signal selection circuit may ignore input of a reset signal provided from the host device.

[0015] The reference clock signal selection circuit may ignore input of a reset signal provided from the host device until a setting operation of a register value associated with detection of the first clock pattern is completed.

[0016] The physical layer further includes: a serializer configured to convert parallel data into serial data and output; a deserializer configured to convert serial data into parallel data and output; and an elastic buffer configured to store data sets and jump ordered sets.

[0017] In case the first clock mode is the single clock mode, the spread spectrum clock selection circuit may output a signal by measuring an interval of a hop ordered set in the elastic buffer.

[0018] In the case where the first clock mode is a single clock mode, the spread spectrum clock selection circuit can set a first reference value and a second reference value greater than the first reference value, and output a signal indicating whether the interval of the hop ordered set is less than the first reference value, or a signal indicating whether the interval of the hop ordered set is greater than the second reference value.

[0019] The spread spectrum clock selection circuit may measure the interval of the hop ordered set by detecting the data set and the hop ordered set based on data received from the host device.

[0020] The spread spectrum clock selection circuit may output a clock mode selection signal for activating the SRIS mode to the physical layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a diagram illustrating an example of a peripheral component interconnect express (PCIe) device based on an embodiment of the disclosed technology.

[0022] Figure 2 is a diagram illustrating the operation of a reference clock signal selection circuit according to an embodiment of the disclosed technology.

[0023] Figure 3A is a diagram illustrating an example of selecting a common clock mode based on an embodiment of the disclosed technology.

[0024] Figure 3B is a diagram illustrating an example of selecting a separate clock mode based on an embodiment of the disclosed technology.

[0025] Figure 4 is a block diagram illustrating a spread spectrum clock selection circuit according to an embodiment of the disclosed technology.

[0026] Figure 5A is a block diagram showing an example in which a spread spectrum clock is activated based on an embodiment of the disclosed technology.

[0027] Figure 5B is a diagram showing an example in which a spread spectrum clock is deactivated according to an embodiment of the disclosed technology.

[0028] Figure 6 is a flow chart illustrating a method of operating a PCIe device based on an embodiment of the disclosed technology.

[0029] Figure 7 is a flow chart illustrating an example method of operating a PCIe device to determine whether to activate spread spectrum clocking based on an embodiment of the disclosed technology.

[0030] Figure 8 is a flow chart illustrating another example method of operating a PCIe device to determine whether to activate spread spectrum clocking based on an embodiment of the disclosed technology.

[0031] Fig. 9 is a flow chart illustrating an example of activating application of spread spectrum clocking according to link status based on an embodiment of the disclosed technology.

[0032] Fig.10 is a flow chart showing another example of activating an application of a spread spectrum clock according to a link status based on an embodiment of the disclosed technology.

[0033] Fig.11 is a diagram showing an example in which a spread spectrum clock is activated based on an embodiment of the disclosed technology.

[0034] Fig.12 is a diagram showing a PCIe system based on an embodiment of the disclosed technology. DETAILED DESCRIPTION

[0035] The specific structural features or functions of certain embodiments disclosed in this patent document are examples for describing certain implementations of the disclosed technology.

[0036] A peripheral component interconnect express (PCIe) device can be connected to a host device having one or more CPUs via a PCIe bus to perform various operations commanded or controlled by the host device based on a reference clock signal. In some embodiments, the reference clock signal can be set according to a common clock mode or a separate clock mode.

[0037] In the common clock mode, the PCIe device and the host controlling the PCIe device can operate using a common reference clock signal. The common reference clock signal can be generated by a reference clock signal generator included in the host. In the separate clock mode, the PCIe device and the host operate using different reference clock signals. The PCIe device and the host can each include a reference clock signal generator for generating different reference clock signals.

[0038] In addition, the PCIe device may convert a reference clock signal into a clock signal having a spread spectrum by using a spread spectrum clock (SSC).

[0039] Figure 1 is a diagram showing an example of a PCIe device 100 based on an embodiment of the disclosed technology.

[0040] Reference Figure 1 , the PCIe device 100 and the host 200 can support communication using a PCIe interface.

[0041] The PCIe device 100 may include a receiver 110 , a first reference clock signal generator 120 , a reference clock signal detector 130 , a reference clock signal selection circuit 140 , an elastic buffer 150 , a buffer status detector 160 , a spread spectrum clock selection circuit 170 , and a reference clock signal controller 180 .

[0042] The receiver 110 may receive data DATA from the host 200 through a PCIe interface. The data DATA may include a data set and a jump ordered set. The jump ordered set may be used to perform clock tolerance compensation. More specifically, when there is a frequency difference between the transmitting side and the receiving side, data may be lost due to the difference in data processing speed between the transmitting side and the receiving side. In order to avoid such data loss, a jump ordered set may be used to compensate for the corresponding frequency difference. The transmitting side may be the host 200, and the receiving side may be the PCIe device 100. The frequency may refer to the frequency of the reference clock signal.

[0043] In an embodiment, the receiver 110 may include a deserializer, a descrambler, a clock data recovery (CDR) circuit, etc. The receiver 110 may receive serial data DATA and output parallel data.

[0044] The first reference clock signal generator 120 may generate a first reference clock signal REFCLK1 . The first reference clock signal REFCLK1 may be generated inside the PCIe device 100 .

[0045] The reference clock signal detector 130 may detect the second reference clock signal REFCLK2. The second reference clock signal REFCLK2 may be generated by the host 200 outside the PCIe device 100. The first reference clock signal REFCLK1 and the second reference clock signal REFCLK2 may be different from each other.

[0046] In an embodiment, the reference clock signal detector 130 may detect the second reference clock signal REFCLK2 in response to the reference clock signal detection request REQ_DET of the reference clock signal selection circuit 140 .

[0047] The reference clock signal selection circuit 140 may select any one of the first reference clock signal REFCLK1 and the second reference clock signal REFCLK2 according to whether the second reference clock signal REFCLK2 is provided from the host 200 .

[0048] In an embodiment, the reference clock signal selection circuit 140 may detect a first clock mode. The first clock mode may include a common clock mode and a separate clock mode.

[0049] In an embodiment, the reference clock signal selection circuit 140 may determine whether the second reference clock signal REFCLK2 is provided from the host 200 based on a comparison result of the first reference clock signal REFCLK1 and the second reference clock signal REFCLK2 .

[0050] In an embodiment, when the reference clock signal selection circuit 140 determines that the second reference clock signal REFCLK2 is provided from the host 200, the reference clock signal selection circuit 140 may select the second reference clock signal REFCLK2. The PCIe device 100 and the host 200 may operate in a common clock mode. For example, the PCIe device 100 and the host 200 may operate by jointly using the second reference clock signal REFCLK2.

[0051] In an embodiment, when the reference clock signal selection circuit 140 determines that the second reference clock signal REFCLK2 is not provided from the host 200, the reference clock signal selection circuit 140 may select the first reference clock signal REFCLK1. For example, when the reference clock signal selection circuit 140 determines that the host 200 does not send the second reference clock signal REFCLK2 to the PCIe device 100 within a predetermined period of time, the reference clock signal selection circuit 140 may select the first reference clock signal REFCLK1. In this case, the PCIe device 100 and the host 200 may operate in a separate clock mode. For example, the PCIe device 100 may operate using the first reference clock signal REFCLK1, and the host 200 may operate using the second reference clock signal REFCLK2. In addition, the reference clock signal selection circuit 140 may provide a separate clock mode enable signal EN_SRMODE to the spread spectrum clock selection circuit 170.

[0052] In an embodiment, the reference clock signal selection circuit 140 may provide the selected reference clock signal SEL_CLK to the reference clock signal controller 180 .

[0053] The elastic buffer 150 may store data sets and jump-ordered sets received by the receiver 110 .

[0054] In an embodiment, the elastic buffer 150 may use hop ordered sets to perform clock tolerance compensation.

[0055] The buffer state detector 160 may detect the state STAT of the elastic buffer 150 .

[0056] In an embodiment, the state STAT of the elastic buffer 150 may include a normal state, an overflow state, and an underflow state UNDER_FLOW. When the transmitting side and the receiving side operate at different frequencies, the overflow state or the underflow state UNDER_FLOW may occur. For example, in a memory buffer such as the elastic buffer 150, an overflow may occur even when the input frequency of the data symbol is greater than the output frequency, and an underflow may occur even when the output frequency of the data symbol is greater than the input frequency.

[0057] The spread spectrum clock selection circuit 170 may determine whether to activate the spread spectrum clock in response to the individual clock mode enable signal EN_SRMODE.

[0058] In an embodiment, when the first clock mode is a separate clock mode, the spread spectrum clock selection circuit 170 may detect the second clock mode to output a clock mode selection signal. The second clock mode may include a first mode in which the spread spectrum clock is activated and a second mode in which the spread spectrum clock is deactivated. The first mode may be a "separate reference clock with independent SSC (SRIS)" mode. The second mode may be a "separate reference clock without SSC (SRNS)" mode.

[0059] In an embodiment, the spread spectrum clock selection circuit 170 may determine whether to activate the spread spectrum clock based on the interval of receiving the hop ordered set and the state STAT of the elastic buffer 150. The receiving interval of the hop ordered set may be set based on the absolute value of the frequency difference between the transmitting side and the receiving side.

[0060] In an embodiment, the spread spectrum clock selection circuit 170 can select any one of the first mode and the second mode. The first mode can be the SRIS mode. The second mode can be the SRNS mode. The spread spectrum clock selection circuit 170 can send the selected mode SEL_MODE to the reference clock signal controller 180.

[0061] When spread spectrum clocking is activated, the reference clock signal controller 180 may generate a target reference clock signal TARGET_CLK having a spread spectrum from the first reference clock signal REFCLK1 .

[0062] For example, when the selected mode SEL_MODE is the first mode, the reference clock signal controller 180 may generate the target reference clock signal TARGET_CLK by applying the spread spectrum clock to the first reference clock signal REFCLK1. The PCIe device 100 may operate using the target reference clock signal TARGET_CLK.

[0063] The host 200 may include a transmitter 210 and a second reference clock signal generator 220 .

[0064] The transmitter 210 may provide the data DATA to the PCIe device 100 through the PCIe interface.

[0065] In an embodiment, when the transmitter 210 provides data sets to the PCIe device 100 , skip ordered sets may be inserted between the data sets at predetermined intervals.

[0066] In an embodiment, the transmitter 210 may include a serializer, a scrambler, etc. In an embodiment, the transmitter 210 may convert parallel data into serial data DATA and output the serial data DATA.

[0067] The second reference clock signal generator 220 may generate the second reference clock signal REFCLK2. In the common clock mode, the transmitter 210 may provide the second reference clock signal REFCLK2 to the PCIe device 100.

[0068] Figure 2 is a diagram illustrating the operation of the reference clock signal selection circuit 140 according to an embodiment of the disclosed technology.

[0069] Reference Figure 2 The reference clock signal selection circuit 140 may include a selection circuit controller 141 , a detection signal generator 142 , a first counter 143 , a second counter 144 , a reference clock signal comparator 145 , and a reference clock signal selector 146 .

[0070] The selection circuit controller 141 may control the reference clock signal selection circuit 140 to perform an operation of selecting a reference clock signal. In an embodiment, the selection circuit controller 141 may include an AND gate circuit 141 - 1 .

[0071] In an embodiment, the selection circuit controller 141 may control the reference clock signal selection circuit 140 to perform an operation of selecting a reference clock signal in response to a reset signal PERST first received among a plurality of reset signals received from the host 200 .

[0072] The reset signal may be provided to perform a reset operation within the PCIe device 100, for example, to initialize a register value set to the PCIe device 100 and to reset the register value. In an embodiment, the reset signal PERST received first may be the reset signal PERST first received from the host 200 after the reference clock signal selection circuit 140 selects a previous reference clock signal selected before the current reference clock signal is selected.

[0073] In an embodiment, when the reset signal PERST and the physical layer initialization signal PHY_INIT received first are enabled, the selection circuit controller 141 may generate a control signal EN_CLKSEL for instructing to perform an operation of selecting a reference clock signal.

[0074] In an embodiment, the physical layer initialization signal PHY_INIT may be enabled until the operation of selecting a reference clock signal and the operation of setting an initial register value of the physical layer are completed.

[0075] In an embodiment, when receiving a signal indicating whether the reference clock signal is detected from the reference clock signal detector 130 , the selection circuit controller 141 may ignore an input of a reset signal provided from the host 200 .

[0076] In an embodiment, the selection circuit controller 141 may ignore input of a reset signal provided from the host 200 until an operation of setting a register value associated with an operation of selecting a reference clock signal is completed.

[0077] In an embodiment, when the selection circuit controller 141 receives another reset signal other than the reset signal PERST received first among multiple reset signals, the selection circuit controller 141 can block the operation caused by the reset signal until the operation of selecting the reference clock signal and the operation of setting the initial register value of the physical layer are completed.

[0078] For example, when the selection circuit controller 141 receives another reset signal during the operation of selecting the reference clock signal and the operation of setting the initial register value of the physical layer, the selection circuit controller 141 may block the operation triggered by the reset signal.

[0079] In an embodiment, the reference clock signal selection circuit 140 may provide a reference clock signal detection request REQ_DET to the reference clock signal detector 130 in response to the control signal EN_CLKSEL. The reference clock signal detector 130 may generate a signal indicating that the detected signal is valid and a signal indicating whether the second reference clock signal REFCLK2 is detected. The reference clock signal detector 130 may provide a signal indicating whether the second reference clock signal REFCLK2 is detected to the detection signal generator 142.

[0080] The detection signal generator 142 may generate the detection signal DET_CLK according to whether the second reference clock signal REFCLK2 is detected. For example, when the reference clock signal detector 130 detects the second reference clock signal REFCLK2, the detection signal generator 142 may enable the detection signal DET_CLK. On the other hand, when the reference clock signal detector 130 does not detect the second reference clock signal REFCLK2, the detection signal generator 142 may disable the detection signal DET_CLK. The detection signal generator 142 may provide the detection signal DET_CLK to the reference clock signal selector 146.

[0081] The first counter 143 may count the number of times the first reference clock signal REFCLK1 is switched (eg, the number of times switched between binary representations 0 and 1) in response to the control signal EN_CLKSEL and output a first count value CNT1.

[0082] The second counter 144 may count the number of times the second reference clock signal REFCLK2 is switched and output a second count value CNT2 in response to the control signal EN_CLKSEL.

[0083] The reference clock signal comparator 145 may compare the first count value CNT1 with the second count value CNT2. The reference clock signal comparator 145 may provide the reference clock signal selector 146 with a comparison result COMP_CLK comparing the first count value CNT1 with the second count value CNT2.

[0084] The reference clock signal selector 146 may select any one of the reference clock signals based on the detection signal DET_CLK and the comparison result COMP_CLK.

[0085] In an embodiment, the reference clock signal selector 146 may include a NOR gate circuit 146 - 1 and a multiplexer (MUX) 146 - 2 .

[0086] In an embodiment, the NOR gate circuit 146-1 of the reference clock signal selector 146 may receive the detection signal DET_CLK and the comparison result COMP_CLK. The NOR gate circuit 146-1 may output the common clock mode enable signal or the individual clock mode enable signal EN_SRMODE to the multiplexer 146-2 in response to the detection signal DET_CLK and the comparison result COMP_CLK.

[0087] In an embodiment, when the multiplexer 146-2 receives the common clock mode enable signal, the multiplexer 146-2 may output the second reference clock signal REFCLK2 as the selected reference clock signal SEL_CLK. On the other hand, when the multiplexer 146-2 receives the individual clock mode enable signal EN_SRMODE, the multiplexer 146-2 may output the first reference clock signal REFCLK1 as the selected reference clock signal SEL_CLK.

[0088] When assertions and de-assertions similar to glitch are repeated when the reset signal PERST is released, it may be determined that the PCIe device 100 stably performs an operation of selecting the common clock mode or the individual clock mode.

[0089] Figure 3A is a diagram illustrating an example of selecting a common clock mode based on an embodiment of the disclosed technology.

[0090] Reference Figure 2 and Figure 3A , the reset signal PERST may be enabled at T0.

[0091] At T1 , the physical layer initialization signal PHY_INIT may be enabled in response to the reset signal PERST.

[0092] When the reset signal PERST and the physical layer initialization signal PHY_INIT are enabled, the reference clock signal selection circuit 140 may enable the reference clock signal detection request REQ_DET. In response to the reference clock signal detection request REQ_DET, the reference clock signal detector 130 may disable the signal DET_VALID indicating that the detection of the reference clock signal is valid at a low level and may enable the signal indicating whether the second reference clock signal REFCLK2 is detected. The detection signal DET_CLK according to whether the second reference clock signal REFCLK2 is detected may be enabled at a low level.

[0093] At T2 , a signal DET_VALID indicating detection validity of the reference clock signal may be enabled at a high level.

[0094] In an embodiment, a first count value CNT1 corresponding to the first reference clock signal REFCLK1 and a second count value CNT2 corresponding to the second reference clock signal REFCLK2 may be compared with each other. As a result of the comparison, when the difference between the first count value CNT1 and the second count value CNT2 is greater than a threshold value, the comparison result COMP_CLK may have a low level. The NOR gate circuit 146-1 may output a high-level signal. The high-level signal may indicate a common clock mode enable signal. Therefore, the multiplexer 146-2 may output the second reference clock signal REFCLK2 as the selected reference clock signal SEL_CLK.

[0095] Figure 3B is a diagram illustrating an example of selecting a separate clock mode based on an embodiment of the disclosed technology.

[0096] Reference Figure 2 and Figure 3B , the reset signal PERST may be enabled at T0 ′.

[0097] At T1 ′, the physical layer initialization signal PHY_INIT may be enabled in response to the reset signal PERST.

[0098] When the reset signal PERST and the physical layer initialization signal PHY_INIT are enabled, the reference clock signal selection circuit 140 may enable the reference clock signal detection request REQ_DET. In response to the reference clock signal detection request REQ_DET, the reference clock signal detector 130 may disable the signal DET_VALID indicating that the detection of the reference clock signal is valid at a low level, and may enable the signal indicating whether the second reference clock signal REFCLK2 is detected. The detection signal DET_CLK corresponding to whether the second reference clock signal REFCLK2 is detected may be enabled at a low level.

[0099] At T2 ′, a signal DET_VALID indicating that detection of the reference clock signal is valid may be enabled at a high level.

[0100] In an embodiment, a first count value CNT1 corresponding to the first reference clock signal REFCLK1 and a second count value CNT2 corresponding to the second reference clock signal REFCLK2 may be compared with each other. As a result of the comparison, when the difference between the first count value CNT1 and the second count value CNT2 is greater than or equal to a predetermined threshold, the comparison result COMP_CLK may have a high level. The NOR gate circuit 146-1 may output a low-level signal. The low-level signal may indicate a separate clock mode enable signal EN_SRMODE. Therefore, the multiplexer 146-2 may output the first reference clock signal REFCLK1 as the selected reference clock signal SEL_CLK.

[0101] Figure 4 is a block diagram illustrating a spread spectrum clock selection circuit 170 according to an embodiment of the disclosed technology.

[0102] Reference Figure 4 The spread spectrum clock selection circuit 170 may include a hopping ordered set detector 171 , a hopping ordered set counter 172 , a hopping ordered set comparator 173 and a mode selector 174 .

[0103] The hopping ordered set detector 171 may detect a hopping ordered set SKPOS received by the receiver 110. For example, the hopping ordered set detector 171 may receive data DATA from the receiver 110. The hopping ordered set detector 171 may detect the hopping ordered set SKPOS included in the data DATA in response to the individual clock mode enable signal EN_SRMODE. The hopping ordered set detector 171 may provide the detected hopping ordered set SKPOS to the hopping ordered set counter 172.

[0104] The hop ordered set counter 172 may output a count value CNT_INTERVAL corresponding to a reception interval in response to the individual clock mode enable signal EN_SRMODE.

[0105] In an embodiment, the hop-ordered-set counter 172 may count the number of times the first reference clock signal REFCLK1 is toggled (eg, the number of times it switches between binary representations of 0 and 1) while continuously receiving the hop-ordered-set SKPOS.

[0106] The hopping ordered-set comparator 173 may compare the reception interval of the hopping ordered-set SKPOS with a predetermined interval.

[0107] In an embodiment, the hopping ordered set comparator 173 may compare the count value CNT_INTERVAL with a reference value CNT_REF corresponding to a predetermined interval.

[0108] In an embodiment, the reference value CNT_REF may include a first reference value for determining whether the receiving interval of the jump ordered set SKPOS is an interval corresponding to the first mode. For example, the interval corresponding to the first mode may be set to 261ns. When the first reference clock signal REFCLK1 is 125MHz, the first reference value may be 33. When the count value CNT_INTERVAL is less than 33, the receiving interval of the jump ordered set SKPOS may be an interval corresponding to the first mode. In other words, when the current receiving interval of the jump ordered set SKPOS is less than the first reference value, the first mode may be selected. The jump ordered set comparator 173 may output a signal corresponding to the first mode.

[0109] In addition, the reference value CNT_REF may include a second reference value for determining whether the receiving interval of the jump ordered set SKPOS is an interval corresponding to the second mode. The second reference value may be greater than the first reference value. For example, the time interval corresponding to the second mode may be set to 5 us. When the first reference clock signal REFCLK1 is 125MHz, the second reference value may be 525. When the count value CNT_INTERVAL is greater than 525, the receiving interval of the jump ordered set SKPOS may be an interval corresponding to the second mode. In other words, when the current receiving interval of the jump ordered set SKPOS is greater than the second reference value, the second mode may be selected. The jump ordered set comparator 173 may output a signal corresponding to the second mode.

[0110] The mode selector 174 may select any one of the first mode and the second mode based on the comparison result COMP_SKPOS and the state of the elastic buffer 150. In an embodiment, the mode selector 174 may include an AND gate circuit 174-1.

[0111] In an embodiment, mode selector 174 may receive comparison result COMP_SKPOS from hop ordered set comparator 173 and signal UNDER_FLOW indicating an underflow state from buffer state detector 160. Mode selector 174 may output a selected mode SEL_MODE to reference clock signal controller 180 in response to the received signals.

[0112] In an embodiment, when the mode selector 174 receives a signal corresponding to the first mode and the elastic buffer 150 is in an underflow state, the mode selector 174 may select the first mode.

[0113] In an embodiment, when the mode selector 174 receives a signal corresponding to the second mode or the elastic buffer 150 is not in an underflow state, the mode selector 174 may select the second mode.

[0114] Figure 5A is a block diagram showing an example in which a spread spectrum clock is activated based on an embodiment of the disclosed technology.

[0115] Reference Figure 4 and Figure 5A , data DATA consisting of a data set D_SET and a jump ordered set SKPOS can be input.

[0116] A count value CNT_INTERVAL corresponding to a reception interval of a hop-ordered set SKPOS may be calculated during a period from time T0 when a hop-ordered set is input to time T1 when a next hop-ordered set is input. The count value CNT_INTERVAL may be output by the hop-ordered set counter 172 as “m”.

[0117] When m is less than the first reference value, the skip ordered set comparator 173 may output a high level comparison result COMP_SKPOS.

[0118] The mode selector 174 may receive a signal UNDER_FLOW indicating an underflow state from the buffer state detector 160. When the signal UNDER_FLOW indicating an underflow state is enabled at a high level, the elastic buffer 150 may be in an underflow state.

[0119] Since all input signals have a high level, the mode selector 174 may select the first mode by outputting a selected mode SEL_MODE of a high level.

[0120] Figure 5B is a diagram showing an example in which a spread spectrum clock is deactivated according to an embodiment of the disclosed technology.

[0121] Reference Figure 4 and Figure 5B , data DATA including a data set D_SET and a jump ordered set SKPOS can be input.

[0122] A count value CNT_INTERVAL corresponding to a reception interval of a hop-ordered set SKPOS may be calculated during a period from time T0' when a hop-ordered set is input to time T1' when a next hop-ordered set is input. The hop-ordered set counter 172 may output a count value CNT_INTERVAL of "n".

[0123] When n is greater than the second reference value, the skip ordered set comparator 173 may output a low level comparison result COMP_SKPOS.

[0124] Since the comparison result COMP_SKPOS is at a low level even when the signal UNDER_FLOW indicating the underflow state is at a high level, the mode selector 174 may select the second mode by outputting the selection mode SEL_MODE of a low level.

[0125] Figure 6 is a flow chart illustrating a method of operating a PCIe device based on an embodiment of the disclosed technology. Figure 6 The method can be used, for example, Figure 1 The PCIe device 100 shown is used for implementation.

[0126] Reference Figure 6 , at S601 , the PCIe device 100 may generate a first reference clock signal.

[0127] In S603 , the PCIe device 100 may detect a second reference clock signal of the host 200 .

[0128] At S605 , the PCIe device 100 may compare the first reference clock signal with the second reference clock signal.

[0129] In an embodiment, the PCIe device 100 may select any one of the common clock mode and the separate clock mode based on the comparison result of the first reference clock signal and the second reference clock signal. For example, the PCIe device 100 may select any one of the common clock mode and the separate clock mode in response to the first switching of the reset signal received from the host 200.

[0130] At S607 , the PCIe device 100 may determine whether the second reference clock signal is provided from the host 200 based on a comparison result of the first reference clock signal and the second reference clock signal.

[0131] When it is determined as a result of the determination of S607 that the second reference clock signal is provided from the host 200, the PCIe device 100 may perform step S609. At S609, the PCIe device 100 may select the second reference clock signal according to the common clock mode.

[0132] When it is determined as a result of the determination of S607 that the second reference clock signal is not provided from the host 200, the PCIe device 100 may perform step S611. At S611, the PCIe device 100 may select the first reference clock signal according to the individual clock mode.

[0133] At S613 , the PCIe device 100 may determine whether to apply spread spectrum clocking to the first reference clock signal based on the reception interval of the hop ordered set and the state of the elastic buffer 150 .

[0134] Figure 7is a flow chart illustrating an example method of operating a PCIe device to determine whether to activate spread spectrum clocking based on an embodiment of the disclosed technology. In an embodiment, Figure 7 You can specify Figure 6 Step S613. Figure 7 The method can be used, for example, Figure 1 The PCIe device 100 shown is used for implementation.

[0135] Reference Figure 7 , at S701 , the PCIe device 100 may receive a data set and a jump ordered set from the host 200 based on a first reference signal in response to a separate clock mode.

[0136] At S703 , the PCIe device 100 may store the data set and the jump ordered set in the elastic buffer 150 .

[0137] At S705, the PCIe device 100 may determine whether the reception interval of the hop ordered set is shorter than the first interval. For example, the PCIe device 100 may compare the reception interval with a predetermined first interval. The first interval may correspond to a first reference value.

[0138] When it is determined as a result of the determination in S705 that the reception interval of the hop-ordered set is shorter than the first interval, the PCIe device 100 may perform step S707 .

[0139] At S707 , the PCIe device 100 may detect the status of the elastic buffer 150 .

[0140] At S709 , the PCIe device 100 may determine whether the elastic buffer 150 is in an underflow state.

[0141] When it is determined that the elastic buffer 150 is in the underflow state as a result of the determination in S709 , the PCIe device 100 may perform step S711 .

[0142] At S711 , the PCIe device 100 may activate application of spread spectrum clocking.

[0143] On the other hand, when the reception interval of the hop ordered sets is not shorter than the first interval, or when it is determined as a result of the determination of S709 that the elastic buffer 150 is not in the underflow state, the PCIe device 100 may perform step S713 .

[0144] At S713 , the PCIe device 100 may disable application of the spread spectrum clock.

[0145] Figure 8 is a flowchart illustrating another example method of operating a PCIe device to determine whether to activate spread spectrum clocking based on an embodiment of the disclosed technology. In an embodiment, Figure 8 You can specify Figure 6 Step S613. Figure 8 The method can be used, for example, Figure 1 The PCIe device 100 shown is used for implementation.

[0146] Reference Figure 8 , at S801 , the PCIe device 100 may receive a data set and a jump ordered set from the host 200 based on a first reference signal in response to a separate clock mode.

[0147] At S803 , the PCIe device 100 may store the data set and the jump ordered set in the elastic buffer 150 .

[0148] At S805, the PCIe device 100 may determine whether the reception interval of the hop ordered set is longer than the second interval. For example, the PCIe device 100 may compare the reception interval and the predetermined second interval with each other. The second interval may correspond to a second reference value.

[0149] When it is determined as a result of the determination in S805 that the reception interval of the jump ordered set is longer than the first interval, the PCIe device 100 may perform step S807 .

[0150] At S807 , the PCIe device 100 may disable application of the spread spectrum clock.

[0151] On the other hand, when it is determined as a result of the determination in S807 that the reception interval of the jump ordered sets is not longer than the second interval, the PCIe device 100 may terminate the process.

[0152] Fig. 9 is a flow chart illustrating an example of activating application of spread spectrum clocking according to link status based on an embodiment of the disclosed technology.

[0153] Reference Fig. 9 , Fig. 9 Link states of the PCIe device 100 , such as a detection (DETECT) state, a polling (POLLING) state, a configuration (CONFIGURATION) state, a hot reset (HOT RESET) state, a disabled state (DISABLED), and an L0 state are shown.

[0154] The detection state may refer to an initial state after power-on or reset. In addition, the link state of the PCIe device may enter this state from the states described below. For example, the PCIe device may enter the detection state from the configuration state, hot reset state, disabled state, L2 state, loopback state, and recovery state. In the detection state, all logic, ports, and registers may be reset, and the link connected to the PCIe interface may be detected. In other words, in the detection state, a physically connected lane may be searched.

[0155] In the polling state, channels capable of data communication can be distinguished from detected channels. In the polling state, the clocks at both ends of the PCIe interface can be synchronized, the polarity of the channel can be confirmed to be D+ or D-, and the data transmission speed available for the channel can be checked. In other words, in the polling state, polarity reversal can be checked. In addition, a link in the polling state can enter the detection state or the configuration state.

[0156] In the configuration state, the connection state of the channel can be checked. More specifically, in the configuration state, the channel width capable of data communication can be determined. In addition, in the configuration state, channel reversal can be checked. The PCIe device 100 can enter the configuration state from the polling state. However, optionally, after entering the L0 state, the PCIe device 100 can enter the configuration state in the case of "channel reduction" and "channel width increase".

[0157] The recovery state can be used to reconfigure the link bandwidth. In the recovery state, the link bandwidth of the set link can be changed, and the bit lock, symbol lock, and lane-to-lane de-skew can be reset. When an error occurs in the L0 state, the recovery state can be entered. Thereafter, after the error is recovered in the recovery state, the state can be changed to the L0 state. In addition, in an embodiment, in the recovery state, an equalization operation of the link can be performed.

[0158] The L0 state may be a normal operating state in which data and packets are sent and received over a link. More specifically, the L0 state may be an operating state of a physical bus interface that sends and receives data and control packets. The L0 state may be a fully active state.

[0159] The L0s state may refer to a state in which a physical bus interface quickly enters a power saving state and recovers from the power saving state without going through a recovery state. The L0s state may be a power saving state. The L0s state may refer to an idle or standby state of certain functions in the interface.

[0160] The L1 state may be a power saving state. The L1 state may refer to a state that further increases power saving compared to the L0s state. The L1 state may be a low power standby state.

[0161] The L2 state can be a power saving state that actively saves power. Most transmitters and receivers can be turned off. Although the main power supply and clock are not guaranteed, auxiliary power can be provided. The L2 state can be a low-power sleep state, and most functional modules are not powered.

[0162] The loopback state can be used for testing and fault isolation. The loopback state can be operated on a channel-by-channel basis only. In the loopback state, the loopback receive channel can be selected and configured.

[0163] The disabled state may allow the provisioning link to be disabled until instructed.

[0164] The hot reset state can be triggered only by the downstream port. The downstream port can use a training sequence (e.g., TS1 or TS2) to propagate the hot reset. The training sequence TS can consist of an ordered set for initializing bit alignment, symbol alignment, and physical layer parameter exchange. In some embodiments of the disclosed technology, the term "training sequence" can be used to indicate a "training sequence ordered set."

[0165] In an embodiment, when changing the speed from the Gen1 state where the PCIe device 100 operates at a rate of 2.5 GT / s to the Gen3 state where the PCIe device 100 operates at a rate of 8 / 16 / 32 Gt / s, the PCIe device 100 may activate application of the SRIS mode or the SRNS mode determined by the spread spectrum clock selection circuit 170 .

[0166] For example, the PCIe device 100 may switch back and forth between the L0 state and the recovery state to change the speed. The PCIe device 100 may activate or deactivate the application of the spread spectrum clock according to the determined mode.

[0167] Fig.10 FIG. 1 is a flowchart showing another example of an application of activating a spread spectrum clock according to a link state based on an embodiment of the disclosed technology. Fig.10 , the PCIe device 100 may operate in the single clock mode according to the determination of the reference clock signal selection circuit 140. When the host 200 operates in the SRIS mode and the PCIe device 100 operates in the default mode SRNS, a link disconnection may occur.

[0168] In an embodiment, when the PCIe device 100 enters the polling state after a link is disconnected, application of the SRIS mode or the SRNS mode determined by the spread spectrum clock selection circuit 170 may be activated.

[0169] For example, when entering the "polling.active" and "polling.configuration" states, the spread spectrum clock selection circuit 170 can determine that the host 200 operates in the SRIS mode. The PCIe device 100 can activate the application of the spread spectrum clock according to the determined SRIS mode. When the link is attempted again through the detection state after timeout from the "polling.active" and "polling.configuration" states, the PCIe device 100 can operate normally.

[0170] Fig.11 is a diagram showing an example in which a spread spectrum clock is activated based on an embodiment of the disclosed technology.

[0171] Reference Fig.11, the host 200 can operate in SRIS mode.

[0172] The PCIe device 100 may determine the single clock mode through the reference clock signal selection circuit 140, and may determine whether to activate the spread spectrum clock through the spread spectrum clock selection circuit 170. The PCIe device 100 may initially operate in the SRNS mode, but may determine through the spread spectrum clock selection circuit 170 that the host 200 operates in the SRIS mode. Fig. 9 or Fig.10 At the time described, the PCIe device 100 may operate in the SRIS mode according to the determination of the spread spectrum clock selection circuit 170 .

[0173] Therefore, when the PCIe device 100 operates in the single clock mode, the interval of the jump ordered set SKPOS can be checked after power-on to be consistent with the above reference. Fig. 9 or Fig.10 Whether to activate the spread spectrum clock operation of the PCIe device 100 is detected by detecting whether a change occurs within a time corresponding to the described link state. The interval of the hop ordered set SKPOS can be detected by various types of protocol analyzers (PA).

[0174] Fig.12 is a diagram showing a PCIe system 1000 based on an embodiment of the disclosed technology.

[0175] Fig.12 The PCIe device 1100 and the host 1200 shown may refer to Figure 1 A PCIe device 100 and a host 200.

[0176] Reference Fig.12 , the PCIe system 1000 may include a PCIe device 1100 and a host 1200 .

[0177] The PCIe device 1100 and the host 1200 may include a first PCIe controller 1110 and a second PCIe controller 1210 , respectively.

[0178] The first PCIe controller 1110 and the second PCIe controller 1210 may have the same structure. Therefore, description will be made based on the first PCIe controller 1110.

[0179] The first PCIe controller 1110 may include a PCIe interface. The PCIe layer included in the PCIe interface may include three discrete logical layers. For example, the PCIe interface may include a transaction layer, a data link layer, and a physical layer. Each layer may include two parts. One part may process outbound information (or information to be transmitted), and the other part may process inbound information (or received information). In addition, the first PCIe controller 1110 may use data packets to communicate information between one PCIe interface and another PCIe interface.

[0180] The upper layer of the PCIe interface may be a transaction layer. The transaction layer may assemble or decompose a transaction layer data packet TLP. In addition, the transaction layer may implement a split transaction, i.e., a transaction for transmitting other traffic to the link while the target system is collecting data required for the response. For example, the transaction layer may implement a transaction in which the request and response are separated in time. In an embodiment, the four transaction address spaces may include a configuration address space, a memory address space, an input / output address space, and a message address space. The memory space transaction may include at least one of a read request and a write request for transmitting data from or to a memory mapped location. In an embodiment, the memory space transaction may use two different address formats, for example, a short address format such as a 32-bit address and a long address format such as a 64-bit address. The configuration space transaction may be used to access the configuration space of the PCIe device 1100. Transactions for the configuration space may include a read request and a write request. Message space transactions (or messages) may be defined to support in-band communication between PCIe devices.

[0181] The transaction layer may store link configuration information, etc. Further, the transaction layer may generate a transaction layer packet (TLP), or may convert a TLP received from an external device into a payload or status information.

[0182] The middle layer in the PCIe interface structure can be a data link layer, which can act as an intermediate level between the transaction layer and the physical layer. The data link layer can mainly perform link management functions and data integrity functions including error detection and error correction. Specifically, the transmitting side of the data link layer can accept the TLP assembled by the transaction layer, assign a data protection code to the TLP, and calculate the TLP sequence number of the TLP. In addition, the transmitting side of the data link layer can send the data protection code and the TLP sequence number to the physical layer so as to send the corresponding information through the link. The receiving side of the data link layer can check the data integrity of the TLP received from the physical layer and send the TLP to the transaction layer for additional processing.

[0183] The physical layer may include circuits for performing interface operations, such as a driver, an input buffer, a serial-to-parallel conversion circuit, a parallel-to-serial conversion circuit, a phase-locked loop (PLL), and an impedance matching circuit.

[0184] Further, the physical layer may include a logical sub-block and an electrical sub-block for physically transmitting data packets to an external PCIe device (e.g., host 1210). The logical sub-block may play the necessary role to perform the "digital" functions of the physical layer. In this regard, the logical sub-block may include: a transmitting portion for preparing information to be sent by the physical sub-block; and a receiving portion for identifying and preparing received information before transmitting the received information to the data link layer. The physical layer may include a transmitter and a receiver. The transmitter may receive symbols serialized by the transmitter through the logical sub-block and sent to an external device. In addition, the receiver may receive the serialized symbols from the external device and convert the received symbols into a bit stream. The receiver may refer to Figure 1 The physical layer may be configured to receive a data packet received from the data link layer and to provide a bit stream to the logical sub-block. The physical layer may be configured to receive a bit stream received from the data link layer and to provide a bit stream to the logical sub-block. That is, the physical layer may convert the TLP received from the data link layer into a serialized format, and may convert the data packet received from the external device into a deserialized format. In addition, the physical layer may include logic functions related to interface initialization and maintenance.

[0185] In an embodiment, Figure 1 The receiver 110, the reference clock signal detector 130, the reference clock selection circuit 140, the elastic buffer 150, the buffer state detector 160, the spread spectrum clock selection circuit 170 and the reference clock signal controller 180 shown may be included in Fig.12 In the physical layer of the PCIe device 1100 shown. Fig.12 , the first reference clock signal generator 120 is illustrated as being included outside the physical layer of the PCIe device 1100. However, in an embodiment, the first reference clock signal generator 120 may be included in the physical layer of the PCIe device 1100.

[0186] In an embodiment, Figure 1 The transmitter 210 shown may include Fig.12 In the physical layer of the host 1200 shown. Fig.12 , the second reference clock signal generator 220 is illustrated as being included outside the physical layer of the host 1200. However, in an embodiment, the second reference clock signal generator 220 may be included in the physical layer of the host 1200.

[0187] According to another embodiment, Figure 1 The reference clock signal selection circuit 140 and the spread spectrum clock selection circuit 170 shown may be included in Fig.12The physical layer of the PCIe device 1100 is shown as outside. The physical layer of the PCIe device 1110 may include a receiver 110 , a reference clock signal detector 130 , an elastic buffer 150 , a buffer status detector 160 , and a reference clock signal controller 180 .

[0188] exist Fig.12 , the structures of the first PCIe controller 1110 and the second PCIe controller 1210 are illustrated. However, the first PCIe controller 1110 and the second PCIe controller 1210 may include any structure, such as a quick path interconnect structure, a next generation high performance computing interconnect structure, or another hierarchical structure.

[0189] In this way, interface devices such as PCIe devices based on some embodiments of the disclosed technology can smoothly perform the operation of automatically selecting a clock mode between a common clock mode or a separate clock mode when multiple reset signals are enabled, can automatically determine whether to apply a spread spectrum clock, and can provide a method for operating a PCIe device.

[0190] The disclosure in U.S. patent application Ser. No. 17 / 081,595, filed on Oct. 27, 2020, is incorporated herein by reference in its entirety.

[0191] In an embodiment, the device may provide an interface device that is capable of adaptively determining transmission parameters based on link characteristics of US Patent Application No. 17 / 081,595, which is incorporated herein by reference in its entirety.

[0192] The disclosure in U.S. patent application Ser. No. 17 / 350,945, filed on June 17, 2021, is incorporated herein by reference in its entirety.

[0193] In an embodiment, a device may provide a peripheral component interconnect express (PCIe) device capable of controlling a computing system including a PCIe device of U.S. patent application Ser. No. 17 / 350,945, which is incorporated herein by reference in its entirety, and lane margining operations in an upstream port.

[0194] The disclosure in U.S. patent application Ser. No. 17 / 350,885, filed on June 17, 2021, is incorporated herein by reference in its entirety.

[0195] In an embodiment, the apparatus may provide an improved Peripheral Component Interconnect Express (PCIe) interface and an interface system including the PCIe interface of US Patent Application No. 17 / 350,885, which is incorporated herein by reference in its entirety.

[0196] The embodiments and implementations disclosed above are merely examples, and various improvements and changes may be made to the disclosed embodiments and implementations and other embodiments and implementations based on the contents described and illustrated in this patent document.

Claims

1. A device for communicating with a host device via an interface, comprising: a clock signal generator that generates a first reference clock signal to be used by the apparatus; as well as a reference clock signal selection circuit connected to communicate with the clock signal generator to receive the first reference clock signal and receive a second reference clock signal from the host device, and in response to a first reset signal first received among a plurality of reset signals from the host device, selects one of the first reference clock signal and the second reference clock signal according to whether the second reference clock signal is provided from the host device.

2. The device according to claim 1, wherein: The first reset signal is a reset signal first received from the host device after selecting a reference clock signal before the reference clock signal selection circuit selects one of the first reference clock signal and the second reference clock signal.

3. The device according to claim 2, wherein: The reference clock signal selection circuit includes a selection circuit controller that generates a control signal to select one of the first reference clock signal and the second reference clock signal in response to the first reset signal and a physical layer initialization signal.

4. The device according to claim 3, wherein: The physical layer initialization signal is enabled until one of the first reference clock signal and the second reference clock signal is selected and an initial register value of the physical layer is set.

5. The device according to claim 4, wherein: The selection circuit controller, upon receiving a different reset signal other than the first reset signal, blocks an operation caused by the different reset signal until one of the first reference clock signal and the second reference clock signal is selected and an initial register value of the physical layer is set. 6 . The apparatus of claim 3 , further comprising a reference clock signal detector that detects the second reference clock signal.

7. The device according to claim 6, wherein: The reference clock signal selection circuit further comprises: a detection signal generator, generating a detection signal in response to the control signal when the second reference clock signal is detected; a first counter that determines a number of toggling times of the first reference clock signal and generates a first count value corresponding to the number of toggling times of the first reference clock signal in response to the control signal; A second counter: determining the number of switching times of the second reference clock signal, and generating a second count value corresponding to the number of switching times of the second reference clock signal in response to the control signal; a reference clock signal comparator to compare the first count value with the second count value; and A reference clock signal selector selects one of the first reference clock signal and the second reference clock signal based on a comparison result between the detection signal and the reference clock signal comparator.

8. A device for communicating with a host device via an interface, comprising: A receiver, receiving a data set and a jump ordered set (SKPOS) from the host device based on a first reference clock signal; an elastic buffer coupled to the receiver and storing the data set and the jump ordered set; a buffer state detector coupled to the elastic buffer and detecting a state of the elastic buffer; as well as A spread spectrum clock selection circuit is coupled to the receiver and determines whether to activate a spread spectrum clock (SSC) based on a reception interval of receiving the hop ordered set and a state of the elastic buffer.

9. The device according to claim 8, wherein: The spread spectrum clock selection circuit comprises: a hopping ordered set detector, detecting the hopping ordered set received by the receiver; a hop ordered set counter to determine a number of toggles of the first reference clock signal upon receiving the hop ordered set; and to generate a count value corresponding to the number of toggles of the first reference clock signal during the reception interval; a skip ordered set comparator, comparing the count value with a predetermined reference value; and a mode selector, which selects one of a first mode and a second mode based on a comparison result of the jump ordered set comparator and a state of the elastic buffer, Wherein, in the first mode, the spread spectrum clock is activated, and in the second mode, the spread spectrum clock is deactivated.

10. The device according to claim 9, wherein: When the jump ordered set comparator determines that the count value is less than a first reference value, the jump ordered set comparator outputs a signal corresponding to the first mode; or, when the jump ordered set comparator determines that the count value is greater than a second reference value, the jump ordered set comparator outputs a signal corresponding to the second mode, and the second reference value is greater than the first reference value.

11. The device according to claim 10, wherein: The mode selector receives a signal corresponding to the first mode and selects the first mode if the elastic buffer is in an underflow state.

12. The device according to claim 10, wherein: The mode selector receives a signal corresponding to the second mode from the hop ordered set comparator or selects the second mode if the elastic buffer is not in an underflow state. 13 . The apparatus of claim 8 , further comprising a clock signal generator that generates the first reference clock signal.

14. The device according to claim 13, wherein: The first reference clock signal is different from a second reference clock signal generated by the host device.

15. The apparatus of claim 8, further comprising a reference clock signal generator that generates a target reference clock signal with spread spectrum from the first reference clock signal when the spread spectrum clock is activated.

16. A method of operating an interface device for communicating with a host device, comprising: generating a first reference clock signal; selecting one of a common clock mode and a separate clock mode based on a comparison between a first reference clock signal generated by the interface device and a second clock signal received from the host device; receiving a data set and a jump ordered set (SKPOS) from the host device based on the first reference clock signal according to the single clock mode; storing the data set and the jump ordered set in an elastic buffer; as well as Whether to apply spread spectrum clocking (SSC) to the first reference clock signal is determined based on a reception interval of receiving the hop ordered set and a state of the elastic buffer.

17. The method according to claim 16, wherein: Selecting one of the common clock mode and the individual clock mode is performed in response to an initial toggle of a reset signal received from the host device.

18. The method according to claim 16, wherein: Determining whether to apply the spread spectrum clock includes: comparing the received interval with a predetermined first interval; In response to the receiving interval being shorter than the predetermined first interval, detecting a state of the elastic buffer; and In response to detecting that the elastic buffer is in an underflow state, application of the spread spectrum clock is activated.

19. The method according to claim 16, wherein: Determining whether to apply the spread spectrum clock includes: comparing the received interval with a predetermined second interval; and In response to the reception interval being longer than the predetermined second interval, application of the spread spectrum clock is deactivated.

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