A random stimulus generation method, system and device for chip verification testing

Abstract

The present application discloses a method, system and device for generating random stimuli for chip verification testing, which relates to the field of chip verification technology. The method comprises: determining the priority of all variables in the stimulus according to the constraint conditions of the stimulus required for the verification test case of the chip to be tested; detecting whether there is an inequality constraint in the constraint conditions, and if so, replacing the inequality constraint with a unified representation and executing subsequent steps, otherwise directly executing subsequent steps; based on the priority of the variable, finding the intersection of all relevant constraints of each variable in the constraint conditions, converting all relevant constraints of each variable into a range constraint, thereby generating optimized constraint conditions; based on the optimized constraint conditions, randomizing the variables from high to low according to their priority, thereby obtaining the random stimuli required for the verification test case of the chip to be tested.

Description

Technical Field

[0001] The present application belongs to the field of chip verification technology, and specifically relates to a random stimulus generation method, system and device for chip verification testing. Background Art

[0002] In chip verification technology, one of the core functions of the verification platform is to generate random stimuli and input the random stimuli into the object under test, thereby evaluating the performance or quality of the object under test by monitoring the difference between the output of the object under test and the expected output.

[0003] Currently, as chip sizes continue to grow, the scale of test cases is also increasing, and the number and range of random stimulus points are also expanding. If only stimuli are generated without effectively constraining them, verification time will be greatly increased, even exponentially, until the final result cannot be obtained. It may also generate many invalid stimuli, which will consume verification time and reduce chip verification efficiency. Therefore, in chip verification, it is necessary not only to generate stimuli but also to constrain them. In practical applications, based on whether the range is determined, the constraints of random stimuli can be divided into the following categories:

[0004] One is the constant range constraint, for example:

[0005] a: [1:100] / / a is randomly between 1 (inclusive) and 100 (inclusive);

[0006] b: [100:3000] / / b is randomly between 100 (inclusive) and 3000 (inclusive);

[0007] c: [90:700] / / i.e. c is randomly between 90 (inclusive) and 700 (inclusive);

[0008] As shown in the above example, this constraint causes the variables to be randomly distributed within their respective ranges, and there is no correlation between the variables, and they are independent of each other.

[0009] The second is the variable expression range constraint, for example:

[0010] a: [-100: b+c] / / a is random between -100 (inclusive) and b+c (inclusive);

[0011] b: [64:1522-c] / / b is random between 64 (inclusive) and 1522-c (inclusive);

[0012] c: [2:100] / / c is randomly between 2 (inclusive) and 100 (inclusive);

[0013] As shown in the above example, the variables in this constraint are related to and constrained with each other.

[0014] The third is inequality constraints, for example:

[0015] a+b+3c<=300 / / The random result must satisfy this inequality;

[0016] a+b>=100 / / The random result must satisfy this inequality;

[0017] As shown in the above example, the variables of this constraint no longer change independently, but are constrained to each other in the random process.

[0018] In practical applications, the constraints for random stimuli are any combination of the three aforementioned constraint forms. It's important to note that the variables used in chip verification all have fixed data types. Input stimuli are all integers or combinations of integers, and decimals or other data types can be converted to integers.

[0019] Existing constraint-based random stimulus generation technologies mainly include: (1) first randomize according to the range, then bring in the constraints. If the constraints are met, the randomization succeeds; if not, the randomization fails, and then randomizes until it succeeds. However, when the constraints are complex, this method may require a large amount of randomization to obtain a compliant solution, which consumes a lot of verification time and reduces chip verification efficiency. (2) first randomize according to the range, then bring the random result into the constraints. If the constraints are met, the randomization succeeds; if not, the correction algorithm is used to correct the result to meet the constraints. However, this method requires a separate correction algorithm to be designed for each constraint. When the constraints are complex or dynamically changing, the algorithm design difficulty and execution complexity are significantly increased. Summary of the Invention

[0020] In order to solve the problems existing in random technology under existing constraints, the present application proposes a random stimulus generation method, system and device for chip verification testing.

[0021] This application is implemented through the following technical solutions:

[0022] A method for generating random stimuli for chip verification testing, the method comprising:

[0023] Determine the priority of all variables in the stimulus according to the constraint conditions of the stimulus required by the test case for verifying the chip under test; the constraint conditions include at least one of a constant range constraint, a variable expression range constraint, and an inequality constraint;

[0024] Detect whether there is an inequality constraint in the constraint condition; if so, replace the inequality constraint with a unified representation and then execute the subsequent steps; otherwise, directly execute the subsequent steps; the unified representation of the inequality constraint is a form represented by ">=" and / or "<=";

[0025] Based on the priority of the variables, the intersection of all the related constraints of each variable in the constraint condition is obtained, and all the related constraints of each variable are converted into a range constraint, thereby generating an optimized constraint condition;

[0026] Based on the optimized constraint conditions, the variables are randomly assigned from high to low priority, thereby obtaining the random stimulus required for the verification test case of the chip under test.

[0027] In some embodiments, the priority of the variables is determined as follows:

[0028] The variables are prioritized according to the range constraints in the constraints. The following conditions must be met during the sorting process:

[0029] The relying party has a lower priority than the dependent party;

[0030] The principle of independent changes having the highest priority;

[0031] When two or more variables have the same priority, they are sorted in alphabetical order;

[0032] When a dependency loop occurs, the entire random constraint has no solution, and feedback is sent to the client to modify the requirements.

[0033] When a variable depends on itself, the entire random constraint has no solution, and feedback is sent to the client to modify the requirements.

[0034] In some embodiments, the priority-based constraint analysis involves finding the intersection of all relevant constraints for each variable in the constraint condition, converting all relevant constraints for each variable into a range constraint, and thereby generating an optimized constraint condition, specifically including:

[0035] Simplify the constraints to generate new inequality constraints, and substitute the generated new inequality constraints into the range constraints of the constraints to obtain a first simplification result;

[0036] Simplifying the result of the first simplification to generate a new inequality constraint, substituting the generated new inequality constraint into the result of the first simplification to obtain a second simplification result;

[0037] This process continues until no new inequality constraints can be generated by simplification. The simplification ends and the result of the last simplification is the optimized constraint condition.

[0038] Among them, in each simplification process, low priority must depend on high priority.

[0039] In some embodiments, the step of finding the intersection of all relevant constraints for each variable in the constraint condition based on the variable priority, converting all relevant constraints for each variable into a range constraint, and thereby generating the optimized constraint condition, further includes:

[0040] In each simplification process, the inequality constraints that always hold true are discarded.

[0041] In some embodiments, the step of finding the intersection of all relevant constraints for each variable in the constraint condition based on the variable priority, converting all relevant constraints for each variable into a range constraint, and thereby generating the optimized constraint condition, further includes:

[0042] When an inequality constraint that is always invalid appears during the simplification process, feedback is given to the client to modify the requirements.

[0043] In some embodiments, the optimization-based constraint conditions are used to randomly select variables from high to low priority, specifically including:

[0044] Randomize the variable with the highest priority to obtain the random value of the variable with the highest priority;

[0045] Based on the random value of the edge with the highest priority, the variable with the second highest priority is randomized to obtain the random value of the variable with the second highest priority, and so on, to obtain the random values of all variables in sequence.

[0046] In some embodiments, before the step of determining the priorities of all variables in the stimulus according to the constraints of the stimulus required for the chip under test verification test case, the method further includes:

[0047] Check whether there is an "or" constraint in the constraint conditions. If so, split the constraint conditions into parallel constraint conditions, and randomly select a group of constraint conditions from the parallel constraint conditions for subsequent processing.

[0048] In a second aspect, the present application proposes a random stimulus generation system for chip verification testing, the system comprising:

[0049] a priority sorting unit, wherein the priority sorting unit determines the priority of all variables in the stimulus according to the constraint conditions of the stimulus required by the test case for verifying the chip under test, wherein the constraint conditions include at least one of a constant range constraint, a variable expression range constraint, and an inequality constraint;

[0050] A normalization unit, the normalization unit is used to detect whether there are inequality constraints in the constraint conditions, and if so, drive the simplification conversion unit to work after equivalently replacing all inequality constraints with a unified representation; otherwise, directly drive the simplification conversion unit to work; the unified representation of the inequality constraints is a form represented by ">=" and / or "<=";

[0051] a simplification conversion unit, wherein the simplification conversion unit calculates the intersection of all relevant constraints of each variable in the constraint condition based on the priority of the variable, converts all relevant constraints of each variable into a range constraint, and thereby generates an optimized constraint condition;

[0052] And, a first random unit, which is based on the optimized constraint conditions and randomly selects variables from high to low priority, thereby obtaining the random stimulus required for the verification test case of the chip under test.

[0053] In some embodiments, the system further comprises:

[0054] a splitting unit, wherein when detecting that an "or" constraint exists in the constraint condition, the splitting unit splits the constraint condition into parallel constraint conditions;

[0055] and a second random unit, which randomly selects a set of inputs from the parallel constraints to the priority ranking unit.

[0056] In a third aspect, the present application proposes a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0057] The present application proposes a random stimulus generation method, system and device for chip verification testing. According to the range constraints in the constraint conditions, the priority of each variable is determined, and all constraints in the constraint conditions are simplified to obtain the intersection, and all relevant constraints of each variable in the constraint conditions are converted into a range constraint, so as to obtain a constraint condition consisting only of the range constraints of each variable. After that, random values of all variables can be directly obtained by performing random operations one by one according to the priority, without repeated random operations or setting up additional revision algorithms, thus avoiding large consumption of CPU and memory, and improving computing efficiency and chip testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The drawings described herein are used to provide a further understanding of the embodiments of the present application, constitute a part of the present application, and do not constitute a limitation of the embodiments of the present application. In the drawings:

[0059] Figure 1 A schematic diagram of the flow of the random stimulus generation method proposed in an embodiment of the present application;

[0060] Figure 2 This is a diagram of the measured results of the embodiment of the present application;

[0061] Figure 3 This is a functional block diagram of the random excitation generation system proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0062] In order to make the objectives, technical solutions and advantages of this application more clear, the present application is further described in detail below in conjunction with examples and drawings. The schematic implementation methods of this application and their descriptions are only used to explain this application and are not intended to limit this application.

[0063] Example: Existing random stimulus generation techniques for constrained conditions cannot determine in advance whether the constraints have solutions. A conclusion can only be drawn during actual execution through repeated iterative calculations. This iterative calculation process is very time-consuming and consumes a large amount of CPU and memory. Furthermore, using optimization algorithms to modify random results to meet the constraints requires the design of additional complex algorithms, which also consumes a large amount of CPU and memory. To address this issue, this example proposes a random stimulus generation method for chip verification testing.

[0064] Specific as Figure 1 As shown, the method proposed in this embodiment includes the following steps:

[0065] Step 1: Determine the priority of all variables in the stimulus based on the constraints of the stimulus required for the chip under test verification test case. In this embodiment, variables represent elements used to generate stimulus signals. They can generate stimulus signals independently or in combination with other variables. For example, when verifying an adder, a variable can directly generate a stimulus signal; however, when verifying a network card, dozens of variables may be required to combine and generate a stimulus signal.

[0066] Step 2: Check whether there are inequality constraints in the constraints. If so, replace the inequality constraints with a unified representation and then execute the subsequent steps. Otherwise, execute the subsequent steps directly. The constraints required for verification of the stimulus by the chip verification test case include at least one of the constant range constraints, variable expression range constraints, and inequality constraints. Among the inequality constraints, the comparison symbols that can be used include "==", ">", ">=", "<", "<=", "!=", etc. The inequality constraints are and relationships, that is, the random results need to satisfy all inequality constraints. To facilitate subsequent simplification, first convert the inequality constraints represented by different comparison symbols into a unified representation of ">=" and / or "<=". Of course, if they are represented by ">=" or "<=", there is no need to perform equivalent replacement. For example, X+Y==m is equivalent to X+Y>=m and X+Y<=m; X+Y>n is equivalent to X+Y>=n+1; X+Y<1 is equivalent to X+Y<=0; X+Y!=m is equivalent to X+Y<20 || X+Y>20, which is equivalent to X+Y<=19|| X+Y>=21.

[0067] Step 3: Based on the priority of the variables, the intersection of all relevant constraints of each variable in the constraint condition is calculated, and all relevant constraints of each variable are converted into a range constraint, thereby generating the optimized constraint condition.

[0068] Step 4: Based on the optimized constraints, randomize the variables from high to low priority to obtain the random stimulus required for the verification test case of the chip under test.

[0069] In an optional implementation, step 1 specifically prioritizes variables based on the range constraints (including constant range constraints and variable expression range constraints) in the constraint conditions, and needs to satisfy the following conditions:

[0070] (1) The relying party has a lower priority than the dependent party;

[0071] (2) The principle of giving highest priority to independent changes;

[0072] (3) When two or more variables have the same priority, they are sorted in alphabetical order;

[0073] (4) When a dependency loop occurs, the entire random constraint has no solution, and feedback is sent to the client to modify the requirements;

[0074] (5) The variable cannot depend on itself, otherwise the entire random constraint will have no solution. At this time, feedback is given to the client to modify the requirements.

[0075] For example, the verification stimulus required for test case 1 includes three variables a, b, and c, and its constraints include:

[0076] a : [-100 : b + c]

[0077] b : [64 : 1522 - c]

[0078] c : [2 : 100]

[0079] a + b + 3c <= 300

[0080] a + b >= 100

[0081] From the above description, we can see that the constraints required for the verification stimulus of this test case 1 include range constraints and inequality constraints. Among them, according to the range constraints, we can determine:

[0082] According to a : [-100 : b + c], a depends on b and c;

[0083] According to b : [64 : 1522 - c], b depends on c;

[0084] According to c: [2: 100], c is independent.

[0085] Then, according to the above priority sorting method, it can be determined that c has the highest priority, and a has a lower priority than b. Therefore, the priority of all variables in the verification stimulus required for test case 1 can be determined as: c>b>a.

[0086] The verification stimulus required for test case 2 includes three variables a, b, and c, and its constraints include:

[0087] a : [b+10 : c-10]

[0088] b : [a : a+c]

[0089] c : [1:100]

[0090] According to the scope constraints of the verification stimulus required for the above test case 2, it can be determined that: a depends on b and c, b depends on c and a, and c is independent. Therefore, a loop is formed between variables a and b, and the entire random constraint has no solution. At this time, feedback needs to be provided to the client to modify the requirements in order to modify the constraints.

[0091] The verification stimulus required for test case three includes two variables a and b, and its constraints include:

[0092] a : [100:b+10]

[0093] b : [b:b+200]

[0094] According to the scope constraints of the verification stimulus required by the above test case three, it can be determined that: a depends on b, and b depends on b. In this case, a variable depends on itself, resulting in an unsolvable random constraint. At this time, feedback needs to be provided to the client to modify the requirements in order to modify the constraints.

[0095] In an optional implementation, the process of finding the intersection of all relevant constraints for each variable in step 3 is as follows:

[0096] First simplification: Based on the constraints, simplification generates new inequality constraints. During the simplification process, low-priority constraints must depend on high-priority constraints. For example, taking the constraints of the stimulus required for the above test case 1 as an example, new inequality constraints can be generated based on the constraints, as follows:

[0097] a:[-100:b+c] -->-100<=b+c -->b>=-100-c

[0098] b:[64:1522-c] -->64<=1522-c -->c<=1522-64

[0099] c:[2:100] -->2<=100

[0100] a+b+3c<=300 -->a<=300-b-3c

[0101] a+b>=100 -->a>=100-b

[0102] Here, c>=100-b cannot be generated, otherwise it will violate the priority principle.

[0103] Furthermore, if there are no variables on either side during the simplification process, the inequality constraint is either always true or always false. Inequality constraints that always hold can be discarded. However, if an inequality constraint that always fails holds, the entire random constraint has no solution. Feedback must be provided to the client for modification. For example, the always true inequality constraint 2<=100 in the above example can be discarded.

[0104] Substitute the four new inequality constraints generated by simplification into the range constraints of the original constraints, and the result of the first simplification is:

[0105] a:[max(-100,100-b):min(b+c,300-b-3c)]

[0106] b:[max(max(64,-100-c):1522-c]

[0107] c:[2:min(100,1522-64)]

[0108] For literal values, it can be further simplified to:

[0109] a:[max(-100,100-b):min(b+c,300-b-3c)]

[0110] b:[max(max(64,-100-c):1522-c]

[0111] c:[2:100]

[0112] Among them, the max() function is used to find the maximum value, and the min() function is used to find the minimum value. The input parameters can be one or more.

[0113] Second simplification: Based on the results of the first simplification, new inequality constraints can be generated as follows:

[0114] a:[max(-100,100-b):min(b+c,300-b-3c)]

[0115] -->-100<=b+c --> Already

[0116] -->-100<=300-b-3c -->b<=400-3c (new)

[0117] -->100-b<=b+c -->b>=(100-c) / 2 (New)

[0118] -->100-b<=300-b-3c -->c<=200 / 3 -->c<=66.7 -->c<=66 (new)

[0119] b:[max(max(64,-100-c):1522-c]

[0120] -->64<=1522-c --> Already

[0121] -->-100-c<=1522-c -->-100<=1522 --> Always true, discard

[0122] c:[2:100]

[0123] -->2<=100 --> Always true, discard

[0124] The simplification produces three new inequality constraints. Substituting them into the result of the first simplification, the result of the second simplification is:

[0125] a:[max(-100,100-b):min(b+c,300-b-3c)]

[0126] b:[max(max(64,-100-c,(100-c) / 2):min(1522-c,400-3c)]

[0127] c:[2:min(100,66)]

[0128] For literal values, it can be further simplified to:

[0129] a:[max(-100,100-b):min(b+c,300-b-3c)]

[0130] b:[ max(max(64,-100-c,(100-c) / 2):min(1522-c,400-3c)]

[0131] c:[2:66]

[0132] Third simplification: Based on the results of the second simplification, new inequality constraints can be generated as follows:

[0133] a:[max(-100,100-b):min(b+c,300-b-3c)]

[0134] -->-100<=b+c --> Already

[0135] -->-100<=300-b-3c --> Already

[0136] -->100-b<=b+c --> Already

[0137] -->100-b<=300-b-3c --> Already available

[0138] b:[ max(max(64,-100-c,(100-c) / 2):min(1522-c,400-3c)]

[0139] -->64<=1522-c --> Already

[0140] -->64<=400-3c -->c<=112 (new)

[0141] -->-100-c<=1522-c --> Already

[0142] -->-100-c<=400-3c -->c<=250 (New)

[0143] -->(100-c) / 2)<= 1522-c -->c<=2944 (new)

[0144] -->(100-c) / 2)<=400-3c -->c<=140 (new)

[0145] c:[2:66]

[0146] -->2<=66 --> Always true, discard

[0147] The simplification produces four new inequality constraints. Substituting them into the second simplification result, the third simplification result is:

[0148] a:[max(-100,100-b):min(b+c,300-b-3c)]

[0149] b:[ max(max(64,-100-c,(100-c) / 2):min(1522-c,400-3c)]

[0150] c:[2:min(66,112,250,2944,140]

[0151] For literal values, it can be further simplified to:

[0152] a:[max(-100,100-b):min(b+c,300-b-3c)]

[0153] b:[ max(max(64,-100-c,(100-c) / 2):min(1522-c,400-3c)]

[0154] c:[2:66]

[0155] Fourth simplification: Based on the results of the third simplification, no new inequality constraints can be generated by simplification, so the simplification ends here, as follows:

[0156] a:[max(-100,100-b):min(b+c,300-b-3c)]

[0157] -->-100<=b+c --> Already

[0158] -->-100<=300-b-3c --> Already

[0159] -->100-b<=b+c --> Already

[0160] -->100-b<=300-b-3c --> Already available

[0161] b:[ max(max(64,-100-c,(100-c) / 2):min(1522-c,400-3c)]

[0162] -->64<=1522-c --> Already

[0163] -->64<=400-3c --> Already

[0164] -->-100-c<=1522-c --> Already

[0165] -->-100-c<=400-3c --> Already

[0166] -->(100-c) / 2)<= 1522-c --> Already

[0167] -->(100-c) / 2)<=400-3c --> Already

[0168] c:[2:66]

[0169] -->2<=66 --> Always true, discard

[0170] Finally, the range constraints of each variable are obtained, and the optimized constraints are:

[0171] a:[max(-100,100-b):min(b+c,300-b-3c)]

[0172] b:[ max(max(64,-100-c,(100-c) / 2):min(1522-c,400-3c)]

[0173] c:[2:66].

[0174] In an optional implementation manner, the successive randomization process of step 4 is specifically as follows:

[0175] First, randomize the variable with the highest priority to obtain the random value of the variable with the highest priority;

[0176] Then, based on the random value of the variable with the highest priority, the variable with the second highest priority is randomized to obtain the random value of the variable with the second highest priority, and so on, the random values of all variables can be obtained in sequence.

[0177] For example, taking the constraints of the stimulus required for the above test case 1 as an example, according to the above step 1, the priority of each variable is determined from high to low as: c, b, a; according to the above step 3, the optimized constraints are:

[0178] a:[max(-100,100-b):min(b+c,300-b-3c)]

[0179] b:[ max(max(64,-100-c,(100-c) / 2):min(1522-c,400-3c)]

[0180] c:[2:66].

[0181] According to the variable priority, variable c is first randomized:

[0182] c:[2:66] --> Assume that the random number is 29

[0183] Substitute the random value 29 of c into the inequality of b and perform randomization on the variable b:

[0184] b:[ max(max(64,-100-c,(100-c) / 2):min(1522-c,400-3c)]

[0185] -->b:[ max(max(64,-100-29,(100-29) / 2):min(1522-29,400-3*29)]

[0186] -->b:[ max(max(64,-129,35.5):min(1493,313)]

[0187] -->b:[ 64:313]

[0188] -->Assume this random number is 273

[0189] Substitute the random values of b and c into the inequality of variable a, and randomize variable a:

[0190] a:[max(-100,100-b):min(b+c,300-b-3c)]

[0191] -->a:[max(-100,100-273):min(273+29,300-273-3*29)]

[0192] -->a:[-100:min(302,-60)]

[0193] -->a:[-100:-60]

[0194] -->Assume this random number is -67

[0195] You can get a random value {a,b,c} = {-67,273,29}.

[0196] The random excitation generation method proposed in this embodiment determines the priority of each variable based on the range constraints in the constraint conditions, simplifies all constraints in the constraint conditions (finds the intersection), and converts all relevant constraints of each variable in the constraint conditions into a range constraint, that is, finally obtaining a constraint condition consisting only of the range constraints of each variable, and then randomizing them one by one according to the priority, which can directly obtain the random values of all variables without repeated randomization or additional revision algorithms; and the constraint simplification and conversion algorithm involved in this method is a simple logical reasoning algorithm, which is only related to the number of variables, and the algorithm only needs to be executed once, and can be randomized one by one according to the priority (this process does not require the above-mentioned logical reasoning algorithm to be executed again), so it does not consume a lot of hardware and greatly improves the computing efficiency.

[0197] Figure 2 The measured results of four common use cases (i.e., Use Case 1, Use Case 2, Use Case 3, and Use Case 4) using the random stimulus generation method proposed in the embodiments of the present application and implemented using SystemVerilog are given respectively.

[0198] Depend on Figure 2 It can be seen that this application randomly divides the solution and calculation stages. According to the measured results, in a complete simulation, the calculation stage accounts for about 1% to 3%, that is, the time consumption of this application is concentrated in the solution stage, and the solution can be reused, that is, no matter how many times the use case is executed, it only needs to be solved once. According to statistics, for ordinary use cases, the speed can be increased by 3 to 10 times after using the random excitation generation method proposed in the embodiment of this application. Once the solution reuse mechanism is enabled, the overall random performance will be accelerated by dozens of times with an extremely huge advantage.

[0199] An optional implementation method should also include before step 1: when it is detected that there is an "or" constraint in the constraint conditions, first split it into parallel constraints, then arbitrarily (randomly) select a group from the parallel constraints, and then generate random values for each variable for the randomly selected constraint conditions according to the process described in steps 1 to 4 above.

[0200] Based on the same technical concept as above, this embodiment also proposes a random stimulus generation system for chip verification testing.

[0201] like Figure 3 As shown, the random stimulus generation system proposed in this embodiment includes:

[0202] A priority sorting unit, which determines the priority of all variables in the stimulus according to the constraint conditions of the stimulus required by the chip under test verification test case;

[0203] A normalization unit is used to detect whether there is an inequality constraint in the constraint condition. If so, the inequality constraint is equivalently replaced with a unified representation and then the simplification conversion unit is driven to work. Otherwise, the simplification conversion unit is directly driven to work.

[0204] A simplification conversion unit, which calculates the intersection of all relevant constraints of each variable in the constraint condition based on the priority of the variable, converts all relevant constraints of each variable into a range constraint, and thus generates an optimized constraint condition;

[0205] And, a first random unit, which is based on the optimized constraint conditions and randomly selects variables from high to low priority, thereby obtaining the random stimulus required for the verification test case of the chip under test.

[0206] It should be noted that the specific implementation methods of each functional module unit of the system are as described in steps 1 to 4 above, and will not be elaborated here.

[0207] In an optional implementation manner, the random incentive generation system proposed in this embodiment further includes:

[0208] A splitting unit, which splits the constraint condition into parallel constraint conditions when detecting that there is an "or" constraint in the constraint condition;

[0209] and a second random unit that arbitrarily (randomly) selects a set of inputs to the priority ranking unit from the parallel constraints.

[0210] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0211] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1A device that provides the functions specified in a block or multiple blocks.

[0212] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0213] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0214] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of this application. It should be understood that the above description is only the specific implementation methods of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. A random stimulus generation method for chip verification testing, characterized in that: The method comprises: Determine the priority of all variables in the stimulus according to the constraint conditions of the stimulus required by the test case for verifying the chip under test; the constraint conditions include at least one of a constant range constraint, a variable expression range constraint, and an inequality constraint; Detect whether there is an inequality constraint in the constraint condition; if so, replace the inequality constraint with a unified representation and then execute the subsequent steps; otherwise, execute the subsequent steps directly; the unified representation of the inequality constraint is in the form of ">=" and / or "<="; Based on the priority of the variables, the intersection of all the related constraints of each variable in the constraint condition is obtained, and all the related constraints of each variable are converted into a range constraint, thereby generating an optimized constraint condition; Based on the optimized constraint conditions, randomize the variables from high to low priority, so as to obtain the random stimulus required for the verification test case of the chip under test; The variable priority-based method is to find the intersection of all relevant constraints for each variable in the constraint condition, convert all relevant constraints for each variable into a range constraint, and thereby generate an optimized constraint condition, specifically including: Simplify the constraints to generate new inequality constraints, and substitute the generated new inequality constraints into the range constraints of the constraints to obtain a first simplification result; Simplifying the result of the first simplification to generate a new inequality constraint, substituting the generated new inequality constraint into the result of the first simplification to obtain a second simplification result; This process continues until no new inequality constraints can be generated by simplification. The simplification ends and the result of the last simplification is the optimized constraint condition. Among them, in each simplification process, low priority must depend on high priority.

2. The random stimulus generation method for chip verification testing according to claim 1, characterized in that: The priority of the variables is determined as follows: The variables are prioritized according to the range constraints in the constraints. The following conditions must be met during the sorting process: The relying party has a lower priority than the dependent party; The principle of independent changes having the highest priority; When two or more variables have the same priority, they are sorted in alphabetical order; When a dependency loop occurs, the entire random constraint has no solution, and feedback is sent to the client to modify the requirements. When a variable depends on itself, the entire random constraint has no solution, and feedback is sent to the client to modify the requirements.

3. The random stimulus generation method for chip verification testing according to claim 1, characterized in that: The method of finding the intersection of all relevant constraints of each variable in the constraint condition based on the variable priority, converting all relevant constraints of each variable into a range constraint, and thereby generating an optimized constraint condition further includes: In each simplification process, the inequality constraints that always hold true are discarded.

4. The random stimulus generation method for chip verification testing according to claim 1, characterized in that: The method of finding the intersection of all relevant constraints of each variable in the constraint condition based on the variable priority, converting all relevant constraints of each variable into a range constraint, and thereby generating an optimized constraint condition further includes: When an inequality constraint that is always invalid appears during the simplification process, feedback is given to the client to modify the requirements.

5. The random stimulus generation method for chip verification testing according to claim 1, characterized in that: The above mentioned optimization-based constraints are randomized in descending order of priority of variables, specifically including: Randomize the variable with the highest priority to obtain the random value of the variable with the highest priority; Based on the random value of the edge with the highest priority, the variable with the second highest priority is randomized to obtain the random value of the variable with the second highest priority, and so on, to obtain the random values of all variables in sequence.

6. A random stimulus generation method for chip verification testing according to any one of claims 1 to 5, characterized in that: Before the step of determining the priorities of all variables in the stimulus according to the constraint conditions of the stimulus required for the test case verification of the chip under test, the method further includes: Check whether there is an "or" constraint in the constraint conditions. If so, split the constraint conditions into parallel constraint conditions, and randomly select a group of constraint conditions from the parallel constraint conditions for subsequent processing.

7. A random stimulus generation system for chip verification testing, characterized in that: The system comprises: a priority sorting unit, wherein the priority sorting unit determines the priority of all variables in the stimulus according to the constraint conditions of the stimulus required by the test case for verifying the chip under test, wherein the constraint conditions include at least one of a constant range constraint, a variable expression range constraint, and an inequality constraint; a normalization unit, the normalization unit being configured to detect whether there are inequality constraints in the constraint conditions, and if so, to drive the simplification conversion unit to work after equivalently replacing all inequality constraints with a unified representation; otherwise, to directly drive the simplification conversion unit to work; the unified representation of the inequality constraints is in the form of ">=" and / or "<="; a simplification conversion unit, wherein the simplification conversion unit calculates the intersection of all relevant constraints of each variable in the constraint condition based on the priority of the variable, converts all relevant constraints of each variable into a range constraint, and thereby generates an optimized constraint condition; and a first random unit, wherein the first random unit performs random operations in descending order of priority of variables based on the optimized constraint conditions, thereby obtaining random stimuli required for the verification test case of the chip under test; The variable priority-based method is to find the intersection of all relevant constraints for each variable in the constraint condition, convert all relevant constraints for each variable into a range constraint, and thereby generate an optimized constraint condition, specifically including: Simplify the constraints to generate new inequality constraints, and substitute the generated new inequality constraints into the range constraints of the constraints to obtain a first simplification result; Simplifying the result of the first simplification to generate a new inequality constraint, substituting the generated new inequality constraint into the result of the first simplification to obtain a second simplification result; This process continues until no new inequality constraints can be generated by simplification. The simplification ends and the result of the last simplification is the optimized constraint condition. Among them, in each simplification process, low priority must depend on high priority.

8. The random stimulus generation system for chip verification testing according to claim 7, characterized in that: The system further comprises: a splitting unit, wherein when detecting that an "or" constraint exists in the constraint condition, the splitting unit splits the constraint condition into parallel constraint conditions; and a second random unit, which randomly selects a set of inputs from the parallel constraints to the priority ranking unit.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

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