Aging method of pixel circuit

Abstract

The application relates to the technical field of display, and particularly provides an aging method of a pixel circuit, aiming to solve the problem that the existing aging method of the pixel circuit is prone to generating large leakage current and causing burn of a display panel. To this end, the aging method of the pixel circuit comprises the following steps: in a signal prewriting stage, the first initialization subcircuit and the gate voltage writing subcircuit are controlled to be turned on, a first initialization signal is provided to a first end of the first initialization subcircuit, and the target voltage is written to the control end of the driving subcircuit by using the first initialization signal, so that the problem that a large data voltage is generally required or the data voltage and the second power supply end need to have a large pressure difference in the related art when the target voltage is written based on the data signal provided to the data writing subcircuit, the large leakage current is easily generated, and the display panel is burned, and the aging effect of the pixel circuit can be effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, and specifically provides an aging method of a pixel circuit. BACKGROUND

[0002] In a pixel circuit of an organic light-emitting diode display panel, the self defects of transistors can cause leakage current, and the leakage degrees of different transistors are different, thereby causing uneven light emission of the display panel. In the related art, in order to solve the problem, the pixel circuit is subjected to aging (Aging) processing, a larger voltage is provided for the transistors in the pixel circuit, the off-state current of each transistor is reduced, thereby ensuring the stable performance of each transistor and improving the display effect.

[0003] However, in the related art, when the pixel circuit is subjected to aging, a larger leakage current is easily generated while the larger voltage required for aging is provided for the transistors, thereby causing problems such as burning of the display panel. SUMMARY

[0004] The present application aims to solve the above technical problem, that is, to solve the problem that the existing aging method of the pixel circuit easily generates a larger leakage current and causes burning of the display panel.

[0005] In a first aspect, the present application provides an aging method of a pixel circuit, the pixel circuit comprising a first initialization sub-circuit, a gate voltage writing sub-circuit, a driving sub-circuit, a data writing sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a light-emitting device, and an energy storage circuit.

[0006] The first light-emitting control sub-circuit, the driving sub-circuit, the second light-emitting control sub-circuit, and the light-emitting device are sequentially connected between a first power supply end and a second power supply end, and the control end of the driving sub-circuit is connected with the energy storage circuit and the gate voltage writing sub-circuit through a first node, respectively. The first end of the driving sub-circuit is connected with the data writing sub-circuit and the first light-emitting control sub-circuit through a second node, respectively. The second end of the driving sub-circuit is connected with the first initialization sub-circuit, the gate voltage writing sub-circuit, and the second light-emitting control sub-circuit through a third node, respectively. The other end of the energy storage circuit is connected with the first power supply end.

[0007] The aging method comprises:

[0008] In the signal pre-writing stage, the first initialization sub-circuit and the gate voltage writing sub-circuit are controlled to be turned on, and a first initialization signal is provided to the first end of the first initialization sub-circuit, so as to write a target voltage to the first node based on the first initialization signal; when the driving sub-circuit is the target to be aged, the target voltage is a first voltage meeting the aging condition of the driving sub-circuit; when the circuit other than the driving sub-circuit in the pixel circuit is the target to be aged, the target voltage is a second voltage for turning on the driving sub-circuit.

[0009] In the aging stage, an aging voltage is provided to the target to be aged.

[0010] In some embodiments, when the driving sub-circuit adopts a P-type transistor, the first voltage is greater than the second voltage; when the driving sub-circuit adopts an N-type transistor, the first voltage is less than the second voltage.

[0011] In some embodiments, after the first initialization sub-circuit and the gate voltage writing sub-circuit are controlled to be turned on and the first initialization signal is provided to the first end of the first initialization sub-circuit in the signal pre-writing stage, the method further comprises: controlling the gate voltage writing sub-circuit to be turned off.

[0012] In some embodiments, after the gate voltage writing sub-circuit is controlled to be turned off and kept for a preset time length, the method further comprises: controlling the first initialization sub-circuit to be turned off.

[0013] In some embodiments, when the driving sub-circuit is the target to be aged, the providing of the aging voltage to the target to be aged in the aging stage comprises:

[0014] In the aging stage, the first light-emitting control sub-circuit and the second light-emitting control sub-circuit are controlled to be turned on, a first power supply voltage is provided to the first power supply end based on the first voltage, and a second power supply voltage is provided to the second power supply end, so as to provide an aging voltage to the first end and the second end of the driving sub-circuit, respectively.

[0015] In some embodiments, the method further comprises: in the signal pre-writing stage, providing an initial first power supply voltage to the first power supply end and an initial second power supply voltage to the second power supply end; when the driving sub-circuit is the target to be aged, the difference between the initial first power supply voltage and the initial second power supply voltage is less than the difference between the first power supply voltage provided to the first power supply end and the second power supply voltage provided to the second power supply end in the aging stage.

[0016] In some embodiments, when the first light-emitting control sub-circuit is the target to be aged, the providing, in the aging stage, of the aging voltage to the target to be aged comprises:

[0017] In the aging stage, the first power supply end is provided with a first power supply voltage, the control end of the first light-emitting control sub-circuit is provided with a light-emitting control signal, and the data write sub-circuit is controlled to be turned on and provided with a data signal, so as to provide the first end, the control end and the second end of the first light-emitting control sub-circuit with the aging voltage respectively.

[0018] In some embodiments, when the second light-emitting control sub-circuit is the target to be aged, the providing, in the aging stage, of the aging voltage to the target to be aged comprises:

[0019] In the aging stage, the second power supply end is provided with a second power supply voltage, the control end of the second light-emitting control sub-circuit is provided with a light-emitting control signal, and the first initialization sub-circuit is controlled to be turned on and provided with a first initialization signal, so as to provide the first end, the control end and the second end of the second light-emitting control sub-circuit with the aging voltage respectively.

[0020] In some embodiments, the pixel circuit further comprises a second initialization sub-circuit and a third initialization sub-circuit, wherein the second end of the second initialization sub-circuit is connected with the anode of the light-emitting device and the second light-emitting control sub-circuit respectively, for initializing the anode of the light-emitting device; and the second end of the third initialization sub-circuit is connected with the second node, for initializing the second node.

[0021] The providing, in the aging stage, of the aging voltage to the target to be aged comprises: in the aging stage, providing the aging voltage to any one of the first initialization sub-circuit, the second initialization sub-circuit, the third initialization sub-circuit and the data write sub-circuit.

[0022] In some embodiments, the providing, in the aging stage, of the aging voltage to any one of the first initialization sub-circuit, the second initialization sub-circuit, the third initialization sub-circuit and the data write sub-circuit comprises:

[0023] In the aging stage, the first light-emitting control sub-circuit and the second light-emitting control sub-circuit are controlled to be turned on, the first power supply end is provided with a first power supply voltage, the control end of any one of the first initialization sub-circuit, the second initialization sub-circuit, the third initialization sub-circuit and the data write sub-circuit is provided with a control end aging signal, and the first end is provided with a first end aging signal.

[0024] In the technical solution, in a signal pre-writing stage, the first initialization sub-circuit and the gate voltage writing sub-circuit are turned on, and a first initialization signal is provided to a first end of the first initialization sub-circuit, so that a target voltage is written to the first node based on the first initialization signal; when the driving sub-circuit is a target to be aged, the target voltage is a first voltage meeting an aging condition of the driving sub-circuit; when a circuit other than the driving sub-circuit in the pixel circuit is a target to be aged, the target voltage is a second voltage for turning on the driving sub-circuit; and in an aging stage, an aging voltage is provided to the target to be aged. In the technical solution, in the signal pre-writing stage, the first initialization signal is used to write the target voltage to the first node, so that the problem that a large data voltage is usually required or a large voltage difference between the data voltage and the second power supply end needs to be set when the target voltage is written to the first node based on a data signal provided to a data writing sub-circuit in the related art, a large leakage current is easily generated, and a display panel is burned, can be avoided, and the aging effect of the pixel circuit can be effectively improved. BRIEF DESCRIPTION OF DRAWINGS

[0025] The preferred embodiments of the present application will be described below with reference to the accompanying drawings, in which:

[0026] Figure 1 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0027] Figure 2 is a flowchart of an aging method of a pixel circuit provided by an embodiment of the present application;

[0028] Figure 3 is a circuit diagram of a pixel circuit provided by an embodiment of the present application; Figure 1

[0029] Figure 4 is a circuit diagram of a pixel circuit provided by another embodiment of the present application;

[0030] Figure 5 is a signal timing diagram of the pixel circuit when the third transistor T3 is aged, provided by an embodiment of the present application;

[0031] Figure 6 is a signal timing diagram of the pixel circuit when the third transistor T3 is aged, provided by another embodiment of the present application;

[0032] Figure 7 is a signal timing diagram of the pixel circuit when the third transistor T3 is aged, provided by another embodiment of the present application;

[0033] Figure 8 ​is a signal timing diagram of the pixel circuit when the fifth transistor T5 is aged, provided by another embodiment of the present application.

[0034] Figure 9 is a signal timing diagram of the pixel circuit when the sixth transistor T6 is aged, provided by another embodiment of the present application.

[0035] Figure 10 is a signal timing diagram of the pixel circuit when the first transistor T1 or the fourth transistor T4 is aged, provided by another embodiment of the present application.

[0036] Figure 11 is a signal timing diagram of the pixel circuit when the seventh transistor T7 or the eighth transistor T8 is aged, provided by another embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0038] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0039] It should be noted that the transistors used in the embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present application, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first end, the other electrode is called the second end, and the gate is called the control end. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. The following embodiments are explained with P-type transistors. When a P-type transistor is used, the first end is the source of the P-type transistor, and the second end is the drain of the P-type transistor. When the gate input is low, the source and drain are turned on, the low level is the working level, and the high level is the non-working level; the N-type transistor is the opposite. It can be imagined that the use of N-type transistors is something that a person skilled in the art can easily think of without creative work, and therefore it is also within the scope of protection of the embodiments of the present application.

[0040] When performing aging processing on a pixel circuit, the transistors of each sub-circuit in the pixel circuit can be aged separately. For the aging of the target transistor, it is necessary to control the voltages provided to the gate, source and drain of the target transistor so that it meets a specific bias condition, namely the aging condition: the gate-drain voltage (V GD ) is set below its threshold voltage (V th ), while applying a sufficiently high drain-source voltage (V DS ).

[0041] In the related art, when aging the pixel circuit, when the larger voltage required for aging is provided to the target transistor to be aged, due to the electrical connection between different transistors, the non-aged transistors are easily affected, unable to be turned off and generate a large leakage current, causing problems such as display panel burns.

[0042] See also Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a pixel circuit provided by an embodiment of the present application. The pixel aging method provided by the present application can be applied to Figure 1 The pixel circuit.

[0043] See also Figure 1 As shown, the pixel circuit may include a first initialization subcircuit, a gate voltage writing subcircuit, a driving subcircuit, a data writing subcircuit, a first light emitting control subcircuit, a second light emitting control subcircuit, a light emitting device and an energy storage circuit.

[0044] Among them, the first light-emitting control sub-circuit, the driving sub-circuit, the second light-emitting control sub-circuit and the light-emitting device are connected in sequence between the first power supply terminal VDD and the second power supply terminal VSS, and the control end of the driving sub-circuit is connected to the energy storage circuit and the gate voltage writing sub-circuit respectively through the first node N1, the first end of the driving sub-circuit is connected to the data writing sub-circuit and the first light-emitting control sub-circuit respectively through the second node N2, the second end of the driving sub-circuit is connected to the first initialization sub-circuit, the gate voltage writing sub-circuit and the second light-emitting control sub-circuit respectively through the third node N3, and the other end of the energy storage circuit is connected to the first power supply terminal.

[0045] To target Figure 1 As an example, the aging of the driving sub-circuit in the pixel circuit shown in FIG. 1 is performed, and a lighting timing sequence is generally adopted in the related art, that is, it includes an initialization stage, a writing stage, and a lighting stage. In the writing stage, the data writing sub-circuit is controlled to be turned on and a data signal Data is provided to the first terminal of the data writing sub-circuit, so that the gate voltage required for aging is written to the control terminal of the driving sub-circuit based on the data signal Data. At the same time, a drain-source voltage (V DS ). To ensure the gate-drain voltage of the driving sub-circuit (V GD ) To meet the aging conditions, it is necessary to ensure that the data voltage Vdata provided by the data signal Data and the drain voltage provided by the second power supply terminal VSS have a sufficiently large voltage difference. Therefore, it is necessary to provide a data voltage Vdata with a larger voltage value or to make the second power supply terminal VSS provide a sufficiently low drain voltage. When the data voltage Vdata with a larger voltage value is provided, the first light-emitting control sub-circuit cannot be turned off, and the current is likely to flow back to the first power supply terminal VDD. Other sub-circuits may also have similar problems as the first light-emitting control sub-circuit, thereby generating leakage current, which is likely to cause burns to the display panel.

[0046] In view of this, the present application provides an aging method for a pixel circuit, which can be applied to Figure 1 The pixel circuit shown in Figure 2 As shown, Figure 2 This is a flowchart of an aging method for a pixel circuit provided in an embodiment of the present application, which may include:

[0047] Step S21: in a signal pre-writing phase, controlling the first initialization sub-circuit and the gate voltage writing sub-circuit to be turned on, and providing a first initialization signal to a first terminal of the first initialization sub-circuit, so as to write a target voltage to the first node based on the first initialization signal;

[0048] When the driving sub-circuit is the target for aging, the target voltage is a first voltage satisfying an aging condition of the driving sub-circuit; when a circuit other than the driving sub-circuit in the pixel circuit is the target for aging, the target voltage is a second voltage enabling the driving sub-circuit to be turned on.

[0049] Step S22: providing an aging voltage for the target for aging in the aging stage.

[0050] The first voltage can make the driving sub-circuit be turned off, and the second voltage is different from the first voltage, and the second voltage can be set based on a requirement for the on-off degree of the driving sub-circuit. When the driving sub-circuit adopts a P-type transistor, the first voltage is greater than the second voltage; when the driving sub-circuit adopts an N-type transistor, the first voltage is less than the second voltage.

[0051] When the target for aging is the driving sub-circuit and a circuit other than the driving sub-circuit in the pixel circuit, the voltage of the first initialization signal Vinit provided is different. When the target for aging is a circuit other than the driving sub-circuit in the pixel circuit, the first initialization signal Vinit corresponding to different circuits can be flexibly set according to the aging requirement, which can be the same or different.

[0052] In some embodiments, step S22 can be specifically:

[0053] When the target for aging is the driving sub-circuit, the aging voltage is provided for the first end and the second end of the driving sub-circuit based on the first voltage.

[0054] The aging voltage corresponds to each end of the target for aging one by one, and can include the aging voltage of the first end and the aging voltage of the second end. When the target for aging adopts a P-type transistor, the aging voltage of the first end is the source voltage of the current target for aging, and the aging voltage of the second end is the drain voltage of the current target for aging. When an N-type transistor is adopted, the above is opposite to the P-type. The aging voltage of the first end, the aging voltage of the second end and the first voltage satisfy the aging condition of the driving sub-circuit.

[0055] When the target for aging is a circuit other than the driving sub-circuit in the pixel circuit, the aging voltage is provided for the first end, the control end and the second end of the target for aging respectively.

[0056] Among them, the aging voltage corresponds to each end of the target to be aged one by one, such as the aging voltage at the first end, the aging voltage at the second end and the aging voltage at the control end, and the aging voltage at the control end is used to cut off the target to be aged. When the target to be aged adopts a P-type transistor, the aging voltage at the first end is the source voltage of the current target to be aged, and the aging voltage at the second end is the drain voltage of the current target to be aged. When an N-type transistor is adopted, it is opposite to the P-type. The aging voltage at the first end, the aging voltage at the second end and the aging voltage at the control end meet the aging conditions of the target to be aged.

[0057] This solution controls the conduction of the first initialization sub-circuit and the gate voltage writing sub-circuit during the signal pre-writing stage, and uses the first initialization signal Vinit provided to the first initialization sub-circuit to write the target voltage to the first node N1. This can avoid the problem in the related art that when writing the target voltage to the first node N1 based on the data signal Data provided to the data writing sub-circuit, a larger data voltage Vdata is usually required or a larger voltage difference between the data voltage Vdata and the second power supply terminal VSS is required, which easily generates a large leakage current and causes burns to the display panel. This can effectively improve the aging effect of the pixel circuit.

[0058] In some embodiments, in order to prevent the gate voltage writing sub-circuit from being in an on state at the moment of switching screens, causing the energy storage circuit to discharge and the voltage of the first node N1 to be disturbed, in the signal pre-writing stage, the first initialization sub-circuit and the gate voltage writing sub-circuit are controlled to be turned on, and a first initialization signal Vinit is provided to the first end of the first initialization sub-circuit, so that the target voltage is written to the first node N1 based on the first initialization signal Vinit. Then, the method may further include: controlling the gate voltage writing sub-circuit to be turned off.

[0059] In some embodiments, in order to further avoid interference of leakage current on the voltage of the first node N1 and prevent product burns caused by leakage current, the gate voltage writing subcircuit is controlled to be cut off and maintained for a preset time. The method also includes controlling the first initialization subcircuit to be cut off.

[0060] In some embodiments, see Figure 3 As shown, Figure 3 This embodiment of the present application provides Figure 1 Circuit diagram of the pixel circuit shown.

[0061] The first initialization subcircuit includes a first transistor T1 , a first terminal of the first transistor T1 is used to input a first initialization signal Vinit1 , a second terminal of the first transistor T1 is connected to a third node N3 , and a control terminal of the first transistor T1 is used to receive a gate drive signal Gate-P.

[0062] The gate voltage writing sub-circuit comprises a second transistor T2, a first end of the second transistor T2 is connected with the third node N3, a second end of the second transistor T2 is connected with the first node N1, and a control end of the second transistor T2 is used for receiving a gate driving signal Gate-N.

[0063] The driving sub-circuit comprises a third transistor T3, a first end of the third transistor T3 is connected with the second node N2, a second end of the third transistor T3 is connected with the third node N3, and a control end of the third transistor T3 is connected with the first node N1.

[0064] The data writing sub-circuit comprises a fourth transistor T4, a first end of the fourth transistor T4 is used for inputting a data signal Data, a second end of the fourth transistor T4 is connected with the second node N2, and a control end of the fourth transistor T4 is used for inputting the gate driving signal Gate.

[0065] The first light emitting control sub-circuit comprises a fifth transistor T5, a first end of the fifth transistor T5 is connected with the first power supply end VDD, a second end of the fifth transistor T5 is connected with the second node N2, and a control end of the fifth transistor T5 is used for inputting a light emitting control signal EM.

[0066] The second light emitting control sub-circuit comprises a sixth transistor T6, a first end of the sixth transistor T6 is connected with the third node N3, a second end of the sixth transistor T6 is connected with an anode of the light emitting device, and a control end of the sixth transistor T6 is used for inputting the light emitting control signal EM.

[0067] The energy storage circuit comprises a capacitor Cst, a first end of the capacitor Cst is connected with the first power supply end VDD, and a second end of the capacitor Cst is connected with the first node N1.

[0068] The cathode of the light emitting device is connected with the second power supply end VSS.

[0069] In the example, the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are all P-type transistors, and the second transistor T2 is an N-type transistor.

[0070] In other embodiments, referring to Figure 4 , Figure 4 is a circuit diagram of a pixel circuit provided by another embodiment of the present application, which can be based on Figure 2 or Figure 3 The corresponding pixel circuit implementation further comprises:

[0071] A second initialization subcircuit and a third initialization subcircuit, wherein the second end of the second initialization subcircuit is respectively connected to the second light-emitting control subcircuit and the anode of the light-emitting device for initializing the anode of the light-emitting device; and the second end of the third initialization subcircuit is connected to the second node N2 for initializing the second node.

[0072] In some embodiments, the second initialization subcircuit may include a seventh transistor T7, the first end of the seventh transistor T7 is used to receive the second initialization signal Vinit2, the second end of the seventh transistor T7 is connected to the anode of the light-emitting device, and the control end of the seventh transistor T7 is used to receive the gate drive signal Gate-H.

[0073] The third initialization sub-circuit may include an eighth transistor T8 , a first terminal of the eighth transistor T8 is used to receive the third initialization signal Vinit3 , a second terminal of the eighth transistor T8 is connected to the second node N2 , and a control terminal of the eighth transistor T8 is used to receive the gate drive signal Gate-H.

[0074] In the following, we will Figure 4 The aging method provided by the present application is described by taking the pixel circuit shown as an example. Figure 4 When the pixel circuit shown is aged, step S21 may be specifically as follows:

[0075] In the signal pre-writing stage, a low-level gate drive signal Gate-P is provided to control the first transistor T1 to be turned on, a high-level gate drive signal Gate-N is provided to control the second transistor T2 to be turned on, and a first initialization signal Vinit1 is provided to the first end of the first transistor T1 to write a target voltage to the first node N1 based on the first initialization signal Vinit1; wherein, when the third transistor T3 is the target to be aged, the target voltage is a first voltage that meets the aging condition of the third transistor T3; when the transistor other than the third transistor T3 in the pixel circuit is the target to be aged, the target voltage is a second voltage that turns on the third transistor T3.

[0076] Step S22 may specifically be providing an aging voltage to the transistor to be aged during the aging stage.

[0077] The first voltage can turn off the third transistor T3.

[0078] When the right Figure 4 When the third transistor T3 in the aging process is carried out, see Figure 5 As shown, Figure 5is a signal timing diagram of the pixel circuit provided by the embodiment of the present application, and step S21 can be specifically: in a signal pre-writing stage, providing a low-level gate driving signal Gate-P to the control end of the first transistor T1, providing a high-level gate driving signal Gate-N to the control end of the second transistor T2, controlling the first transistor T1 and the second transistor T2 to be turned on, and providing a first initialization signal Vinit1 to the first end of the first transistor T1, so as to write a first voltage to the first node N1 based on the first initialization signal Vinit1. The third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are all turned off.

[0079] Step S22 can be specifically: in an aging stage, providing a low-level light-emitting control signal EM to the control end of the fifth transistor T5 and the sixth transistor T6 respectively, controlling the fifth transistor T5 and the sixth transistor T6 to be turned on, and providing a first power voltage to the first power end VDD based on the first voltage, and providing a second power voltage to the second power end VSS, so as to provide an aging voltage to the first end and the second end of the third transistor respectively, so that the gate-drain voltage of the third transistor T3 and the drain-source voltage meet the aging condition, and the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all turned off.

[0080] In some embodiments, the method can further include: in the signal pre-writing stage, providing an initial first power voltage to the first power end VDD and providing an initial second power voltage to the second power end VSS; wherein when the driving sub-circuit is the target to be aged, the difference between the initial first power voltage and the initial second power voltage is less than the difference between the first power voltage provided to the first power end and the second power voltage provided to the second power end in the aging stage. In the signal pre-writing stage, the present application can set the initial first power voltage and the initial second power voltage with a smaller difference, which effectively prevents the un-aged transistor from affecting the writing of the signal due to its own characteristic leakage. The present application solves the problem in the related art that when writing a signal to the first node N1, the first power voltage and the second power voltage with a large pressure difference are required, and the initial first power voltage is usually set to be large or the initial second power voltage is usually set to be small, which leads to the problem of easy leakage current and affects the signal writing.

[0081] As an example, the voltage values of various signals in the signal pre-writing stage are shown in Table 1 as follows:

[0082]

[0083] VGH and VGL represent the high level and low level of the gate driving signal Gate, Gate-P and Gate-H respectively, and VGH_N and VGL_N represent the high level and low level of the gate driving signal Gate-N respectively. VINIT1, VINIT2 and VINIT3 are the voltages corresponding to the first initialization signal Vinit1, the second initialization signal Vinit2 and the third initialization signal Vinit3 respectively. Vdata is the data voltage corresponding to the data signal Data, Vdd is the first power voltage corresponding to the first power supply end VDD, and Vss is the second power voltage corresponding to the second power supply end VSS.

[0084] VSS does not participate in the writing of the first voltage of the control end of the third transistor T3, and does not need to be set lower than in the related art. VINTI1 can be set to VGH to avoid current leakage of the fifth transistor T5 and the sixth transistor T6. VINIT2 can be set to be greater than VSS to avoid current backflow and cause the seventh transistor T7 to leak current. In addition, the voltages of other signals can be flexibly set based on avoiding leakage current.

[0085] The voltage values of the signals in the aging stage are shown in Table 2:

[0086]

[0087] The value of VSS in the aging stage is less than the value in the signal pre-writing stage to meet the aging condition of the third transistor T3.

[0088] In the related art, when the third transistor T3 is aged, the voltage values of the signals are shown in Table 3:

[0089]

[0090] Compared with the related art, the aging method of the present application does not need to take a larger value for Vdata, and the value of VSS also does not need to be lower.

[0091] In some embodiments, to prevent the second transistor T2 from being in an open state for an instant when switching pictures, causing the capacitor Cst to discharge and the voltage of the first node N1 to be disturbed, the signal timing as shown in Figure 6 may also be used. Wherein, the signal timing as shown in Figure 5The difference is that, in the signal pre-write stage, the first transistor T1 and the second transistor T2 are controlled to be turned on, and a first initialization signal Vinit1 is provided to the first end of the first transistor T1, so as to write a first voltage to the first node N1 based on the first initialization signal Vinit1. After that, the method further comprises: controlling the second transistor T2 to be turned off. Specifically, the second transistor T2 can be controlled to be turned off by providing a low-level gate drive signal Gate-N to the control end of the second transistor T2.

[0092] Wherein, the first transistor T1 and the second transistor T2 can be controlled to be turned on, a first voltage is written to the first node N1 and maintained for a first time duration t1.

[0093] In other embodiments, in order to further avoid the interference of the leakage current on the voltage of the first node N1 and prevent the product from being burnt due to the leakage current, after the second transistor T2 is controlled to be turned off and maintained for a preset time duration, the method can further comprise: controlling the first transistor T1 to be turned off. Specifically, as shown in Figure 7 Figure 7 is a signal timing diagram of the pixel circuit when the third transistor T3 is aged, and the preset time duration is greater than zero, which can be represented as t2. The first transistor T1 can be controlled to be turned off by providing a high-level gate drive signal Gate-P to the control end of the first transistor T1, and maintained for a third time duration t3 before entering the aging stage.

[0094] When the fifth transistor T5 in Figure 4 is aged, referring to the pixel circuit signal timing diagram shown in Figure 8 , the step S21 can be specifically: in the signal pre-write stage, a low-level gate drive signal Gate-P is provided to the control end of the first transistor T1, a high-level gate drive signal Gate-N is provided to the control end of the second transistor T2, the first transistor T1 and the second transistor T2 are controlled to be turned on, and a first initialization signal Vinit1 is provided to the first end of the first transistor T1, so as to write a second voltage to the first node N1 based on the first initialization signal Vinit1.

[0095] The step S22 can be specifically: in the aging stage, a first power supply voltage is provided to the first power supply end VDD, an aging voltage is provided to the control end of the fifth transistor T5 through the light emission control signal EM, and the fourth transistor T4 is controlled to be turned on and provided with a data signal Data, so as to provide the aging voltage to the first end, the control end and the second end of the fifth transistor T5 respectively. Wherein, the third transistor T3 and the fourth transistor T4 are turned on, and the other transistors are turned off.

[0096] When the fifth transistor T5 in Figure 4 ​When the sixth transistor T6 in the embodiment is aged, see Figure 9 As shown in the timing diagram of each signal in the pixel circuit, step S21 can be specifically provided as follows: in the signal pre-writing stage, a low-level gate drive signal Gate-P is provided to the control end of the first transistor T1, and a high-level gate drive signal Gate-N is provided to the control end of the second transistor T2 to control the first transistor T1 and the second transistor T2 to be turned on, and a first initialization signal Vinit1 is provided to the first end of the first transistor T1 to write a second voltage to the first node N1 based on the first initialization signal Vinit1.

[0097] Step S22 may specifically include, during the aging stage, providing a second power supply voltage to the second power supply terminal VSS, providing an aging voltage of the control terminal to the control terminal of the sixth transistor T6 through the light-emitting control signal EM, and controlling the first transistor T1 to be turned on and providing a first initialization signal Vinit to the first transistor T1, so as to provide aging voltages to the first terminal, the control terminal, and the second terminal of the sixth transistor T6, respectively.

[0098] The third transistor T3 and the first transistor T1 are turned on, and the other transistors are turned off.

[0099] When the right Figure 4 When aging the first transistor T1 and the fourth transistor T4, the same method as that for aging the fifth transistor T5 or the sixth transistor T6 can be used in the signal pre-writing stage. Figure 10 As shown, Figure 10 This is a pixel circuit signal timing diagram provided by another embodiment of the present application. Step S22 can be specifically as follows: in the aging stage, controlling the fifth transistor T5 and the sixth transistor T6 to be turned on, providing the first power supply voltage to the first power supply terminal VDD, providing the control end aging signal to the first transistor T1 or the fourth transistor T4, and providing the first end aging signal to the first end.

[0100] Among them, when the first transistor T1 is the target to be aged, the control end aging signal can be provided by the gate drive signal Gate-P, thereby obtaining the aging voltage of the control end of the first transistor T1, and the first end aging signal can be provided by the first initialization signal Vinit1, thereby obtaining the aging voltage of the first end of the first transistor T1.

[0101] When the fourth transistor T4 is the target to be aged, the control end aging signal can be provided by the gate drive signal Gate, thereby obtaining the aging voltage of the control end of the fourth transistor T4, and the first end aging signal can be provided by the data signal Data, thereby obtaining the aging voltage of the first end of the fourth transistor T4.

[0102] As an example, when the first transistor T1 is aged, the voltage values of the signals can be seen from Table 4:

[0103]

[0104] The third transistor T3 can be kept open, i.e., no large opening degree is required, and VINIT1 can be set to be lower, at -1 to -3V. The values of the other signals can be flexibly set based on no leakage occurring.

[0105] As an example, when the fourth transistor T4 is aged, the voltage values of the signals can be seen from Table 5:

[0106]

[0107] When the seventh transistor T7 and the eighth transistor T8 in Figure 4 are aged, the same method as when the first transistor T1 or the fourth transistor T4 is aged can be used in the signal pre-writing stage, as shown in Table 4 or Table 5. Figure 11 Figure 11 is a pixel circuit signal timing diagram provided by another embodiment of the present application, and step S22 can be specifically: in the aging stage, the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on, the first power supply end VDD is provided with a first power supply voltage, the seventh transistor T7 or the eighth transistor T8 is provided with a control end aging signal, and the first end is provided with a first end aging signal.

[0108] When the seventh transistor T7 is the target to be aged, the control end aging signal can be provided through the gate drive signal Gate-H, so as to obtain the aging voltage of the control end of the seventh transistor T7, and the first end aging signal can be provided through the second initialization signal Vinit2, so as to obtain the aging voltage of the first end of the seventh transistor T7.

[0109] When the seventh transistor T7 is aged, the voltage values of the signals can be seen from Table 4.

[0110] When the eighth transistor T8 is the target to be aged, the control end aging signal can be provided through the gate drive signal Gate-H, so as to obtain the aging voltage of the control end of the eighth transistor T8, and the first end aging signal can be provided through the third initialization signal Vinit3, so as to obtain the aging voltage of the first end of the eighth transistor T8.

[0111] When the eighth transistor T8 is aged, the voltage values of the signals can be seen from Table 5.

[0112] The timing of the signals in the signal writing stage can also use, for example, Figure 6 or Figure 7 ​in the same manner as the same phase shown.

[0113] In addition, for the pixel circuit of the display panel, the control signals can be provided to the pixel circuit by different gate driving circuits and light emitting control circuits arranged at the periphery of the display area of the display panel, so as to realize the aging of the pixel circuit. The gate driving signals of the first transistor T1 and the second transistor T2 can be provided by different gate driving circuits respectively, and the light emitting control signals EM of the fifth transistor T5 and the sixth transistor T6 can be provided by the same light emitting control circuit. The gate driving circuit can provide the required gate voltage according to the aging condition or conduction requirement of the corresponding transistor, and the light emitting control circuit is similar.

[0114] So far, the technical scheme of the present application has been described in combination with the preferred embodiments shown in the drawings, but those skilled in the art can easily understand that the protection scope of the present application is obviously not limited to these specific embodiments. Those skilled in the art can make equivalent changes or replacements to the related technical features without departing from the principles of the present application, and the technical schemes after the changes or replacements will fall within the protection scope of the present application.

Claims

1. A method for aging a pixel circuit, characterized in that: The pixel circuit includes a first initialization subcircuit, a gate voltage writing subcircuit, a driving subcircuit, a data writing subcircuit, a first light emitting control subcircuit, a second light emitting control subcircuit, a light emitting device and an energy storage circuit; wherein the first light-emitting control subcircuit, the driving subcircuit, the second light-emitting control subcircuit, and the light-emitting device are sequentially connected between a first power supply terminal and a second power supply terminal, and the control terminal of the driving subcircuit is respectively connected to the energy storage circuit and the gate voltage writing subcircuit via a first node, the first terminal of the driving subcircuit is respectively connected to the data writing subcircuit and the first light-emitting control subcircuit via a second node, the second terminal of the driving subcircuit is respectively connected to the first initialization subcircuit, the gate voltage writing subcircuit, and the second light-emitting control subcircuit via a third node, and the other terminal of the energy storage circuit is connected to the first power supply terminal; The aging method comprises: In a signal pre-writing phase, the first initialization sub-circuit and the gate voltage writing sub-circuit are controlled to be turned on, and a first initialization signal is provided to the first terminal of the first initialization sub-circuit, so as to write a target voltage to the first node based on the first initialization signal; wherein, when the driver sub-circuit is a target to be aged, the target voltage is a first voltage that satisfies an aging condition of the driver sub-circuit; and when a circuit other than the driver sub-circuit in the pixel circuit is a target to be aged, the target voltage is a second voltage that turns on the driver sub-circuit; In the aging stage, an aging voltage is provided to the target to be aged.

2. The method according to claim 1, characterized in that When the driving sub-circuit adopts a P-type transistor, the first voltage is greater than the second voltage; when the driving sub-circuit adopts an N-type transistor, the first voltage is less than the second voltage.

3. The method according to claim 1, characterized in that In the signal pre-writing stage, after controlling the first initialization sub-circuit and the gate voltage writing sub-circuit to be turned on and providing a first initialization signal to the first end of the first initialization sub-circuit to write the target voltage to the first node based on the first initialization signal, the method further includes: controlling the gate voltage writing sub-circuit to be turned off.

4. The method according to claim 2, characterized in that After controlling the gate voltage writing sub-circuit to be turned off and maintaining the state for a preset time period, the method further includes controlling the first initialization sub-circuit to be turned off.

5. The method according to any one of claims 1 to 3, characterized in that When the driving sub-circuit is the target to be aged, providing the target to be aged with an aging voltage during the aging phase includes: During the aging stage, the first light-emitting control subcircuit and the second light-emitting control subcircuit are controlled to be turned on, and a first power supply voltage is provided to the first power supply terminal based on the first voltage, and a second power supply voltage is provided to the second power supply terminal, so as to provide aging voltages to the first terminal and the second terminal of the driving subcircuit, respectively.

6. The method according to claim 5, characterized in that The method further includes: in the signal pre-writing stage, providing an initial first power supply voltage to the first power supply terminal and providing an initial second power supply voltage to the second power supply terminal; wherein, when the driving sub-circuit is the target to be aged, the difference between the initial first power supply voltage and the initial second power supply voltage is smaller than the difference between the first power supply voltage provided to the first power supply terminal and the second power supply voltage provided to the second power supply terminal during the aging stage.

7. The method according to any one of claims 1 to 3, characterized in that When the first light-emitting control subcircuit is the target to be aged, providing the target to be aged with an aging voltage during the aging stage includes: During the aging stage, a first power supply voltage is provided to the first power supply terminal, a light control signal is provided to the control terminal of the first light control sub-circuit, and the data writing sub-circuit is controlled to be turned on and a data signal is provided to the data writing sub-circuit, so as to provide aging voltages to the first terminal, the control terminal and the second terminal of the first light control sub-circuit, respectively.

8. The method according to any one of claims 1 to 3, characterized in that When the second light emitting control subcircuit is the target to be aged, providing the target to be aged with an aging voltage during the aging stage includes: During the aging stage, a second power supply voltage is provided to the second power supply terminal, a light control signal is provided to the control terminal of the second light control sub-circuit, and the first initialization sub-circuit is controlled to be turned on and a first initialization signal is provided to the first initialization sub-circuit, so as to provide aging voltages to the first terminal, the control terminal and the second terminal of the second light control sub-circuit, respectively.

9. The method according to any one of claims 1 to 3, characterized in that The pixel circuit further includes a second initialization subcircuit and a third initialization subcircuit, wherein a second end of the second initialization subcircuit is connected to the second light emitting control subcircuit and the anode of the light emitting device, respectively, for initializing the anode of the light emitting device; a second end of the third initialization subcircuit is connected to the second node, for initializing the second node; Providing the aging voltage to the target to be aged during the aging phase includes providing the aging voltage to any one of the first initialization sub-circuit, the second initialization sub-circuit, the third initialization sub-circuit and the data writing sub-circuit during the aging phase.

10. The method according to claim 9, characterized in that The step of providing an aging voltage to any one of the first initialization sub-circuit, the second initialization sub-circuit, the third initialization sub-circuit, and the data writing sub-circuit during the aging phase includes: During the aging stage, the first light-emitting control subcircuit and the second light-emitting control subcircuit are controlled to be turned on, a first power supply voltage is provided to the first power supply terminal, a control terminal aging signal is provided to the control terminal of any one of the first initialization subcircuit, the second initialization subcircuit, the third initialization subcircuit and the data writing subcircuit, and a first terminal aging signal is provided to the first terminal.

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