Non-volatile memory read-write calculation method and calculation circuit and storage device

Abstract

The invention discloses a nonvolatile memory read-write calculation method and circuit and a storage device.The nonvolatile memory read-write calculation circuit comprises a storage circuit and a latch circuit, and the nonvolatile memory read-write calculation method comprises the following steps that a first digital signal and a second digital signal are sequentially written into the storage circuit through a two-step writing method; and selecting a reading mode to digitally read the first digital signal and the second digital signal in the storage circuit through the latch circuit and then latch and output the first digital signal and the second digital signal, or selecting a calculation mode to digitally calculate the first digital signal and the second digital signal in the storage circuit. According to the invention, the problems that the reading circuit of the nonvolatile memory is too slow in reading and cannot carry out digital memory internal calculation are solved.

Description

Technical Field

[0001] The present invention relates to the field of non-volatile memory, and in particular to a non-volatile memory reading and writing calculation method, a calculation circuit and a storage device. Background Art

[0002] Compute-in-Memory (CIM) is an emerging computing architecture that is widely used in artificial intelligence (AI) chips and neural network accelerators. According to the different signal domains used, CIM is divided into analog CIM and digital CIM. Analog CIM mainly performs calculations in the analog signal domain, while digital CIM mainly performs calculations in the digital signal domain. Analog Compute-in-Memory (ACIM) is widely used to efficiently perform multiplication and accumulation operations in a variety of analog domain signals (such as charge, current, and voltage). Analog CIM uses different memory devices, including volatile memories such as static random access memory (SRAM) and dynamic random access memory (DRAM) and non-volatile memories (NVM), such as resistive memory (RRAM), magnetic memory (MRAM), and phase change memory (PCM). The values ​​stored in these non-volatile memories are expressed as high and low resistance values.

[0003] However, the value stored in NVM is the resistance value, not the digital 0 or digital 1 (VSS or VDD) on the voltage, and cannot be directly output to the digital circuit for calculation. The traditional NVM reading circuit first precharges the parasitic capacitance of the bit line to VDD, and then opens the word line of the NVM to be read, so that the bit line capacitance is discharged through the NVM, and the discharge rate is negatively correlated with the resistance: the larger the resistance, the slower the discharge. The bit line voltage is then compared with the reference voltage through the sense amplifier (SA) to read the value stored in the NVM, and it is converted into a digital 0 or digital 1 on the voltage, which can then be output to the digital circuit for calculation. However, the traditional NVM reading circuit faces some problems. If there are too many NVMs connected to the bit line, the parasitic capacitance and parasitic resistance of the bit line will be too large, making the discharge time longer and the reading speed slower, thereby lowering the computing throughput. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the purpose of the present invention is to provide a non-volatile memory read and write calculation method and a calculation circuit and a storage device to solve the problem that the reading circuit of the non-volatile memory reads too slowly and cannot perform digital storage calculations.

[0005] The technical solution of the present invention is as follows:

[0006] A non-volatile memory read-write calculation method is applied to a non-volatile memory read-write calculation circuit, the non-volatile memory read-write calculation circuit includes a storage circuit and a latch circuit, and the non-volatile memory read-write calculation method includes the following steps:

[0007] Writing a first digital signal and a second digital signal into the storage circuit in sequence by a two-step writing method;

[0008] Select the read mode to digitally read the first digital signal and the second digital signal in the storage circuit through the latch circuit and then latch and output them, or select the calculation mode to digitally calculate the first digital signal and the second digital signal in the storage circuit.

[0009] Optionally, the non-volatile memory read / write calculation circuit further includes a source line, a bit line and an inverted bit line connected to the storage circuit, and the step of sequentially writing the first digital signal and the second digital signal to the storage circuit by the two-step writing method specifically includes:

[0010] Applying a first voltage to the source line and grounding the bit line and the inverted bit line to write a first digital signal to the storage circuit;

[0011] The source line is set to a second voltage, and the first voltage or the second voltage is applied to the bit line and the inverted bit line according to the write data, so as to write a second digital signal to the storage circuit.

[0012] Optionally, the non-volatile memory read / write calculation circuit further includes an address decoder, and when executing the step of sequentially writing the first digital signal and the second digital signal into the storage circuit by the two-step writing method, further includes:

[0013] The input data output by the address decoder is obtained, and the voltages on the source line, the bit line, and the inverted bit line are adjusted according to the input data.

[0014] Optionally, the step of selecting a read mode to digitally read the first digital signal and the second digital signal in the storage circuit specifically includes:

[0015] Obtain input data output by the address decoder, and connect the bit line and the inverted bit line to a first voltage;

[0016] Perform an AND gate calculation according to the input data and the first digital signal and the second digital signal in the storage circuit to obtain output data, and latch and output it through a latch circuit;

[0017] The output data is added through the addition tree, and the storage data in the storage circuit is output.

[0018] Optionally, the non-volatile memory read-write calculation circuit further includes a storage memory and an accumulator, and the step of selecting the calculation mode to perform digital calculation on the first digital signal and the second digital signal in the storage circuit specifically includes:

[0019] The input data is simultaneously applied to the memory bank in a most significant bit first and bit serial manner, and the adder tree adds the multiple output data to obtain a 12-bit adder tree output;

[0020] The adder tree outputs are accumulated over multiple cycles through an accumulator to output the accumulated result.

[0021] The present invention also proposes a non-volatile memory read-write calculation circuit based on the above non-volatile memory read-write calculation method, comprising:

[0022] Storage circuit;

[0023] Latch circuit;

[0024] A control circuit is connected to the storage circuit and the latch circuit respectively, and is used to receive a control signal and control the non-volatile memory to enter one of a write mode, a read mode or a calculation mode; in the write mode, the control circuit writes a first digital signal and a second digital signal to the storage circuit in sequence through a two-step write method; in the read mode, the control circuit digitally reads the first digital signal and the second digital signal in the storage circuit and latches and outputs them through a latch circuit; in the calculation mode, the control circuit digitally calculates the first digital signal and the second digital signal in the storage circuit.

[0025] Optionally, the non-volatile memory read-write calculation circuit further includes:

[0026] an address decoder for outputting input data for use as a word line;

[0027] A write circuit is connected to the address decoder, and is used to control the voltages of a source line, a bit line and an inverted bit line according to the input data.

[0028] Optionally, the non-volatile memory read-write calculation circuit further includes:

[0029] A storage repository, the storage repository being used to store input data output by the address decoder;

[0030] Addition tree;

[0031] accumulator;

[0032] The control circuit is used for adding a plurality of output data in the storage memory through an addition tree to obtain a 12-bit addition tree output, and controlling an accumulator to accumulate the addition tree output of multiple cycles to output an accumulation result.

[0033] Optionally, the non-volatile memory read-write calculation circuit further includes:

[0034] A test circuit is used to perform logic test, timing test and cache test on a non-volatile memory read and write calculation circuit.

[0035] The present invention also provides a storage device, comprising the non-volatile memory read-write calculation circuit as described above.

[0036] The technical solution of the present invention firstly writes the first digital signal and the second digital signal to the storage circuit in sequence through a two-step writing method to complete the data storage of the storage circuit; then selects the reading mode to digitally read the first digital signal and the second digital signal in the storage circuit and then latches the output through a latch circuit to complete the data reading of the storage circuit; or selects the calculation mode to digitally calculate the first digital signal and the second digital signal in the storage circuit to complete the data calculation of the storage circuit. The writing method of the two-step writing method and the digital reading method can solve the problem that the reading circuit of the non-volatile memory reads too slowly and cannot perform digital storage calculation. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary personnel in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0038] Figure 1 It is a flow chart of the method steps of an embodiment of a non-volatile memory read and write calculation method of the present invention.

[0039] Figure 2 It is a flow chart of the method steps of another embodiment of the non-volatile memory read and write calculation method of the present invention.

[0040] Figure 3 It is a method step flow chart of another embodiment of the non-volatile memory read and write calculation method of the present invention.

[0041] Figure 4 It is a functional module diagram of an embodiment of a non-volatile memory read-write calculation circuit of the present invention.

[0042] Figure 5 It is a circuit structure diagram of an embodiment of a non-volatile memory read-write calculation circuit of the present invention.

[0043] Figure 6It is a schematic diagram of the working principle of the two-step writing method in the non-volatile memory read-write calculation method of the present invention.

[0044] Figure 7 It is a waveform diagram of digital reading and digital calculation in the non-volatile memory read-write calculation method of the present invention.

[0045] Figure 8 It is a schematic diagram of the architecture of an embodiment of the non-volatile memory read-write calculation circuit of the present invention for performing digital in-memory calculation. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0047] In the embodiments and the scope of the patent application, unless the text specifically defines the article, "a", "an", "the" and "the" may also include plural forms. If there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features.

[0048] It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when an element is said to be "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can also be intermediate elements. In addition, the "connection" or "coupling" used herein can include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0049] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as herein.

[0050] In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0051] Compute-in-Memory (CIM) is an emerging computing architecture that is widely used in artificial intelligence (AI) chips and neural network accelerators. According to the different signal domains used, CIM is divided into analog CIM and digital CIM. Analog CIM mainly performs calculations in the analog signal domain, while digital CIM mainly performs calculations in the digital signal domain. Analog Compute-in-Memory (ACIM) is widely used to efficiently perform multiplication and accumulation operations in a variety of analog domain signals (such as charge, current, and voltage). Analog CIM uses different memory devices, including volatile memories such as static random access memory (SRAM) and dynamic random access memory (DRAM) and non-volatile memories (NVM), such as resistive memory (RRAM), magnetic memory (MRAM), and phase change memory (PCM). The values ​​stored in these non-volatile memories are expressed as high and low resistance values.

[0052] However, the value stored in NVM is the resistance value, not the digital 0 or digital 1 (VSS or VDD) on the voltage, and cannot be directly output to the digital circuit for calculation. The traditional NVM reading circuit first precharges the parasitic capacitance of the bit line to VDD, and then opens the word line of the NVM to be read, so that the bit line capacitance is discharged through the NVM, and the discharge rate is negatively correlated with the resistance: the larger the resistance, the slower the discharge. The bit line voltage is then compared with the reference voltage through the sense amplifier (SA) to read the value stored in the NVM, and it is converted into a digital 0 or digital 1 on the voltage, which can then be output to the digital circuit for calculation. However, the traditional NVM reading circuit faces some problems. If there are too many NVMs connected to the bit line, the parasitic capacitance and parasitic resistance of the bit line will be too large, making the discharge time longer and the reading speed slower, thereby lowering the computing throughput.

[0053] In order to solve the above problems, the present invention proposes a non-volatile memory read-write calculation method, which is applied to a non-volatile memory read-write calculation circuit.

[0054] Reference Figure 1 In one embodiment, the non-volatile memory read-write calculation circuit includes a storage circuit 10 and a latch circuit 20, and the non-volatile memory read-write calculation method includes the following steps:

[0055] S100, writing a first digital signal and a second digital signal into the storage circuit 10 in sequence by a two-step writing method;

[0056] S200 , selecting a read mode to digitally read the first digital signal and the second digital signal in the storage circuit 10 through the latch circuit 20 and then latch and output them, or selecting a calculation mode to digitally calculate the first digital signal and the second digital signal in the storage circuit 10 .

[0057] In this embodiment, the storage circuit 10 and the latch circuit 20 can constitute a bit unit. In the system of in-memory calculation, multiple bit units can be included to calculate the data in the multiple bit units. The storage circuit 10 can be composed of multiple transistors and multiple non-volatile memories with resistive properties, such as two transistors and two resistive non-volatile memories. One resistive non-volatile memory can be used to store data, which can be 1 or 0, and the other resistive non-volatile memory can be used to store the complementary value of the data. The latch circuit 20 can be composed of multiple transistors, which can be used to amplify the voltage in the circuit and latch the comparison result of the data in the storage circuit 10.

[0058] For data writing to non-volatile memory, a two-step writing method can be used to write the first digital signal and the second digital signal to the storage circuit 10 in sequence. For example, digital signals are usually 0 or 1, so the first digital signal can be 0, representing a low voltage; the second digital signal can be 1, representing a high voltage. After the data writing is completed, the digital signal in the storage circuit 10 can be digitally read, or the first digital signal and the second digital signal in the storage circuit 10 can be digitally calculated and the calculation result can be output. For example, the resistance values ​​between two resistive non-volatile memories are different, so the discharge rate is different, so an input-related differential voltage is generated between the two resistive non-volatile memories, and the voltage is then converted to VDD or 0V output and latched by the latch circuit 20, VDD represents a digital signal 1, and 0V represents a digital signal 0. Through a bit unit composed of multiple transistors and multiple non-volatile memories with resistive properties, after using software to extract parasitic resistance and capacitance from the actual circuit layout, combined with the simulation results of the model provided by the foundry, the average delay for data reading of the non-volatile memory can be obtained. The use of the reading method and circuit structure in this solution can reduce the average delay in reading data from the non-volatile memory.

[0059] The technical solution of the present invention firstly writes the first digital signal and the second digital signal to the storage circuit 10 in sequence through the two-step writing method to complete the data storage of the storage circuit 10; then selects the reading mode to digitally read the first digital signal and the second digital signal in the storage circuit 10 and then latches and outputs them through the latch circuit 20 to complete the data reading of the storage circuit 10; or selects the calculation mode to digitally calculate the first digital signal and the second digital signal in the storage circuit 10 to complete the data calculation of the storage circuit 10. The writing method of the two-step writing method and the digital reading method can solve the problem that the reading circuit of the non-volatile memory is too slow to read and cannot perform digital storage calculation.

[0060] Reference Figure 2 In one embodiment, the nonvolatile memory read / write calculation circuit further includes a source line, a bit line, and an inverted bit line connected to the storage circuit 10, and the step of sequentially writing the first digital signal and the second digital signal to the storage circuit 10 by the two-step writing method specifically includes:

[0061] S110, applying a first voltage to the source line, and grounding the bit line and the inverted bit line to write a first digital signal into the storage circuit 10;

[0062] S120 , setting the source line to a second voltage, acquiring and applying the first voltage or the second voltage to the bit line and the inverted bit line according to the write data, so as to write a second digital signal to the storage circuit 10 .

[0063] In this embodiment, the source line is a line for providing current or voltage, the bit line is a line connecting the storage circuit 10, which is usually used to read or write data, and the inverse bit line is a line corresponding to the bit line, which is usually used to provide an inverse signal of the bit line. The two-step writing method in this embodiment can achieve efficient writing in the bit unit without adding additional transistors. First, the first digital signal is written to the two non-volatile memories in the storage circuit 10. The first digital signal can be 0. Specifically, the first voltage can be applied to the source line of the selected row through the transmission gate, and the bit line and the inverse bit line are grounded at the same time. The first voltage can be a high voltage; secondly, the second digital signal is written to the target non-volatile memory, the source line is set to the second voltage, the second voltage can be 0V, and the first voltage or the second voltage is applied to the bit line and the inverse bit line according to the storage value to be written. In this way, the writing of data 0 and 1 to the storage circuit 10 can be completed.

[0064] In one embodiment, the non-volatile memory read / write calculation circuit further includes an address decoder 40, and when executing the step of sequentially writing the first digital signal and the second digital signal to the storage circuit 10 by the two-step writing method, further includes:

[0065] The input data outputted by the address decoder 40 is acquired, and the voltages on the source line, the bit line and the inverted bit line are adjusted according to the input data.

[0066] In this embodiment, the address decoder 40 can convert the input address signal into a selection signal of a specific storage unit. The main function is to ensure that only the target storage unit is activated during a read or write operation, thereby achieving accurate access to the data. The address decoder 40 in this embodiment can work as an 8-bit to 256-bit decoder, and outputs input data used as word lines, and the input data can be IN and INB signals. The control circuit 30 of the source line, bit line and inverted bit line can adjust the voltage on the source line, bit line and inverted bit line according to the input data.

[0067] Reference Figure 3 In one embodiment, the step of selecting the read mode to digitally read the first digital signal and the second digital signal in the storage circuit 10 specifically includes:

[0068] S210, obtaining input data output by the address decoder 40, and connecting the bit line and the inverted bit line to a first voltage;

[0069] S220, performing AND gate calculation according to the input data and the first digital signal and the second digital signal in the storage circuit 10 to obtain output data, and latching and outputting the output data through the latch circuit 20;

[0070] S230 , adding the output data through the addition tree 70 , and outputting the storage data in the storage circuit 10 .

[0071] In this embodiment, when the input data outputted by the address decoder 40 is obtained as 0, that is, the voltage is 0V, the transistor in the storage circuit 10 will precharge the connection node between the storage circuit 10 and the latch circuit 20 to VDD, which in turn causes the latch circuit 20 to discharge its output node to 0V. When the input data becomes 1 and the voltage is VDD, the two resistive non-volatile memories in the storage circuit 10 discharge the connection node between the storage circuit 10 and the latch circuit 20 respectively, but because the resistance values ​​of the two resistive non-volatile memories are different, the discharge rates of the connection node between the storage circuit 10 and the latch circuit 20 are different, so an input-related differential voltage is generated between the connection node between the storage circuit 10 and the latch circuit 20. This voltage is then converted to VDD or 0V output and latched by the latch structure, so that it always has a certain potential and will not cause the input node of the addition tree 70 to be suspended. Furthermore, according to the read and calculated waveforms, the truth table of the bit unit calculation can be obtained, and the output result is the result of the AND gate of the input data and the data stored in the resistive non-volatile memory, thereby realizing binary single-bit multiplication, and can also be regarded as reading the data stored in the resistive non-volatile memory. This process is also called "digitalization in the bit unit", because it digitizes the resistance value stored in the bit unit to 0 or 1 on the voltage according to the input data. The read results of the latch output of the latch circuit 20 can be added through the addition tree 70, and finally output as the storage data of the selected row. This reading method is also called reading by calculation, so that the reading operation of the data stored in the resistive non-volatile memory of the storage circuit 10 can be realized through the non-volatile memory read and write calculation circuit.

[0072] In one embodiment, the non-volatile memory read / write calculation circuit further includes a storage memory 60 and an accumulator 80, and the step of selecting the calculation mode to perform digital calculation on the first digital signal and the second digital signal in the storage circuit 10 specifically includes:

[0073] The input data is simultaneously applied to the memory bank 60 in a most significant bit first and bit serial manner, and the adder tree 70 adds the multiple output data to obtain a 12-bit adder tree 70 output;

[0074] The output of the adder tree 70 for multiple cycles is accumulated by the accumulator 80 to output the accumulated result.

[0075] In this embodiment, in the calculation mode, multiple input data can be applied to the memory bank 60 at the same time in a most significant bit first and bit serial manner; the most significant bit first means that when inputting data, the most significant bit of each data word is input first, and the bit serial input means that the data is input one by one in bits, rather than in bytes or larger units. This method can reduce input delays and allow more efficient parallel processing. The addition tree 70 adds the calculation results of each bit unit to obtain a 12-bit addition tree 70 output. The accumulator 80 is composed of a shift adder and a partial sum adder. The accumulator 80 can accumulate the outputs of the addition tree 70 for multiple cycles and output the corresponding accumulated results. Flexible input precision can be achieved, and the shift addition outputs of different memory banks 60 can be integrated to achieve flexible weight precision configuration.

[0076] The present invention also provides a non-volatile memory read-write calculation circuit based on the non-volatile memory read-write calculation method.

[0077] Reference Figure 4 In one embodiment, the non-volatile memory read-write calculation circuit includes:

[0078] A storage circuit 10;

[0079] Latch circuit 20;

[0080] The control circuit 30 is connected to the storage circuit 10 and the latch circuit 20 respectively. The control circuit 30 is used to receive a control signal and control the non-volatile memory to enter one of a write mode, a read mode or a calculation mode; in the write mode, the control circuit 30 writes the first digital signal and the second digital signal to the storage circuit 10 in sequence through a two-step write method; in the read mode, the control circuit 30 digitally reads the first digital signal and the second digital signal in the storage circuit 10 and latches and outputs them through the latch circuit 20; in the calculation mode, the control circuit 30 digitally calculates the first digital signal and the second digital signal in the storage circuit 10.

[0081] In this embodiment, the storage circuit 10 and the latch circuit 20 can constitute a bit unit. In the non-volatile memory read and write calculation circuit of the in-memory computing system, multiple bit units can be included to calculate the data in the multiple bit units. The multiple bit units can be divided into multiple rows, such as 256 rows, and each row can also be provided with multiple bit units. The storage circuit 10 can be composed of multiple transistors and multiple non-volatile memories with resistive properties. The transistors can be MOS tubes; the latch circuit 20 can be composed of multiple transistors, which can be used to amplify the voltage in the circuit and latch the comparison result of the data in the storage circuit 10. The specific circuit structure of the storage circuit 10 and the latch circuit 20 can be referred to. Figure 5, wherein the first resistive nonvolatile memory R0, the second resistive nonvolatile memory R1, the fifth transistor M5 and the sixth transistor M6 constitute a storage circuit 10; the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the seventh transistor M7 and the eighth transistor M8 constitute a latch circuit 20, and the ninth transistor M9 and the tenth transistor M10 are transistors commonly connected to the bit cells of each row.

[0082] The control circuit 30 controls the storage circuit 10 and the latch circuit 20 to read, write and calculate data, which can be referred to the description of the above embodiment and will not be repeated here. The reading method and circuit structure in this solution can reduce the average delay of data reading of the non-volatile memory.

[0083] Reference Figure 4 In one embodiment, the non-volatile memory read-write calculation circuit further includes:

[0084] An address decoder 40 for outputting input data for use as a word line;

[0085] The write circuit 50 is connected to the address decoder 40 and is used to control the voltages of the source line, the bit line and the inverted bit line according to the input data.

[0086] In this embodiment, the address decoder 40 can work as an 8-bit to 256-bit decoder, and outputs input data used as word lines, and the input data can be IN and INB signals. The write circuit 50 includes a source line control circuit, a bit line control circuit, and an inverted bit line control circuit for writing bit units. The source line control circuit, the bit line control circuit, and the inverted bit line control circuit can adjust the voltages on the source line, the bit line, and the inverted bit line according to the input data to meet the voltage requirements for data reading and writing.

[0087] Reference Figure 4 In one embodiment, the non-volatile memory read-write calculation circuit further includes:

[0088] A storage memory 60, the storage memory 60 is used to store the input data output by the address decoder 40;

[0089] Addition tree 70;

[0090] Accumulator 80;

[0091] The control circuit 30 is used to add the multiple output data in the memory bank 60 through the addition tree 70 to obtain a 12-bit addition tree 70 output, and control the accumulator 80 to accumulate the addition tree 70 output of multiple cycles to output the accumulation result.

[0092] In this embodiment, the computing architecture based on non-volatile memory may include 64 memory banks 60, each memory bank 60 includes 256×4 bit cells, a 7-level addition tree 70 and an accumulator 80, and the 256×4 bit cells refer to 256 rows, with 4 bit cells in each row. Multiple input data can be applied to the memory bank 60 at the same time in a most significant bit first and bit serial manner. The addition tree 70 adds the calculation results of each bit cell to obtain a 12-bit addition tree 70 output. The accumulator 80 is composed of a shift adder and a partial sum adder. The accumulator 80 can accumulate the output of the addition tree 70 for multiple cycles and output the corresponding accumulation result. Flexible input precision can be achieved, and the shift addition outputs of different memory banks 60 can be integrated to achieve flexible weight precision configuration.

[0093] In one embodiment, the non-volatile memory read-write calculation circuit further includes:

[0094] A test circuit is used to perform logic test, timing test and cache test on a non-volatile memory read and write calculation circuit.

[0095] In this embodiment, the test circuit can use the on-chip cache and the on-chip clock generator for full-speed testing, and use the scan chain (serial-parallel conversion circuit) to write and read the cache. The on-chip cache is a high-speed memory integrated inside the chip, which is used to temporarily store data to improve the access speed of the processor. During the test, the on-chip cache can be used to store test data and intermediate results. The on-chip clock generator is used to generate the required clock signal to drive the operation of the circuit. In the full-speed test, the clock frequency is usually set to the maximum operating frequency of the chip to ensure that the test is performed under the most extreme conditions. The scan chain is formed by connecting multiple triggers in series to form a chain, so that the circuit can be tested through serial input and output. In the test of the memory, the scan chain can be used to write and read the on-chip cache. In this way, the test circuit can complete logic testing, timing testing and cache testing for the non-volatile memory read and write calculation circuit.

[0096] In order to better illustrate the technical concept of the present invention, Figures 1 to 8 The present invention describes the workflow of reading, writing and calculating the non-volatile memory:

[0097] The bit unit proposed in this scheme consists of 8 transistors (Transistor) and 2 resistive non-volatile storage (Resistor), hereinafter referred to as 8T2R bit unit. The specific circuit structure can be referred to Figure 5. The 8T2R consists of two parts, a 2T2R structure consisting of two transistors and two resistive non-volatile memories (a storage circuit 10 for storing data), and a latch structure (a latch circuit 20 for amplifying voltage and latching the comparison result). For the 8T2R bit cell, the first resistive non-volatile memory R0 can store data, and the second resistive non-volatile memory R1 can store the complementary value of the data in R0. The bit cell array supports comprehensive write, read and calculate functions, which are controlled by the source line (SL) and bit line / anti-bit line (BL / BLB) circuits (such as Figure 8 As shown). This scheme adopts a novel two-step writing scheme to achieve efficient writing in 8T2R bit cells without adding additional transistors: Step 1: Write '0' to two resistive non-volatile memories (NVMs), apply VDD voltage to SL of the selected row through the transmission gate, and ground BL and BLB at the same time; Step 2: Write '1' to the target resistive non-volatile memory, set SL to 0V, and apply VDD or 0V to BL / BLB according to the storage value to be written. For example, when writing '1' to R0, VDD is applied to BL and 0V is applied to BLB; when writing '1' to R1, VDD is applied to BBL and 0V is applied to LB. The specific writing process can be referred to Figure 6 .

[0098] In the calculation mode, BL and BLB are always connected to the VDD voltage. When the input data (IN) = 0, that is, the voltage is 0V, the fifth transistor M5 and the sixth transistor M6 precharge the Di+ and Di- nodes to VDD, which in turn causes the eighth transistor M8 to discharge the output node to 0V. When the input data IN becomes 1, that is, the voltage is VDD, the ninth transistor M9 and the tenth transistor M10, R0 and R1 discharge the Di+ and Di- nodes respectively, but due to the different resistance values ​​of R0 and R1, the discharge rates of the Di+ and Di- nodes are different, so an input-related differential voltage ΔVDi is generated between Di+ and Di-. This voltage ΔVDi is then converted to VDD or 0V output and latched by the latch circuit 20, so that it always has a certain potential and will not cause the input node of the addition tree 70 to be suspended. In this solution, the reading and calculation of the resistive non-volatile memory achieves an output rise delay of 88ps and a fall delay of 22ps (after using software to extract parasitic resistance and capacitance from the actual circuit layout, combined with the simulation results of the model provided by the foundry), with an average delay of 55ps. Figure 7As shown in the reading and calculation waveforms in . Further, according to the reading and calculation waveforms, the truth table of this bit unit calculation can be obtained, and the output result is the result of AND gate calculation of the input data (IN) and the first resistive non-volatile memory R0 storage data (W), thereby realizing binary single-bit multiplication, which can also be regarded as reading the storage data. This process is also called "digitalization in the bit unit", because it digitizes the resistance value stored in the bit unit into 0 or 1 (VSS or VDD) on the voltage according to the input data.

[0099] It should be noted that, for a storage array composed of bit cells, the ninth transistor M9 and the tenth transistor M10 can be shared with other bit cells in the same row, thereby reducing the transistor overhead. If the input data does not flip in subsequent clock cycles (for example, IN=11...1 or 00...0), no excessive digitization will occur, and the output state remains unchanged, thereby achieving zero dynamic power consumption.

[0100] The in-memory computing solution composed of the 8T2R bit cell array and other peripheral circuits can be referred to Figure 8 , the architecture consists of four main components:

[0101] (1) Write circuit 50: including a source line (SL) control circuit and a bit line / bit line bar (BL / BLB) control circuit for bit cell writing;

[0102] (2) write / read / calculate control circuit and address decoder 40;

[0103] (3) 64 nvDCIM memory banks 60, each memory bank 60 contains 256×4 bit cells, a 7-level adder tree 70 and an accumulator 80;

[0104] (4) Test circuit, use on-chip cache and on-chip clock generator for full-speed testing, and use scan chain (serial-to-parallel conversion circuit) to write and read the cache.

[0105] In write mode, the address decoder 40 operates as an 8-bit to 256-bit decoder, outputting IN and INB signals used as word lines (WL), ie, input data, and the SL / BL / BLB control circuit adjusts the voltage on SL / BL / BLB according to the input data.

[0106] In read mode, the decoder generates step signals only on IN and INB of the selected row (IN: 0→1, INB: 1→0), where the 8T2R bit cell performs an intra-bit cell digitization operation, which essentially implements an AND operation between the input (IN=1) and the data stored in the resistive non-volatile memory (e.g. Figure 8As shown in ). Further, since only the input of the selected row is 1 and the other rows are 0, only the selected row is read, and the bit unit reading results of the other rows are all 0. The adder tree 70 adds the reading results of each row and finally outputs the storage data of the selected row. This reading method is also called reading by calculation, and the reading operation of the storage array is realized by using a calculation circuit. In this way, the reading of the non-volatile memory can be realized by using only two control signals.

[0107] In the digital in-memory calculation mode, 256 input data are simultaneously applied to the memory bank 60 in a most significant bit first and bit serial manner. The adder tree 70 adds the calculation results of the bit cells of each row, that is, adds the 256 OUT[3:0] from OUT0[3:0] to OUT255[3:0] to obtain a 12-bit adder tree 70 output; in addition, the transistor width of the third transistor M3 and the fourth transistor M4 is slightly larger than that of other transistors, thereby enhancing the driving capability of the adder tree 70. The accumulator 80 is composed of a shift adder and a partial sum adder. It accumulates the output of the adder tree 70 of multiple cycles to achieve flexible input precision, and integrates the shift addition outputs of different memory banks 60 to achieve flexible weight precision configuration.

[0108] The invention also provides a storage device.

[0109] In one embodiment, the storage device includes the non-volatile memory read-write calculation circuit as described above. It is understandable that, since the non-volatile memory read-write calculation circuit is used in the storage device of the present invention, the embodiment of the storage device of the present invention includes all technical solutions of all embodiments of the non-volatile memory read-write calculation circuit, and the technical effects achieved are also exactly the same, which will not be repeated here.

[0110] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A non-volatile memory read-write calculation method, applied to a non-volatile memory read-write calculation circuit, characterized in that: The non-volatile memory read-write calculation circuit includes a storage circuit and a latch circuit, and the non-volatile memory read-write calculation method includes the following steps: Writing a first digital signal and a second digital signal into the storage circuit in sequence by a two-step writing method; Select the read mode to digitally read the first digital signal and the second digital signal in the storage circuit through the latch circuit and then latch and output them, or select the calculation mode to digitally calculate the first digital signal and the second digital signal in the storage circuit.

2. The non-volatile memory reading and writing calculation method according to claim 1, characterized in that: The non-volatile memory read-write calculation circuit also includes a source line, a bit line and an inverted bit line connected to the storage circuit. The step of sequentially writing the first digital signal and the second digital signal to the storage circuit by the two-step writing method specifically includes: Applying a first voltage to the source line and grounding the bit line and the inverted bit line to write a first digital signal to the storage circuit; The source line is set to a second voltage, and the first voltage or the second voltage is applied to the bit line and the inverted bit line according to the write data, so as to write a second digital signal to the storage circuit.

3. The non-volatile memory reading and writing calculation method as claimed in claim 2, characterized in that: The non-volatile memory read-write calculation circuit also includes an address decoder, and when executing the step of sequentially writing the first digital signal and the second digital signal into the storage circuit by the two-step writing method, it also includes: The input data output by the address decoder is obtained, and the voltages on the source line, the bit line, and the inverted bit line are adjusted according to the input data.

4. The non-volatile memory reading and writing calculation method as claimed in claim 3, characterized in that: The step of selecting a read mode to digitally read the first digital signal and the second digital signal in the storage circuit specifically includes: Obtain input data output by the address decoder, and connect the bit line and the inverted bit line to a first voltage; Perform an AND gate calculation according to the input data and the first digital signal and the second digital signal in the storage circuit to obtain output data, and latch and output it through a latch circuit; The output data is added through the addition tree, and the storage data in the storage circuit is output.

5. The non-volatile memory reading and writing calculation method as claimed in claim 4, characterized in that: The non-volatile memory read-write calculation circuit also includes a storage memory and an accumulator. The step of selecting the calculation mode to perform digital calculation on the first digital signal and the second digital signal in the storage circuit specifically includes: The input data is simultaneously applied to the memory bank in a most significant bit first and bit serial manner, and the adder tree adds the multiple output data to obtain a 12-bit adder tree output; The adder tree outputs are accumulated over multiple cycles through an accumulator to output the accumulated result.

6. A non-volatile memory read-write calculation circuit based on the non-volatile memory read-write calculation method according to any one of claims 1 to 5, characterized in that: include: Storage circuit; Latch circuit; A control circuit is connected to the storage circuit and the latch circuit respectively, and is used to receive a control signal and control the non-volatile memory to enter one of a write mode, a read mode or a calculation mode; in the write mode, the control circuit writes a first digital signal and a second digital signal to the storage circuit in sequence through a two-step write method; in the read mode, the control circuit digitally reads the first digital signal and the second digital signal in the storage circuit and latches and outputs them through a latch circuit; in the calculation mode, the control circuit digitally calculates the first digital signal and the second digital signal in the storage circuit.

7. The non-volatile memory read-write calculation circuit according to claim 6, characterized in that: The non-volatile memory read-write calculation circuit also includes: an address decoder for outputting input data for use as a word line; A write circuit is connected to the address decoder, and is used to control the voltages of a source line, a bit line and an inverted bit line according to the input data.

8. The non-volatile memory read-write calculation circuit according to claim 7, characterized in that: The non-volatile memory read-write calculation circuit also includes: A storage repository, the storage repository being used to store input data output by the address decoder; Addition tree; accumulator; The control circuit is used for adding a plurality of output data in the storage memory through an addition tree to obtain a 12-bit addition tree output, and controlling an accumulator to accumulate the addition tree output of multiple cycles to output an accumulation result.

9. The non-volatile memory read-write calculation circuit according to claim 6, characterized in that: The non-volatile memory read-write calculation circuit also includes: A test circuit is used to perform logic test, timing test and cache test on a non-volatile memory read and write calculation circuit.

10. A storage device, characterized in that: It comprises a non-volatile memory read-write calculation circuit as described in any one of claims 6 to 9.

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