Random data polarity inversion of computational weight data in computational processing systems in digital memory

Abstract

The invention relates to random data polarity inversion of computational weight data in a computational processing system in digital memory. Computation weight data for in-memory computation operations is written to memory cells in a memory array by randomly selected polarity inversion. During execution of a compute operation in memory, compute weight data is read from memory cells in a memory array. A polarity inversion is applied to the read computational weight data when the read computational weight data is written to a memory cell in the memory array by a randomly selected polarity inversion.

Claims

1. A circuit comprising: A memory array includes a plurality of memory cells arranged in a matrix having a plurality of rows and a plurality of columns, each row including at least one word line connected to the memory cells in the row, and each column including at least one bit line connected to the memory cells in the column. The memory unit stores computational weight data for in-memory computational operations; as well as The input / output circuitry for each column includes: The write circuit is configured to write the calculated weight data into memory cells in the memory array using a randomly selected polarity reversal. as well as The read circuit is configured to read the computation weight data from memory cells in the memory array during the execution of computation operations in the memory, and to apply polarity reversal to the read computation weight data when the read computation weight data is written to memory cells in the memory array using the randomly selected polarity reversal.

2. The circuit of claim 1, wherein the polarity reversal of the randomly selected computational weight data during writing is controlled by a control signal having a randomly selected logic state.

3. The circuit according to claim 2, wherein the control signal is generated in response to a random number generator circuit.

4. The circuit of claim 1 further includes a control circuit configured to generate a control signal having a first logic state and a second logic state, the first logic state causing the write circuit to write the calculated weight data without polarity reversal, and the second logic state causing the write circuit to write the calculated weight data with polarity reversal.

5. The circuit of claim 4, wherein the control circuit is further configured to allow the second logic state only when the sparsity of the computed weight data to be written to the memory array meets a sparsity threshold.

6. The circuit according to claim 4, further comprising: A word line driving circuit for each row, having an output configured to drive the word line of the row; as well as The row decoder circuit is configured to actuate at least one word line driver circuit in the word line driver circuit in response to the decoded access address when writing calculated weight data to a memory cell in the memory array. The control circuit further includes a reversal record, which stores the address of the calculated weight data that has been stored in the memory array using polarity reversal.

7. The circuit of claim 6, wherein during the execution of the computation operation in the memory, the line decoder circuit further actuates one or more word line drive circuits in response to the decoded computation address, and wherein the read circuit applies the polarity reversal when the computation weight data is read from the memory array at one of the addresses stored in the inverted record.

8. The circuit of claim 1, wherein the input / output circuit is configured to apply the polarity reversal by XORing the data using a control signal derived from a random number and a sparsity threshold for the memory.

9. The circuit of claim 8, wherein the random number is generated in response to the application of the same seed value during both writing to and from the memory cells in the memory array.

10. The circuit of claim 1, wherein the input / output circuit is configured to apply the same seed value for random number generation when writing to and from the memory cells in the memory array, to control the polarity reversal of the random selection.

11. The circuit of claim 1, further comprising a processing circuit configured to receive feature data computed in the memory and perform a computation operation based on the feature data and data generated by the input / output circuit based on the read computation weight data.

12. The circuit of claim 1, wherein each memory cell is a static random access memory (SRAM) cell or other logic bit cell.

13. The circuit according to claim 12, wherein the SRAM cell is one of a 6T cell or an 8T cell.

14. The circuit according to claim 1, wherein the in-memory computation operation is a digital memory computation.

15. A method for processing computational weight data for in-memory computational operations, comprising: The calculated weight data is written into the memory cells of the memory array by randomly selecting polarity reversals; The computational weight data is read from memory cells in the memory array during the execution of the computational operation in the memory; as well as When the read computational weight data is written into a memory cell in the memory array using the randomly selected polarity reversal, the polarity reversal is applied to the read computational weight data.

16. The method of claim 15, wherein writing includes applying polarity reversal to the computed weight data during writing in response to a control signal having a randomly selected logic state.

17. The method of claim 16, further comprising generating the control signal using a random number generator circuit.

18. The method of claim 16, further comprising: The application of polarity reversal is permitted only if the sparsity of the computed weight data to be written to the memory array meets a sparsity threshold.

19. The method of claim 16 further includes storing the addresses of the memory array that already contain computational weight data using polarity reversal in a reversal record.

20. The method of claim 19, wherein applying the polarity reversal includes applying the polarity reversal when the computed weight data is read from the memory array at one of the addresses stored in the reversal record.

21. The method of claim 16, further comprising applying the polarity reversal by XORing the data using a control signal derived from a random number and a sparsity threshold for the memory.

22. The method of claim 21, further comprising applying the same seed value to generate the random number both when writing to and from the memory cells in the memory array.

23. The method of claim 16, further comprising applying the same seed value for random number generation during both writing to and from the memory cells in the memory array, to control the polarity reversal of the random selection.

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