An InAs / InP quantum dot single photon source device and a preparation method thereof

Abstract

The present application discloses an InAs / InP quantum dot single photon source device and a preparation method thereof, including: preparing an InP substrate, which sequentially includes an InAs / InP quantum dot layer, an InGaAs sacrificial layer, and an InP substrate layer from top to bottom; depositing a SiO2 spacer layer on the surface of the InAs / InP quantum dot layer of the InP substrate; evaporating an Au mirror layer on the surface of the SiO2 spacer layer; evaporating an Au mirror layer on the surface of a GaAs substrate; using flip-chip bonding technology to bond the Au mirror layer of the InP substrate to the Au mirror layer of the GaAs substrate; wet etching to remove the InP substrate layer and the InGaAs sacrificial layer; depositing a first mask layer on the surface of the InAs / InP quantum dot layer; preparing a second mask layer on the surface of the first mask layer, exposing and developing; dry etching the first mask layer; dry etching the InAs / InP quantum dot layer to obtain an InAs / InP quantum dot single photon source device. It can enhance the light field confinement and reflection efficiency, realize a high-Q resonator, and improve the brightness and purity of the single photon source.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor materials and devices, and particularly to an InAs / InP quantum dot single photon source device and a preparation method thereof. Background Art

[0002] With the rapid development of quantum communication and quantum information technologies, single photon sources in the communication bands (1.3 µm and 1.55 µm) have become key components for realizing long-distance and highly secure quantum communication. Semiconductor quantum dots, also known as Quantum dots (QDs), have become ideal candidate materials for single photon sources due to their excellent single photon emission characteristics (high purity, high brightness, and wavelength tunability). Among many material systems, II-VI, III-V group quantum dots represented by cadmium selenide (CdSe) and indium phosphide (InP), and perovskite quantum dots have the most mature development, with a luminous efficiency reaching over 90%. In particular, InP-based InAs quantum dots stand out due to their natural matching with the communication bands. The bandgap of InP material (~1.35 eV) enables it to efficiently cover the 1.3 µm and 1.55 µm bands, while the quantum confinement effect and high-efficiency light emission characteristics of InAs quantum dots further improve the performance of the single photon source.

[0003] However, traditional InP substrates have certain optical absorption losses in the near-infrared band, which limits the device efficiency. Moreover, InP material itself is relatively brittle, the complexity of preparing optical microcavities is high, and there are still disadvantages such as optical loss, thermal management challenges, wavelength tuning difficulties, mechanical stability problems, and high costs that need further research and optimization. Summary of the Invention

[0004] To address the above deficiencies in the art, this application aims to provide an InAs / InP quantum dot single photon source device and a preparation method thereof.

[0005] According to one aspect of this application, a preparation method of an InAs / InP quantum dot single photon source device is provided, including:

[0006] Preparing an InP substrate, which sequentially includes an InAs / InP quantum dot layer, an InGaAs sacrificial layer, and an InP substrate layer from top to bottom;

[0007] Depositing a SiO 2 spacer layer on the surface of the InAs / InP quantum dot layer of the InP substrate;

[0008] Evaporating an Au mirror layer on the surface of the SiO 2 spacer layer;

[0009] Evaporating an Au mirror layer on the surface of a GaAs substrate;

[0010] The Au mirror layer of the InP substrate is combined with the Au mirror layer of the GaAs substrate by using flip-chip bonding technology;

[0011] The InP substrate layer and the InGaAs sacrificial layer are removed by wet etching;

[0012] A first mask layer is deposited on the surface of the InAs / InP quantum dot layer;

[0013] A second mask layer is prepared on the surface of the first mask layer, and exposure and development are carried out;

[0014] The first mask layer is dry-etched;

[0015] The InAs / InP quantum dot layer is dry-etched to obtain an InAs / InP quantum dot single-photon source device.

[0016] According to some embodiments of the present application, the first mask layer is a SiO 2 mask layer.

[0017] According to some embodiments of the present application, the InGaAs sacrificial layer is an In 0.53 Ga 0.47 As sacrificial layer;

[0018] According to some embodiments of the present application, the InAs / InP quantum dot layer is an InP layer containing InAs quantum dots.

[0019] According to some embodiments of the present application, removing the InP substrate layer and the InGaAs sacrificial layer by wet etching includes: removing the InP substrate layer by wet etching with HCl, and then using H 3 PO 4 :H 2 O 2 :H 2 O mixed solution to wet-etch and remove the InGaAs sacrificial layer.

[0020] According to some embodiments of the present application, the volume ratio of H 3 PO 4 :H 2 O 2 :H 2 O is 2:3:30.

[0021] According to some embodiments of the present application, the exposure voltage is 30 kV - 125 kV, and optionally, the exposure voltage is 125 kV.

[0022] According to some embodiments of the present application, the thickness of the InAs / InP quantum dot layer is 310 nm, the thickness of the InGaAs sacrificial layer is 200 nm, and the thickness of the InP substrate layer is 350 μm.

[0023] According to some embodiments of the present application, SiO 2 The thickness of the mask layer is 100 nm - 200 nm. Optionally, SiO 2 The thickness of the mask layer is 150 nm.

[0024] According to another aspect of the present application, there is also provided an InAs / InP quantum dot single photon source device prepared by the preparation method of the above-mentioned InAs / InP quantum dot single photon source device.

[0025] According to some embodiments of the present application, the InAs / InP quantum dot single photon source device has a ring Bragg grating microcavity structure.

[0026] Compared with the prior art, the present application has at least the following beneficial effects:

[0027] The present application provides a preparation method for an InAs / InP quantum dot single photon source device. By introducing a substrate removal technique to remove the InP substrate, the optical loss is significantly reduced and the thermal management performance is improved.

[0028] The preparation method of the present application removes the InP substrate with a thickness of hundreds of micrometers by selecting the substrate transfer material of the InP substrate and controlling the stability of the combination of the InP substrate and the new substrate during the whole process. At the same time, the integrity and flatness of the film with a thickness of hundreds of nanometers left after substrate removal are ensured. The process accuracy of the ring Bragg grating with a size of hundreds of nanometers prepared on the surface of the InAs / InP film with a thickness of hundreds of nanometers is controlled.

[0029] The InAs / InP quantum dot single photon source device of the present application is an enhanced InAs / InP quantum dot single photon source device based on a ring Bragg grating structure, which has an alloy mirror reflective layer (Au mirror layer) and a ring Bragg grating structure. It can further enhance the light field confinement and reflection efficiency, realize a high-Q resonant cavity, thereby improving the brightness and purity of the single photon source; it also provides a new solution for the miniaturization and integration of photonic integrated circuits (PICs), and becomes an important direction for the research of single photon sources in the communication band. Description of the Drawings

[0030] Figure 1 It is a schematic structural diagram of an InP substrate of an exemplary embodiment of the present application.

[0031] Figure 2 It is a schematic process flow diagram of the preparation of an InAs / InP quantum dot single photon source device of an exemplary embodiment of the present application.

[0032] Figure 3 It is a comparative diagram of the stability of InP materials transferred onto three different substrates in an exemplary embodiment of the present application.

[0033] Figure 4 Scanning electron microscope image of the surface morphology of the material after being processed by the traditional wet etching technique for the exemplary embodiment of the present application.

[0034] Figure 5 Optical microscope and scanning electron microscope image characterization for the exemplary embodiment of the present application.

[0035] Figure 6 For the exemplary embodiment of the present application, the morphology image of the surface after bonding the InAs / InP thin film to a new substrate with NOA61 and depositing SiO 2 hard mask.

[0036] Figure 7 Comparison diagram of substrate transfer by flip-chip bonding technology and cured adhesive bonding technology for the exemplary embodiment of the present application.

[0037] Figure 8 Morphology image of the ring-shaped Bragg grating obtained by exposure at different acceleration voltages for the exemplary embodiment of the present application. Detailed implementation manners

[0038] Next, the technical solutions of the present application will be clearly and completely described in conjunction with the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present application.

[0039] It should be particularly noted that similar replacements and modifications made to the present application are obvious to those skilled in the art, and they are all considered to be included in the present application. Relevant personnel can clearly make changes or appropriate alterations and combinations to the methods and applications described herein without departing from the content, spirit and scope of the present application to implement and apply the technology of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0040] Unless otherwise specified in the present application, all are carried out according to conventional conditions or conditions recommended by the manufacturer. For the raw materials or auxiliary materials used, and for the reagents or instruments used without indicating the manufacturer, they are all conventional products that can be obtained through commercial purchase.

[0041] Next, the present application will be described in detail.

[0042] The present application provides an InAs / InP quantum dot single photon source device and a preparation method thereof, in particular an enhanced InAs / InP quantum dot single photon source device based on a ring-shaped Bragg grating structure. It overcomes the following problems existing in the art and promotes the practical application of InP materials in quantum communication and photonic integrated circuits.

[0043] Select the substrate transfer material for the InP substrate, control the stability of the bonding between the InP substrate and the new substrate throughout the process, and remove the InP substrate with a thickness of hundreds of micrometers. Overcome the problems of high complexity in preparing optical microcavities due to the brittleness of the InP material itself, and ensure the integrity and flatness of the film with a thickness of hundreds of nanometers left after substrate removal. At the same time, control the process accuracy of the nanoscale ring Bragg gratings prepared on the surface of the hundreds-of-nanometer InAs / InP film.

[0044] To solve the above technical problems, the present application can be implemented through the following technical solutions as Figure 2 shown below.

[0045] Preparation of InP substrate: The materials from top to bottom are: InP layer containing InAs quantum dots (hereinafter referred to as InAs / InP quantum dot layer), In 0.53 Ga 0.47 As sacrificial layer (hereinafter referred to as InGaAs), (100) InP substrate.

[0046] Pretreatment of InP substrate: Soak it in acetone, ethanol and deionized water in sequence, and then dry it with a nitrogen gun.

[0047] Preparation of spacer layer: Use a plasma-enhanced chemical vapor deposition system to deposit SiO 2 spacer layer.

[0048] Preparation of Au mirror layer: Use an electron beam evaporation coating system to evaporate the Au mirror layer on the surface of the InP substrate deposited with the SiO 2 spacer layer and on the surface of the new substrate GaAs.

[0049] Structure compounding: Use flip-chip bonding technology to firmly bond the Au mirror surface of the InP substrate to the Au mirror surface of the GaAs substrate.

[0050] Wet etching: Remove the InP substrate layer by wet etching with HCl, and then immediately use H 3 PO 4 :H 2 O 2 :H 2 O mixed solution for wet etching to remove the InGaAs sacrificial layer, leaving the InAs / InP quantum dot layer.

[0051] Preparation of the first mask layer: Use a plasma-enhanced chemical vapor deposition system to deposit a layer of SiO 2 on the surface of the InAs / InP quantum dot layer as the first mask layer for the ring Bragg grating.

[0052] Fabrication of the second mask layer: Spin-coat a layer of electron beam resist on the surface of the first mask layer, and bake it at a high temperature to form the second mask layer; then perform electron beam exposure using a voltage of 30 - 125 kV, and the pattern of the layout after development is reproduced on the electron beam resist.

[0053] Dry etching: Use an inductively coupled plasma etching machine to perform dry etching on the SiO 2 first mask layer. After etching is completed, use a stripping solution, organic solvent, and plasma stripping machine to remove the residual electron beam resist; use an inductively coupled plasma etching machine to perform dry etching on the InAs / InP quantum dot layer to obtain the enhanced InAs / InP quantum dot single-photon source device based on the ring-shaped Bragg grating structure of the present application.

[0054] The technical solution of the present application will be further introduced below in conjunction with specific embodiments.

[0055] Instrumentation: Electron beam evaporation coating system, model ADNANOTEK EBS150;

[0056] Plasma chemical vapor deposition system, model SAMCO PD-220NL;

[0057] Flip-chip bonder, model FINETECH FINEPLACER-96;

[0058] Electron beam exposure equipment, model Elionix ELS-F125;

[0059] Inductively coupled plasma etching machine, model Plasma Pro 100 Cobra.

[0060] Example 1

[0061] Preparation of InP substrate: The materials from top to bottom are as follows: 310 nm InAs / InP quantum dot layer, 200 nm InGaAs sacrificial layer, 350 μm (100) InP substrate (as Figure 1 shown).

[0062] Pre-treatment of InP substrate: Cut the InP substrate into 1 cm × 1 cm, soak it in acetone, ethanol, and deionized water for 5 min in sequence after cutting, and then blow it dry with a nitrogen gun.

[0063] Fabrication of the spacer layer: Use a plasma chemical vapor deposition system to deposit a 300 nm SiO 2 spacer layer; set the upper and lower electrode temperatures to 150 °C and 350 °C respectively, and select the gas as SiH diluted with 100 sccm Ar 4 (5% SiH 4 / 95% Ar) and 460 sccm N 2O, the process pressure is 80 Pa, the radio frequency power is 50 W, and the growth time is 6 min 9 s.

[0064] Preparing the Au mirror layer: Using an electron beam evaporation coating system, deposit 10 nm of Ti and 100 nm of Au on the surface of the InP substrate with the spacer layer and on the surface of the new substrate GaAs respectively. 2 Spacer layer of InP substrate surface and the new substrate GaAs surface evaporation of 10nm of Ti and 100nm of Au.

[0065] Structure compound: Adopt the flip-chip bonding technology to firmly bond one side of the Au mirror layer of the InP substrate with one side of the Au mirror layer of the GaAs substrate; Place the GaAs substrate with the Au side facing up horizontally on the operating table, place the InP substrate with the Au side facing down horizontally on the GaAs substrate, heat the operating table to 200 °C, and apply a pressure of 5 kN.

[0066] Wet etching: Remove the InP substrate layer by wet etching with HCl, and then immediately use H 3 PO 4 :H 2 O 2 :H 2 O = 2:3:30 mixed solution for wet etching to remove the InGaAs sacrificial layer, leaving the InAs / InP quantum dot layer.

[0067] Preparing the first mask layer: Use a plasma chemical vapor deposition system to deposit 150 nm of SiO 2 on the surface of the InAs / InP quantum dot layer as the first mask layer of the ring-shaped Bragg grating.

[0068] Preparing the second mask layer: Spin-coat an electron beam resist, ZEP520A, on the surface of the first mask layer. The spin-coating parameters are 300 rpm for 6 sec, then accelerate to 3000 rpm and spin for 60 sec. The thickness of the resist is 380 nm, the temperature is 180 °C, and bake for 180 sec to form the second mask layer; Expose the sample cooled to room temperature after baking. The exposure parameters are set as follows: writing field size 200×200 μm, acceleration voltage 125 kV, beam current 300 pA, step size 2 nm, aperture size 120 μm, exposure dose 360 μC / cm 2 .

[0069] Develop and fix the exposed sample. The developer is ZED-N50, the developing time is 60 sec, the fixer is IPA, the fixing time is 20 sec, and then dry the sample with a nitrogen gun.

[0070] Dry etching: The sample to be etched is adhered to a single-crystal silicon Wafer with thermally conductive silicone oil and placed in a pre-vacuum chamber. After the vacuum reaches the preset value, it is transferred to the etching chamber. Etching parameters: The sample stage temperature is set at 10°C, the pressure of He gas purging on the back of the sample is 10 Torr, the process pressure is 1 mTorr, the upper electrode power is 1000 W, the lower electrode power is 35 W, and the etching gas is a mixed gas of trifluoromethane and argon, and the gas component flow rate is CHF 3 / Ar = 20 sccm / 10 sccm, and the process time is 2 min.

[0071] Removing residual glue: The sample after dry etching is soaked in the glue remover N,N-dimethylacetamide of ZEP520A for 5 min to dissolve the large-area residual glue, and then a plasma glue remover is used to remove the small-area residual glue. The O 2 flow rate is 50 sccm, the RF power is 100 W, and the processing time is 5 min.

[0072] Dry etching: An inductively coupled plasma etching machine is used to transfer the pattern of the first mask layer to the InAs / InP quantum dot layer. The etching parameters are: the sample stage temperature is set at 25°C, the pressure of He gas purging on the back of the sample is 10 Torr, the process pressure is 4 mTorr, the upper electrode power is 1000 W, the lower electrode power is 150 W, and the etching gas is a mixed gas of methane, chlorine, and argon, and the gas component flow rate is CH 4 / Cl 2 / Ar = 12 sccm / 6 sccm / 3 sccm, and the process time is 1 min.

[0073] Example 2

[0074] The preparation steps are basically the same as those in Example 1, except that: a voltage of 30 kV is used, and the thickness of the SiO 2 mask layer is 200 nm.

[0075] Comparative Example 1

[0076] The preparation steps are basically the same as those in Example 1, except that: the new substrate material is a quartz glass substrate.

[0077] Comparative Example 2

[0078] The preparation steps are basically the same as those in Example 1, except that: the new substrate material is a Si substrate.

[0079] Comparative Example 3

[0080] The preparation steps are basically the same as those in Example 1, except that: an ultraviolet-curing optical adhesive NOA61 is used to bond the InP substrate and the new substrate instead of flip-chip bonding. NOA61 is spin-coated evenly on the Au mirror surface of the InP substrate, and a quartz glass is used to replace the GaAs substrate (quartz glass is selected here because NOA61 is most suitable for optical bonding of glass and metal surfaces, and the bonding effect is better). It is placed horizontally on the Au surface coated with the adhesive, and the bonded wafer is placed in a drawer-type ultraviolet-curing box for curing.

[0081] After the bonding of the InP substrate and the quartz glass is completed, wet etching is used to remove the InP substrate, and the preparation steps are the same as those in Example 1.

[0082] A SiO 2 hard mask layer is deposited on the surface of the 310 nm InAs / InP thin film sample left after removing the substrate, and the preparation steps are the same as those in Example 1. Since the temperature tolerance of NOA61 is 190 °C and the deposition temperature of SiO 2 is 300 °C, a large number of cracks, wrinkles and bubbles appear on the surface of the thin film sample after depositing SiO 2 , and the flatness of the sample surface does not meet the flatness requirements of the subsequent exposure process, as Figure 6 shown.

[0083] Comparative Example 4

[0084] The preparation steps are basically the same as those in Example 1, except that: traditional wet etching is used. The sample after flip-chip bonding is placed in a beaker filled with concentrated HCl. After standing for etching for 30 min, it is found that the thickness reduction of the sample is not obvious. The sample is taken out, soaked in isopropyl alcohol and deionized water for 5 min respectively, cleaned, and then blown dry with a nitrogen gun. The surface of the sample is characterized by a scanning electron microscope, as Figure 4 shown. Figure 4 (a) shows that at a magnification of 300X, the by-products generated during the long-term etching process on the sample surface are not dissolved in time and deposited on the sample surface, blocking the etching process, resulting in different etching depths at different positions of the substrate and an uneven sample surface. Figure 4 (b) shows that at a magnification of 6kX, the attachment of by-products results in very poor cleanliness of the sample surface.

[0085] Comparative Example 5

[0086] The preparation steps are basically the same as those in Example 1, except that: the first mask layer is not prepared.

[0087] According to Comparative Example 1 and Comparative Example 2, as Figure 3As shown, the present application selects GaAs material as the new substrate of InP. The thermal expansion coefficient of GaAs as the new substrate is close to that of InP, which is suitable as the flip-chip substrate material of InP. In addition, the hardness of GaAs is higher than that of InP, which is suitable as the support material of the thin film with a thickness of hundreds of nanometers remaining after the InP substrate is removed. For comparison, Si substrate ( Figure 3 (a)) and quartz glass substrate ( Figure 3 (b) In the process of wet etching to remove the substrate of InP substrate, when the remaining thickness of the substrate is in the micron level, the flip-chip bonding effect between InP and the substrate material is not ideal. The InP film is separated from the Si substrate and the quartz glass substrate, but it is always firmly bonded to the GaAs substrate.

[0088] As shown in Comparative Example 3, the present application selects the flip-chip technology. The surface-to-surface bonding between metals has extremely good stability and is insensitive to acid-base corrosion, high-temperature baking, and organic solvent cleaning in subsequent processes. It effectively solves the problem of weak bonding and substrate falling off from the substrate when using curing glue for surface-to-surface bonding in subsequent process operations. For example, air bubbles appear during high-temperature baking, curing glue melts during organic solvent cleaning, and curing glue reacts and deforms during acid-base corrosion. These situations will cause the substrate and the substrate to separate, and the hundreds of nanometers thick film left after the substrate is removed from the substrate will be uneven and deformed, or even fall off the surface of the substrate. Figure 7 As shown in Figure 1, Figure (a) shows a sample prepared by flip-chip bonding technology. After acid-base corrosion, high-temperature baking, and organic solvent cleaning, it still has a flat and stable bond with the substrate material; Figure (b) shows a sample prepared by curing adhesive bonding. After high-temperature deposition of SiO 2 Sometimes wrinkles, cracks or even partial detachment occur, making it impossible to carry out the next experiment.

[0089] According to Comparative Example 4, Figure 4 As shown, HCl is selected as the etching solution for InP in this application. HCl reacts with InP to generate a soluble product InCl 3 and gaseous pH 3 , causing the material to gradually dissolve. Traditional wet etching is usually applicable to nanometer-level depths. For InP materials with a thickness of 350μm, byproducts will not be dissolved in time and deposited on the sample surface during the long-term etching process, blocking the progress of corrosion, resulting in different corrosion depths at different locations on the substrate, uneven sample surfaces, and poor experimental repeatability. In order to solve this problem, the etching liquid beaker is placed on a magnetic stirrer to keep the etching liquid in a flowing state during the entire etching process, preventing attachments from depositing on the sample surface and ensuring smooth corrosion. Select H 3 PO 4 :H 2 O 2 :H 2The O mixed solution corrodes the InGaAs sacrificial layer, and this etching solution hardly corrodes the InP material, which can ensure that the InGaAs sacrificial layer is completely corroded without damaging the remaining InAs / InP film.

[0090] According to Comparative Example 5, in the preparation method of the present application, a SiO hard mask is added on the basis of the electron beam resist because the thickness of the InAs / InP quantum dot layer is relatively thick. The etching ratio of the commonly used electron beam resist to InP in the laboratory is about 3:1 to 2:1, and the maximum etching depth of InP is about 200 nm, which cannot meet the etching depth greater than 200 nm. 2

[0091] According to Example 1 and Example 2, selecting a high voltage of 125 kV during electron beam exposure in the present application can reduce the forward scattering of electrons in the resist during exposure, reduce the proximity effect, so that the pattern size obtained after development is closer to the designed pattern line width. As shown, Figures (a) and (b) are annular Bragg gratings obtained by exposure at 30 kV. Due to forward scattering and proximity effect, adjacent gratings are adhered or discontinuous. Figure (c) is an annular Bragg grating obtained by exposure and etching at 30 kV after adding a layer of conductive glue. Although the pattern is prepared, the pattern size is widened by 60 nm compared with the designed size. Figure (d) is an annular Bragg grating obtained by exposure and etching at 125 kV. It can be seen that at 125 kV high voltage, the pattern morphology is excellent and the edge perpendicularity is good. Figure 8

[0092] The InAs / InP annular Bragg grating quantum dot single photon source device prepared by the preparation method of the present application is characterized by optical microscopy and scanning electron microscopy images, as shown. It can be seen that the surface of the nanoscale thickness film of the present application is smooth and flat, and the morphology of the 100-nm annular Bragg grating spacer structure is excellent. The quantum dot single photon source of the present application combines the advantages of InP materials, substrate removal technology and gold mirror reflection layer, and has important application value in photonics and optoelectronic devices. This device can reduce optical loss, improve the Q value of the cavity, improve the thermal management performance, reduce the heat accumulation in the microcavity, improve the temperature stability of the device, and can realize a low-threshold and high-efficiency laser. At the same time, this structure can be integrated with other photonic devices (such as modulators, detectors, etc.) to realize multifunctional photonic integrated circuits. Figure 5

[0093] The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.​​​

Claims

1. A method for preparing an InAs / InP quantum dot single photon source device, characterized in that: include: An InP substrate is prepared, wherein the InP substrate comprises, from top to bottom, an InAs / InP quantum dot layer, an InGaAs sacrificial layer, and an InP substrate layer; Depositing a SiO2 spacer layer on the surface of the InAs / InP quantum dot layer of the InP substrate; Vapor depositing an Au mirror layer on the surface of the SiO2 spacer layer; An Au mirror layer is evaporated on the surface of the GaAs substrate; The Au mirror layer of the InP substrate is combined with the Au mirror layer of the GaAs substrate by using a flip-chip bonding technique; Removing the InP substrate layer and the InGaAs sacrificial layer by wet etching; Depositing a first mask layer of annular Bragg grating on the surface of the InAs / InP quantum dot layer; Preparing a second mask layer on the surface of the first mask layer, and performing exposure and development; performing dry etching on the first mask layer; The InAs / InP quantum dot layer is dry-etched to obtain the InAs / InP quantum dot single-photon source device.

2. The method for preparing the InAs / InP quantum dot single photon source device according to claim 1, characterized in that: The first mask layer is a SiO2 mask layer.

3. The method for preparing the InAs / InP quantum dot single photon source device according to claim 1, characterized in that: The InGaAs sacrificial layer is In 0.53 Ga 0.47 As sacrificial layer; The InAs / InP quantum dot layer is an InP layer containing InAs quantum dots.

4. The method for preparing the InAs / InP quantum dot single photon source device according to any one of claims 1 to 3, characterized in that: Removing the InP substrate layer and the InGaAs sacrificial layer by wet etching includes: removing the InP substrate layer by wet etching with HCl, and then removing the InGaAs sacrificial layer by wet etching with a mixed solution of H3PO4:H2O2:H2O.

5. The method for preparing the InAs / InP quantum dot single photon source device according to claim 4, characterized in that: The volume ratio of H3PO4:H2O2:H2O is 2:3:

30.

6. The method for preparing the InAs / InP quantum dot single photon source device according to claim 5, characterized in that: The exposure voltage is 30 kV-125 kV.

7. The method for preparing the InAs / InP quantum dot single photon source device according to any one of claims 1 to 3, characterized in that: The thickness of the InAs / InP quantum dot layer is 310 nm, the thickness of the InGaAs sacrificial layer is 200 nm, and the thickness of the InP substrate layer is 350 μm.

8. The method for preparing the InAs / InP quantum dot single photon source device according to claim 2, characterized in that: The thickness of the SiO2 mask layer is 100 nm-200 nm.

9. An InAs / InP quantum dot single-photon source device prepared by the method for preparing an InAs / InP quantum dot single-photon source device according to any one of claims 1 to 8.

10. The InAs / InP quantum dot single photon source device according to claim 9, characterized in that: It has a ring Bragg grating microcavity structure.

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