Overvoltage protection circuit, power conversion device and control method

Abstract

The invention relates to the technical field of power electronics, and discloses an overvoltage protection circuit, a power conversion device and a control method.The overvoltage protection circuit controls driving of an upper bridge circuit and a lower bridge circuit by adding an active short-circuit maintenance circuit in cooperation with an overvoltage signal and a reset signal of software. And the lower bridge circuit is always kept in an active short-circuit state and cannot exit due to the influence of other factors, so that circuit devices are protected from being damaged.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to an overvoltage protection circuit, a power conversion device and a control method. Background Art

[0002] With the development of new energy vehicles, fault identification and protection of drive circuits are becoming increasingly important, especially overvoltage faults. At present, circuit protection during overvoltage is mainly achieved through the working status of the upper and lower bridges in the inverter circuit. After an overvoltage fault occurs, the controller will control the IGBT to enter the upper bridge wave blocking and lower bridge ASC state (Active Short Circuit). When the lower bridge enters the ASC state, a large reverse braking torque will be generated, which will reduce the speed of the motor and stop the car slowly. At the same time, the motor of the lower bridge will become a resistive load in the ASC state, consuming the energy of the overvoltage, thereby reducing the voltage on the bus and achieving the purpose of protecting the circuit components. Therefore, the ASC state of the lower bridge needs to exist until the overvoltage fault disappears, and it cannot be exited halfway, otherwise reverse electromotive force will still be generated, causing overvoltage damage to the circuit components.

[0003] In order to ensure that the lower bridge remains in the ASC state before the overvoltage fault message is received, the software is used to output an enable signal to control it all the time. However, the software itself may experience a runaway reset. During the runaway reset, it cannot ensure that the enable signal is always maintained, causing the ASC state to exit, thereby damaging circuit components. Summary of the invention

[0004] The present application provides an overvoltage protection circuit, a power conversion device and a control method to solve the problem that the ASC state cannot be maintained due to software runaway reset during an overvoltage fault.

[0005] The first aspect of the present application provides an overvoltage protection circuit comprising: a controller, which generates and outputs an active short-circuit maintenance signal; a logic chip circuit, whose input end is connected to the output end of the controller, and the logic chip circuit controls the output of the lower bridge drive signal based on the active short-circuit maintenance signal; an active short-circuit maintenance circuit, whose input end is respectively connected to the output end of the controller and the output end of the logic chip circuit, and the active short-circuit maintenance circuit controls the lower bridge drive signal to drive the lower bridge circuit and maintain it in an active short-circuit state.

[0006] In a feasible implementation, the logic chip circuit includes: a switching circuit and a logic chip; the input end of the switching circuit is connected to the output end of the controller, and the output end of the switching circuit is connected to the input end of the logic chip; under the action of the active short-circuit maintenance signal, the switching circuit controls the logic chip to be turned on, and outputs the bridge drive signal received at the input end of the logic chip from the output end of the logic chip to the active short-circuit maintenance circuit.

[0007] In a feasible implementation, the switching circuit includes at least a first switching tube, a current limiting resistor and a bias circuit; the gate of the first switching tube is connected to the output end of the controller through the current limiting resistor for receiving the active short-circuit maintenance signal; the drain of the first switching tube is connected to the control end of the logic chip for outputting a switching signal to control the conduction of the logic chip; the source of the first switching tube is connected to the gate of the first switching tube through the bias circuit.

[0008] In a feasible implementation manner, the active short-circuit maintaining circuit includes: a state maintaining circuit, whose input end is connected to the output end of the controller, for receiving an overvoltage signal and a software reset signal, and generating an active short-circuit drive signal for the lower bridge circuit based on the overvoltage signal and the software reset signal; a lower bridge logic circuit, whose input end is respectively connected to the output end of the state maintaining circuit and the lower bridge output end in the logic chip circuit, for driving the lower bridge circuit based on the active short-circuit drive signal and the lower bridge drive signal and maintaining it in an active short-circuit state.

[0009] In a feasible implementation, the state maintenance circuit includes: a logic gate circuit connected to the output end of the controller, used to perform a logic operation on the received overvoltage signal and the reset signal of the software, and output a first operation result and a second operation result; an inverter provided between the output end of the logic gate circuit and the input end of the lower bridge logic circuit, used to invert the first operation result to obtain an active short-circuit drive signal, and invert the second operation result to obtain a conduction signal of the logic chip circuit.

[0010] In a feasible implementation, the logic gate circuit includes a first OR gate and a first AND gate, and the input end of the first OR gate and the input end of the first AND gate are both connected to the output end of the controller; the first OR gate is used to perform an OR operation on the overvoltage signal and the reset signal of the software to obtain a first operation result; the first AND gate is used to perform an AND operation on the reset signal of the software and the hardware drive signal to obtain a second operation result.

[0011] In a feasible implementation, the active short-circuit maintaining circuit also includes: an upper bridge logic circuit, whose input end is connected to the upper bridge output end in the logic chip circuit, for performing logic operations on the upper bridge drive signal output by the logic chip circuit, and controlling the upper bridge circuit to enter the wave cover based on the result of the operation.

[0012] In a feasible implementation, the lower bridge logic circuit includes at least one second OR gate; the first output end of the at least one second OR gate is connected to the output end of the state maintenance circuit, and the first output end of the at least one second OR gate is connected to the lower bridge output end in the logic chip circuit.

[0013] In a feasible implementation manner, the lower bridge logic circuit includes a second switch tube and at least one third switch tube; the gate of the second switch tube is connected to the output end of the state maintaining circuit for receiving an active short-circuit drive signal; the drain of the second switch tube is connected to the gate of the at least one third switch tube, and the drain of the at least one third switch tube is connected to the lower bridge output end of the logic chip circuit through a resistor; the source of the second switch tube is connected to the gate of the second switch tube through a resistor and a capacitor.

[0014] In a feasible implementation, the lower bridge logic circuit includes a coil and at least one magnetic switch; the coil is connected in parallel between the output end of the state maintenance circuit and the ground, and is used to generate a magnetic force based on the active short-circuit drive signal; the at least one magnetic switch is connected to the lower bridge output end of the logic chip circuit, and is used to output the lower bridge drive signal to the lower bridge circuit under the control of the magnetic force.

[0015] In a feasible implementation, the lower bridge logic circuit also includes a fourth switch tube; the coil is connected in series to the drain of the fourth switch tube, the gate of the fourth switch tube is connected to the output end of the state maintenance circuit, and the source of the fourth switch tube is connected to the gate of the fourth switch tube through a resistor and a capacitor.

[0016] In a feasible implementation manner, the overvoltage protection circuit further includes: an independent power supply, configured to provide a voltage signal for the active short circuit maintaining circuit.

[0017] A second aspect of the present application provides a power conversion device, characterized in that the power conversion device includes a drive signal generating circuit, at least one of the above-provided overvoltage protection circuits and a bridge circuit connected in series, wherein the bridge circuit includes at least one switching device.

[0018] The third aspect of the present application provides a control method applied to the power conversion device provided above, and the control method includes: when it is determined that the bus voltage is overvoltage, generating and outputting an active maintenance signal; based on the active short-circuit maintenance signal, controlling the lower bridge drive signal generated by the drive signal generation circuit to be output to the lower bridge circuit in the bridge circuit; after the lower bridge drive signal is output to the lower bridge circuit, the active short-circuit maintenance circuit controls the lower bridge drive signal to drive the lower bridge circuit and maintain it in an active short-circuit state.

[0019] In the technical solution provided by the present application, the overvoltage protection circuit includes a logic chip circuit, an active short-circuit maintenance circuit and a controller; the controller generates and outputs an active short-circuit maintenance signal; the input end of the logic chip circuit is connected to the output end of the controller, and is used to control the output of the upper bridge drive signal and the lower bridge drive signal based on the active short-circuit maintenance signal; the input end of the active short-circuit maintenance circuit is respectively connected to the output end of the controller and the output end of the logic chip circuit, and is used to control the lower bridge drive signal to drive the lower bridge circuit and maintain it in an active short-circuit state. By adding an active short-circuit maintenance circuit and coordinating the active short-circuit maintenance signal to control the drive of the lower bridge circuit, such a circuit setting realizes that when overvoltage occurs, the lower bridge circuit is always kept in an active short-circuit state, and will not be exited due to other factors, so as to protect the circuit components from damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a schematic diagram of the first structure of the overvoltage protection circuit in the embodiment of the present application;

[0021] Figure 2 A circuit schematic diagram of a logic chip circuit in an embodiment of the present application;

[0022] Figure 3 This is a second structural schematic diagram of the overvoltage protection circuit in the embodiment of the present application;

[0023] Figure 4 A circuit schematic diagram of a state maintenance circuit in an embodiment of the present application;

[0024] Figure 5 This is a first circuit schematic diagram of the lower bridge logic circuit in the embodiment of the present application;

[0025] Figure 6 This is a second circuit schematic diagram of the lower bridge logic circuit in the embodiment of the present application;

[0026] Figure 7 This is a third circuit schematic diagram of the lower bridge logic circuit in the embodiment of the present application;

[0027] Figure 8 This is a fourth circuit schematic diagram of the lower bridge logic circuit in the embodiment of the present application;

[0028] Fig. 9 This is a third structural schematic diagram of the overvoltage protection circuit in the embodiment of the present application;

[0029] Fig.10 This is a circuit diagram of the independent power supply in the embodiment of the present application;

[0030] Fig.11 This is a schematic diagram of the structure of a power conversion device in an embodiment of the present application;

[0031] Fig.12 Schematic diagram of a flow chart of a control method for a power conversion device in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The present application provides an overvoltage protection circuit, a power conversion device and a control method. On the basis of the existing active short-circuit control scheme, an active short-circuit maintaining circuit is added. When an overvoltage fault and a software runaway reset are determined, the lower bridge circuit can be kept in the ASC state to avoid the lower bridge circuit exiting the ASC state and generating a reverse electromotive force, thereby causing overvoltage damage to the power tube and the membrane capacitor.

[0033] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] like Figure 1 As shown, an embodiment of the present application provides an overvoltage protection circuit, specifically comprising:

[0035] A logic chip circuit 110, an active short-circuit maintaining circuit 120 and a controller 130, wherein the controller 130 is connected to the converter and detects working parameters in the converter, such as whether it is overvoltage, whether it is necessary to maintain a braking short-circuit state and whether the software is reset; the logic chip circuit 110 is used to output a driving signal (PWM signal wave) of the bridge circuit to control the on and off of each switching device (IGBT) in the bridge circuit; the active short-circuit maintaining circuit 120 is used to control the output of the driving signal (PWM signal wave) based on the detection result of the controller 130 being overvoltage, so as to maintain the lower bridge circuit in the bridge circuit in an active short-circuit state.

[0036] It should be noted that the logic chip circuit 110 is a bus transceiver logic integrated circuit, which is mainly connected to the PWM signal wave generating circuit and the control end of the bridge circuit, and is used to control the PWM signal wave output to the control end of the bridge circuit. Specifically, it is based on the software wave enable signal in the converter to drive it to output the PWM signal wave to the control end of the bridge circuit.

[0037] In this embodiment, the controller 130 is used to detect the operating parameters of the converter and generate an active short-circuit maintenance signal based on the operating parameters, wherein the operating parameters include an overvoltage signal and a software reset signal; the active short-circuit maintenance signal is output to the input end of the logic chip circuit 110.

[0038] The input end of the logic chip circuit 110 is connected to the output end of the controller 130, and is used to control the output of the upper bridge drive signal and the lower bridge drive signal based on the active short-circuit maintenance signal; specifically, the logic chip circuit 110 generates a low level based on the active short-circuit maintenance signal to control the logic chip circuit 110 itself to be turned on, thereby outputting the PWM signal wave to the control end of the bridge circuit, that is, the upper bridge drive signal is output to the control end of the upper bridge circuit and the lower bridge drive signal is output to the control end of the lower bridge circuit.

[0039] The input end of the active short circuit maintaining circuit 110 is respectively connected to the output end of the controller 130 and the output end of the logic chip circuit 110, and is used to control the upper bridge driving signal to drive the upper bridge circuit and control the lower bridge driving signal to drive the lower bridge circuit based on the working parameters.

[0040] It should be noted that, the controlling the upper bridge driving signal to drive the upper bridge circuit and the controlling the lower bridge driving signal to drive the lower bridge circuit based on the working parameters respectively includes:

[0041] If the overvoltage signal in the working parameters is at a low level (i.e., an overvoltage fault) and / or the software reset signal is at a low level (i.e., a software runaway reset), the active short-circuit maintaining circuit 120 outputs a high-level active short-circuit drive signal, and controls the lower bridge drive signal output to control the lower bridge circuit to be turned on, so as to enter the ASC state.

[0042] If the overvoltage signal in the working parameter is at a high level (ie, not an overvoltage fault), the active short circuit maintaining circuit 120 outputs a low level active short circuit driving signal and controls the output of the lower bridge driving signal to control the lower bridge circuit to enter the wave blocking state.

[0043] In this embodiment, the logic chip circuit 110 includes: a switch circuit 111 and a logic chip 112; the switch circuit 111 controls the on and off of the logic chip 112, and the logic chip 112 controls the transmission direction of the driving signal of the bridge circuit, that is, transmits the PWM signal wave in the direction of the bridge circuit.

[0044] The input end of the switch circuit 111 is connected to the output end of the controller 130, and the output end of the switch circuit 111 is connected to the input end of the logic chip 112;

[0045] Under the action of the active short circuit maintaining signal, the switch circuit 111 controls the logic chip 112 to be turned on, and outputs the bridge driving signal received at the input end of the logic chip 112 to the active short circuit maintaining circuit 120 from the output end of the logic chip 112 .

[0046] It should be noted that the switch circuit 111 controls whether the logic circuit 112 is turned on based on the overvoltage signal and the software reset signal. That is, when the overvoltage signal is at a low level and the software reset signal is at a high level, the controller 130 outputs an active short-circuit maintenance signal to the switch circuit 111. When the switch circuit 111 receives the active short-circuit maintenance signal, the logic chip 112 is turned on, thereby realizing that the PWM signal wave at the input end of the logic chip 112 is output from the output end to the control end of the bridge circuit.

[0047] It should be noted that when the PWM signal wave is output from the output end of the logic chip 112 to the control end of the bridge circuit, it is controlled based on the active short-circuit maintenance signal. When the active short-circuit maintenance signal is at a high level, the input and output ends of the logic chip 112 are turned on, and the PWM signal wave is output to the control end of the bridge circuit. Among them, the specific level of the part of the drive signal belonging to the lower bridge circuit in the PWM signal wave is also controlled based on the calculation result of the overvoltage signal and the reset signal of the software. When both are at a low level at the same time, the part of the drive signal belonging to the lower bridge circuit in the PWM signal wave is at a high level, and the lower bridge circuit is in the ASC state; when only one of the two is at a low level, the part of the drive signal belonging to the lower bridge circuit in the PWM signal wave is the same as the original signal.

[0048] It is understandable that the switch circuit 111 is specifically formed by a switch tube design, such as an NMOS tube, a PMOS tube, etc., and the logic chip 112 is formed by a bus transceiver design, wherein the control end in the logic chip 112 is connected to the output end of the switch circuit 111.

[0049] The switch circuit 111 at least includes a first switch tube, a current limiting resistor and a bias circuit, wherein the first switch tube can be an NMOS tube; the gate of the first switch tube is connected to the output end of the controller 130 through the current limiting resistor, for receiving the active short-circuit maintenance signal; the drain of the first switch tube is connected to the control end of the logic chip 112, for outputting a switch signal to control the conduction of the logic chip 112; the source of the first switch tube is connected to the gate of the first switch tube through the bias circuit, and the current limiting resistor is used to limit the driving voltage of the gate of the first switch tube; the bias circuit provides a bias voltage for the first switch tube, thereby protecting the first switch tube, and is specifically composed of a capacitor and a resistor connected in parallel.

[0050] like Figure 2 As shown, the switch circuit 111 includes an NMOS tube Q1, resistors R3, R4 and R5, and a capacitor C1. The gate of the NMOS tube Q1 is connected to the output end of the controller 130 through the resistor R4, and the active short-circuit maintenance signal is input. A resistor R5 and a capacitor C1 are provided between the gate and the source of the NMOS tube Q1. The resistor R5 and the capacitor C1 are connected in parallel. The drain of the NMOS tube Q1 is connected to the control end of the logic chip 112 and the output end of the active short-circuit maintenance circuit, and the drain of the NMOS tube Q1 is also connected to the power supply end in the logic chip 112 through the resistor R3. When the active short-circuit maintenance signal of the NMOS tube Q1 is at a high level, the drain outputs a low level, so that the input and output ends in the logic chip 112 are turned on to realize the transmission of the driving signal of the bridge circuit.

[0051] The logic chip 112 includes a chip U6 and a plurality of pull-down circuits and auxiliary circuits connected to the chip U6, wherein the input end of U6 is connected to the PWM signal wave generating circuit, the output end is connected to the control end of the bridge circuit, and the plurality of pull-down circuits are respectively arranged on each output end of U6. The logic chip 112 here is described by taking the upper bridge and the lower bridge as three-phase as an example.

[0052] like Figure 3As shown, the active short-circuit maintaining circuit 120 includes: a state maintaining circuit 121 and a lower bridge logic circuit 122; wherein the input end of the state maintaining circuit 121 is connected to the output end of the controller 130, for receiving an overvoltage signal and a software reset signal, and generating an active short-circuit drive signal for the lower bridge circuit based on the overvoltage signal and the software reset signal; the input end of the lower bridge logic circuit 122 is respectively connected to the output end of the state maintaining circuit 121 and the lower bridge output end in the logic chip circuit 110, for driving the lower bridge circuit based on the active short-circuit drive signal and the lower bridge drive signal and maintaining it in an active short-circuit state.

[0053] It is understandable that the state maintaining circuit 121 outputs the turn-on signal and the active short-circuit driving signal of the logic chip 112 respectively according to the overvoltage signal, the software reset signal and the active short-circuit maintaining signal detected by the controller 130. Specifically, the active short-circuit driving signal is output based on the overvoltage signal and the software reset signal, and the turn-on signal is output based on the software reset signal and the active short-circuit maintaining signal.

[0054] In this embodiment, the state maintaining circuit 121 includes: a logic gate circuit and an inverter, and the two input ends of the logic gate circuit are connected to the output end of the controller, and are used to perform logical operations on the received overvoltage signal Q1_OV and the reset signal of the software, and output a first operation result and a second operation result; the second operation result is specifically obtained based on the software reset signal ENSW and the active short-circuit maintenance signal GD_ENA1.

[0055] It can be understood that the logic gate circuit includes a first OR gate and a first AND gate, and the input end of the first OR gate and the input end of the first AND gate are both connected to the output end of the controller 130; the first OR gate is used to perform an OR operation on the overvoltage signal and the reset signal of the software to obtain a first operation result; the first AND gate is used to perform an AND operation on the reset signal of the software and the hardware drive signal to obtain a second operation result.

[0056] The inverter is provided between the output end of the logic gate circuit and the input end of the lower bridge logic circuit, and is used to invert the first operation result to obtain the active short-circuit drive signal P1_DRV_HW_SHUTL, and invert the second operation result to obtain the conduction signal P1_OE of the logic chip circuit 110.

[0057] like Figure 4As shown, the logic gate circuit mainly includes an OR gate U10D and an AND gate U7A, the inverter is the automotive-grade inverter U11 in the figure, the two input ends of the OR gate U10D are respectively connected to the overvoltage signal Q1_OV output by the controller 130 and the reset signal ENSW of the software, the output end of the OR gate U10D is connected to the 1 pin of the inverter U11, the two input ends of the AND gate U7A are respectively connected to the active short-circuit maintenance signal GD_ENA1 output by the controller 130 and the reset signal ENSW of the software, the output end of the AND gate U7A is connected to the 3 pin of the inverter U11, the 6 pin of the inverter U11 outputs the active short-circuit drive signal P1_DRV_HW_SHUTL, and the 4 pin of the inverter U11 outputs the turn-on signal P1_OE of the logic chip 112.

[0058] In actual applications, when the software is not running wild (ENSW is high) and no overvoltage occurs (Q1_OV is also high), the output of pin 11 of U10D is high, the output of pin 6 of U11 is low, and P1_DRV_HW_SHUTL is low.

[0059] When the software runs away, ENSW is low level. Assuming that due to factors such as low speed, the reverse electromotive force is small and no overvoltage is triggered, Q1_OV is high level. U7 is an AND gate. When ENSW is low level, the output of U7's 3rd pin is low level. U11 is a NOT gate, so the output of U11's 4th pin P1_OE is high level.

[0060] When the software runs out of control, due to factors such as high speed, the reverse electromotive force is large, triggering overvoltage, then Q1_OV and ENSW are both low level, and pin 11 of U10D outputs low level. U11 is a NOT gate, so pin 6 of U11 outputs high level. After the RC delay circuit composed of R24 and C8, the output P1_DRV_HW_SHUTL is high level.

[0061] In this embodiment, the active short-circuit maintaining circuit 120 also includes: an upper bridge logic circuit 123, whose input end is connected to the upper bridge output end of the logic chip circuit 110, and is used to perform logic operations on the upper bridge drive signal output by the logic chip circuit 110, and control the upper bridge circuit to enter the wave cover based on the result of the operation.

[0062] The lower bridge logic circuit 122 includes at least one second OR gate; the first output end of the at least one second OR gate is connected to the output end of the state maintenance circuit 121, and the first output end of the at least one second OR gate is connected to the lower bridge output end in the logic chip circuit 110.

[0063] It is understandable that the lower bridge logic circuit 122 and the upper bridge logic circuit 123 are both implemented using OR gates, such as Figure 5As shown, the number of OR gates in the lower bridge logic circuit 122 and the upper bridge logic circuit 123 is determined according to the number of phases of the bridge circuit. Here, taking three phases as an example, the lower bridge logic circuit 122 includes OR gates U10A, U10B, and U10C, and the upper bridge logic circuit 123 includes OR gates U8A, U8B, and U8C; one input end of the OR gates U10A, U10B, and U10C is connected to the active short-circuit drive signal P1_DRV_HW_SHUTL, and the other input end is respectively connected to the lower bridge output end in the logic chip 112. When the active short-circuit drive signal P1_DRV_HW_SHUTL is at a high level, the output lower bridge drive signal of the upper bridge logic circuit 123 is all at a high level, so as to realize that the lower bridge circuit enters the ASC state. One input end of the OR gates U8A, U8B, and U8C is connected to the ground, and the other input end is respectively connected to the upper bridge output end in the logic chip 112.

[0064] In this embodiment, the lower bridge logic circuit 122 can also be designed and formed using NMOS tubes and PMOS tubes, specifically including a second switch tube (using an NMOS tube) and at least one third switch tube (using a PMOS tube); the gate of the second switch tube is connected to the output end of the state maintenance circuit 121 for receiving an active short-circuit drive signal; the drain of the second switch tube is connected to the gate of the at least one third switch tube, and the drain of the at least one third switch tube is connected to the lower bridge output end of the logic chip circuit 110 through a resistor; the source of the second switch tube is connected to the gate of the second switch tube through a resistor and a capacitor.

[0065] like Figure 6 As shown, the lower bridge logic circuit 122 is composed of an NMOS transistor Q4, a PMOS transistor Q1, a PMOS transistor Q2, a PMOS transistor Q3 and a plurality of resistors and capacitors, wherein the gate of the NMOS transistor Q4 is connected to the active short circuit maintenance signal P1_DRV_HW_SHUTL, a resistor R3 and a capacitor C1 are arranged between the gate and the source of the NMOS transistor Q4, the resistor R3 and the capacitor C1 are connected in parallel, the drain of the NMOS transistor Q4 is respectively connected to the gates of the PMOS transistor Q1, the PMOS transistor Q2, and the PMOS transistor Q3, and the drain of the NMOS transistor Q4 is also connected to the power supply through the resistor R1; the drains of the PMOS transistors Q1, the PMOS transistors Q2, and the PMOS transistors Q3 are connected to the control end of the lower bridge circuit and to the lower bridge output end of the logic chip 112 through the resistor; the sources of the PMOS transistors Q1, the PMOS transistors Q2, and the PMOS transistors Q3 are connected to the power supply.

[0066] In this embodiment, the lower bridge logic circuit 122 can also be designed and formed using switching devices such as relays, such as a relay, which includes a coil and at least one magnetic switch; the coil is connected in parallel between the output end of the state maintaining circuit 121 and the ground, and is used to generate a magnetic force based on the active short-circuit drive signal; the at least one magnetic switch is connected to the lower bridge output end of the logic chip circuit 110, and is used to output the lower bridge drive signal to the lower bridge circuit under the control of the magnetic force.

[0067] like Figure 7 As shown, after the coil K1A is connected in parallel with the resistor R3 and the capacitor C1, an active short circuit maintenance signal P1_DRV_HW_SHUTL is input; one end of each contact K1B, K2B and K3B is connected to the control end of the lower bridge circuit and to the lower bridge output end of the logic chip 112 through a resistor, and the other end is connected to the power supply.

[0068] In this embodiment, the lower bridge logic circuit 122 further includes a fourth switch tube; the coil is connected in series to the drain of the fourth switch tube, the gate of the fourth switch tube is connected to the output end of the state maintaining circuit 121, and the source of the fourth switch tube is connected to the gate of the fourth switch tube through a resistor and a capacitor. Figure 8 As shown, the fourth switch tube is an NMOS tube, and the coil K1A is arranged on the drain of the fourth switch tube Q1.

[0069] In this embodiment, the overvoltage protection circuit further includes: an independent power supply 140, which is used to provide a voltage signal for the active short circuit maintaining circuit 120. Fig. 9 and 10 As shown, the independent power supply 140 is powered solely by a battery, and is implemented by using LDOU12, multiple capacitors, and a diode design. An independent power supply LDO U12 is designed, and the output voltage Vsafe_5V can be guaranteed to be stable when an abnormality occurs in the normal power supply VQUC, thereby further ensuring stable control of the ASC state during an overvoltage fault.

[0070] In this embodiment, by separately setting up an active short-circuit maintaining circuit 110, as long as an overvoltage fault is detected, it can ensure that the lower bridge circuit is always in the ASC state and does not exit, thereby solving the problem in the prior art that the lower bridge circuit exits the ASC state and generates a reverse electromotive force, the bus voltage will rise rapidly, and the power tube and the membrane capacitor may be damaged by overvoltage.

[0071] like Fig.11As shown, the present application also provides an embodiment of a converter, which includes: a series-connected drive signal generating circuit 1101, an overvoltage protection circuit 1102 provided by at least one of the above embodiments, and a bridge circuit 1103, wherein the bridge circuit 1103 includes at least one switching device, which is a power switch such as an IGBT.

[0072] Since the converter includes all the features of the overvoltage protection circuit, the converter using the overvoltage protection circuit also solves the above-mentioned problems.

[0073] See also Fig.12 , is an implementation of a control method for a power conversion device provided in the present application, the method comprising the following steps:

[0074] 1201. When determining that the bus voltage is overvoltage, generate and output an active maintenance signal;

[0075] In this embodiment, by detecting whether the bus voltage of the power conversion device is overvoltage, overvoltage here refers to whether the DC bus voltage exceeds a preset threshold. If overvoltage, an overvoltage signal, a software reset signal and an active short circuit maintenance signal are generated.

[0076] That is, an active short circuit maintenance signal is generated based on the overvoltage signal of the bus voltage overvoltage and the reset signal of the logic chip circuit; and the active short circuit maintenance signal is output to the switch circuit in the logic chip circuit and the active short circuit maintenance circuit.

[0077] When overvoltage is determined, a low-level overvoltage signal is generated, and at the same time, it is detected whether the output control software for the PWM signal wave in the power conversion device is out of control. If so, a low-level reset signal is output, otherwise, a high-level reset signal is output.

[0078] Furthermore, while determining the overvoltage, a high-level active short-circuit maintenance signal is output through software.

[0079] 1202. Controlling the lower bridge driving signal generated by the driving signal generating circuit based on the active short circuit maintaining signal to output the lower bridge driving signal to the lower bridge circuit in the bridge circuit;

[0080] 1203. After the lower bridge driving signal is output to the lower bridge circuit, the active short circuit maintaining circuit controls the lower bridge driving signal to drive the lower bridge circuit and maintain it in an active short circuit state.

[0081] Specifically, an active short-circuit drive signal of the lower bridge circuit is generated based on the overvoltage signal and the reset signal; the lower bridge circuit is driven based on the active short-circuit drive signal and the lower bridge drive signal, and maintained in an active short-circuit state.

[0082] In this step, the overvoltage protection circuit in the power conversion device generates an active short-circuit drive signal for the lower bridge circuit based on the overvoltage signal and the software reset signal to control the working state of the lower bridge circuit; based on the software reset signal and the active short-circuit maintenance signal, the transmission signal of the upper bridge drive signal and the lower bridge drive signal (i.e., the above-mentioned conduction signal) is generated. The active short-circuit maintenance signal here is a signal obtained when an overvoltage is detected, and is used to maintain the ASC state of the lower bridge circuit. The active short-circuit drive signal is used to force the ASC state of the lower bridge circuit to be maintained when the software runs away.

[0083] In another feasible implementation, when it is determined that the bus voltage is not over-voltage and a reset signal is detected, the active short-circuit maintenance circuit outputs an enable signal of the logic chip circuit based on the reset signal; and controls the logic chip circuit to output a drive signal of the bridge circuit based on the enable signal.

[0084] The following is a detailed description of the above method using a three-phase converter as an example of a power conversion device. Figure 1-10 The circuit structure diagram of the overvoltage protection circuit provided defines the software runaway monitoring signal ENSW, which is the GPIO signal of the controller. After normal power-on, the push-pull output high level is configured by software. When the software runs away, the GPIO port is in a high-impedance state, and ENSW will be pulled down to a low level by the external pull-down resistor R23. After the drive signal generating circuit generates a wave, it is input into the left side of U6 in the overvoltage protection circuit and output from the right side of U6. The right side output includes the upper three bridges P1_PWM_UHS_1, P1_PWM_VHS_1, and P1_PWM_WHS_1, and the lower three bridges P1_PWM_ULS_1, P1_PWM_VLS_1, and P1_PWM_WLS_1. Among them, the lower three bridge signals P1_PWM_ULS_1, P1_PWM_VLS_1, and P1_PWM_WLS_1 will pass through the OR gate chips U10A, U10B, and U10C. The output signals to the bridge circuit are P1_PWM_ULS_2, P1_PWM_VLS_2, and P1_PWM_WLS_2. The upper three bridges P1_PWM_UHS_1, P1_PWM_VHS_1, and P1_PWM_WHS_1 signals are directly output to the bridge circuit.

[0085] Based on the above structure, the converter has three working conditions, as follows:

[0086] Working condition 1: When the software is not out of control (ENSW is high) and no overvoltage occurs (Q1_OV is also high), the output of pin 11 of U10D is high, the output of pin 6 of U11D is low, and P1_DRV_HW_SHUTL is low. Then the outputs P1_PWM_ULS_2, P1_PWM_VLS_2, and P1_PWM_WLS_2 of U10A, U10B, and U10C will change with the outputs P1_PWM_ULS_1, P1_PWM_VLS_1, and P1_PWM_WLS_1 of U6.

[0087] When ENSW is high, the software wave enable signal GD_ENA1 is high, and P1_DRVEN is high, the 3rd pin output of the AND gate chip U7A is high, the 4th pin output P1_OE of U11 is low, and U6 is normally turned on. Then the right side of U6 outputs PWM normally, and P1_PWM_ULS_2, P1_PWM_VLS_2, and P1_PWM_WLS_2 also output PWM normally. Therefore, the upper and lower bridges of the bridge circuit all emit PWM waves normally;

[0088] When GD_ENA1 is low, P1_DRVEN is low, the 3rd pin of the AND gate chip U7A is low, the 4th pin of U11 outputs P1_OE high, and U6 is turned off, then the right side of U6 is in high impedance state. Due to the existence of the pull-down resistor, the right side of U6 outputs low level, then P1_PWM_ULS_2, P1_PWM_VLS_2, and P1_PWM_WLS_2 also output low level, so the upper and lower bridges of the bridge circuit are all low level. The current design does not change the traditional wave logic, and the software wave enable signal GD_ENA1 can control the PWM wave normally.

[0089] Working condition 2: When the software runs away, ENSW is low level. Assuming that due to factors such as low speed, the reverse electromotive force is small and no overvoltage is triggered, Q1_OV is high level. U7A is an AND gate. When ENSW is low level, the output of U7A's 3rd pin is low level. U11 is an inverter designed as a NOT gate, so the output of U11's 4th pin P1_OE is high level. P1_OE is the enable signal of U6. When P1_OE is high level, U6 will be turned off, and the right output of U6 is high impedance. Due to the existence of the pull-down resistor, the output of U6 is all low level. U10D is an OR gate, ENSW is low, Q1_OV is high, then the output of pin 11 of U10D is high, the output of pin 6 of U11 is low, and P1_DRV_HW_SHUTL is low. Therefore, P1_PWM_ULS_2, P1_PWM_VLS_2, and P1_PWM_WLS_2 will follow the output of U6 P1_PWM_ULS_1, P1_PWM_VLS_1, and P1_PWM_WLS_1 (output low level), so the upper and lower three bridge PWM waves of the bridge circuit are all low.

[0090] Working condition 3: When the software runs away, due to factors such as high speed, the reverse electromotive force is large, triggering overvoltage, then Q1_OV and ENSW are both low level, and pin 11 of U10D outputs low level. U11 is an inverter designed as a NOT gate, so pin 6 of U11 outputs high level. After the RC delay circuit composed of R24 and C8, the output hardware ASC signal P1_DRV_HW_SHUTL is high level. U10A, U10B and U10C are OR gates, so the outputs P1_PWM_ULS_2, P1_PWM_VLS_2, and P1_PWM_WLS_2 of U10A, U10B and U10C are all high levels, so the lower three bridges of the bridge circuit are all high levels, and since U6 is in the off state, the right side outputs of U6 are all high-impedance states. Due to the presence of three 10k pull-down resistors R10, R12, and R14, the right side outputs of U6 P1_PWM_UHS_1, P1_PWM_VHS_1, and P1_PWM_WHS_1 are all low levels, so the upper three bridges of the bridge circuit are all in a low-level sealing state, and the lower three bridges of the bridge circuit are all in a high-level ASC state.

[0091] Furthermore, if the overvoltage disappears at this time (Q1_OV is high level), but the software is still in the runaway state (ENSW is low level), it will enter working condition 2, and the upper and lower three bridges of the bridge circuit are all in the low-level blocking state.

[0092] If the overvoltage does not disappear at this time (Q1_OV is low), but the software restores control (ENSW is high), the 11th pin of U10D outputs high, and the output P1_DRV_HW_SHUTL of U11 is low, then the outputs P1_PWM_ULS_2, P1_PWM_VLS_2, and P1_PWM_WLS_2 of U10A, U10B, and U10C will change with the changes of P1_PWM_ULS_1, P1_PWM_VLS_1, and P1_PWM_WLS_1 output by U6. If ENSW is high, GD_ENA1 is high, and P1_DRVEN is high, then the 3rd pin of the AND gate chip U7A outputs high, and the 4th pin of U11 outputs P1_OE is low, then the 245 chip U6 is turned on, and the right side of U6 outputs normally. When overvoltage occurs, the upper bridge blocks the wave, and the logic of the lower bridge ASC is that the input of U6 is the upper three bridges P1_PWM_UHS, P1_PWM_VHS, P1_PWM_WHS are low level, and the lower three bridges P1_PWM_ULS, P1_PWM_VLS, P1_PWM_WLS are high level. Then the output of U6 upper three bridges (P1_PWM_UHS_1, P1_PWM_VHS_1, P1_PWM_WHS_1) are low level, and the lower three bridges (P1_PWM_ULS_1, P1_PWM_VLS_1, P1_PWM_WLS_1) are high level, so the upper three bridges of the bridge circuit are low level blocking, and the lower three bridges of the bridge circuit are high level ASC state.

[0093] In another embodiment, the input and output of the lower bridge logic circuit in the overvoltage protection circuit are delayed, so the lower three bridge signals P1_PWM_ULS_2, P1_PWM_VLS_2, P1_PWM_WLS_2 of the bridge circuit and the upper three bridge signals P1_PWM_UHS_1, P1_PWM_VHS_1, P1_PWM_WHS_1 of the bridge circuit are delayed, which will reduce the dead time between the upper and lower bridge PWMs, thereby increasing the risk of direct conduction, so the upper three bridge signals of the bridge circuit can also pass through a first-level or gate chip, and the U8 input is P1_PWM_UHS_1. , P1_PWM_VHS_1, P1_PWM_WHS_1, U8 output is one pin P1_PWM_UHS_2, P1_PWM_VHS_2, P1_PWM_WHS_2, the other pin is connected to DGND as a low level, then the output of U8 will follow the input P1_PWM_UHS_2, P1_PWM_VHS_2, P1_PWM_WHS_2 and the lower three bridge signals P1_PWM_ULS_2, P1_PWM_VLS_2, P1_PWM_WLS_2 of the original bridge circuit. The dead time is closer to the dead time of the initial wave setting of DSP.

[0094] In another embodiment, the lower bridge logic circuit in the overvoltage protection circuit is implemented by NMOS+PMOS. Figure 6 As shown, when working condition 3 occurs, P1_DRV_HW_SHUTL is at a high level, and Q4 is turned on due to the GS voltage difference of 5V, then the G pole voltage of Q1, Q2, and Q3 will be pulled down to 0V, and the GS voltage will be 5V, then Q1, Q2, and Q3 will be turned on, and P1_PWM_UHS_2, P1_PWM_VHS_2, and P1_PWM_WHS_2 will be pulled up to a high level by Vsafe_5V, thereby realizing the high-level ASC of the lower bridge, and the lower three bridges (P1_PWM_ULS_1, P1_PWM_VLS_1, and P1_PWM_WLS_1) will maintain a low-level sealing wave due to the presence of the pull-down resistor.

[0095] In another embodiment, the lower bridge logic circuit in the overvoltage protection circuit is implemented using a relay, such as Figure 7 As shown, when working condition 3 occurs, P1_DRV_HW_SHUTL is at a high level, the relay coil K1A is energized, and the relay contacts K1B, K2B, and K3B are closed, then P1_PWM_UHS_2, P1_PWM_VHS_2, and P1_PWM_WHS_2 will be pulled up to a high level by Vsafe_5V, thereby realizing the lower bridge high level ASC.

[0096] In another embodiment, the lower bridge logic circuit in the overvoltage protection circuit is implemented by a relay + NMOS tube, such as Figure 7 As shown, when working condition 3 occurs, P1_DRV_HW_SHUTL is at a high level, the MOS tube Q1 is closed, the relay coil K1AX2 is pulled down to the ground, the coil K1A is energized, the relay contacts K1B, K2B, and K3B are closed, and P1_PWM_UHS_2, P1_PWM_VHS_2, and P1_PWM_WHS_2 will be pulled up to a high level by Vsafe_5V, thereby realizing the lower bridge high level ASC.

[0097] In summary, the control method provided by this application, in the case of software reset, the output end of the controller is in an unstable state, and the method of adding a pull-down resistor outside the ENSW can be used to monitor whether the software is reset. If a reset occurs, the PWM output is turned off. If the bus overvoltage occurs further, the hardware three-bridge forced ASC state is entered to ensure that the hardware is not damaged. At the same time, it is compatible with the original overvoltage lower bridge ASC logic. After the software restores control, it can switch to the original overvoltage lower bridge ASC logic to achieve redundancy of the protection scheme.

[0098] Furthermore, in the case of abnormal power supply of the VQUC5V power supply, a stable power supply Vsafe_5V is provided to ensure that the overvoltage signal can be stable, so that the forced ASC state of the three bridges under the hardware can remain stable.

[0099] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0100] In addition, in the description of the embodiments of the present application, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For those skilled in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0101] In the description of the present application, the terms “first”, “second” and “third” are used for descriptive purposes only and should not be understood as indicating or implying relative importance.

[0102] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above embodiments, those skilled in the art should understand that any person skilled in the art who is familiar with the technical field can still modify the technical solutions recorded in the above embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. An overvoltage protection circuit, characterized in that: The overvoltage protection circuit comprises: a controller that generates and outputs an active short-circuit maintaining signal; A logic chip circuit, whose input end is connected to the output end of the controller, and the logic chip circuit controls the output of the lower bridge driving signal based on the active short-circuit maintenance signal; An active short circuit maintaining circuit has its input end connected to the output end of the controller and the output end of the logic chip circuit respectively, and the active short circuit maintaining circuit controls the lower bridge driving signal to drive the lower bridge circuit and maintain it in an active short circuit state.

2. The overvoltage protection circuit according to claim 1, characterized in that: The logic chip circuit comprises: a switch circuit and a logic chip; The input end of the switch circuit is connected to the output end of the controller, and the output end of the switch circuit is connected to the input end of the logic chip; Under the action of the active short-circuit maintaining signal, the switch circuit controls the logic chip to be turned on, and outputs the bridge driving signal received by the input end of the logic chip from the output end of the logic chip to the active short-circuit maintaining circuit.

3. The overvoltage protection circuit according to claim 2, characterized in that: The switch circuit at least includes a first switch tube, a current limiting resistor and a bias circuit; The gate of the first switch tube is connected to the output end of the controller through the current limiting resistor, and is used to receive the active short-circuit maintaining signal; The drain of the first switch tube is connected to the control terminal of the logic chip, and is used to output a switch signal to control the conduction of the logic chip; The source of the first switch tube is connected to the gate of the first switch tube through the bias circuit.

4. The overvoltage protection circuit according to claim 1, characterized in that: The active short circuit maintaining circuit comprises: A state maintaining circuit, whose input end is connected to the output end of the controller, is used to receive an overvoltage signal and a software reset signal, and generate an active short-circuit driving signal for the lower bridge circuit based on the overvoltage signal and the software reset signal; The lower bridge logic circuit has an input end respectively connected to the output end of the state maintaining circuit and the lower bridge output end in the logic chip circuit, and is used to drive the lower bridge circuit based on the active short circuit drive signal and the lower bridge drive signal and maintain it in an active short circuit state.

5. The overvoltage protection circuit according to claim 4, characterized in that: The state maintaining circuit comprises: A logic gate circuit connected to the output terminal of the controller, used for performing a logic operation on the received overvoltage signal and the reset signal of the software, and outputting a first operation result and a second operation result; The inverter provided between the output end of the logic gate circuit and the input end of the lower bridge logic circuit is used to invert the first operation result to obtain an active short-circuit drive signal, and to invert the second operation result to obtain a conduction signal of the logic chip circuit.

6. The overvoltage protection circuit according to claim 5, characterized in that: The logic gate circuit includes a first OR gate and a first AND gate, and the input end of the first OR gate and the input end of the first AND gate are both connected to the output end of the controller; The first OR gate is used to perform an OR operation on the overvoltage signal and the software reset signal to obtain a first operation result; The first AND gate is used to perform an AND operation on the software reset signal and the hardware drive signal to obtain a second operation result.

7. The overvoltage protection circuit according to claim 4, characterized in that: The active short circuit maintaining circuit also includes: The upper bridge logic circuit has an input end connected to the upper bridge output end of the logic chip circuit, and is used to perform a logic operation on the upper bridge drive signal output by the logic chip circuit, and control the upper bridge circuit to enter the wave envelope based on the result of the operation.

8. The overvoltage protection circuit according to claim 4, characterized in that: The lower bridge logic circuit includes at least one second OR gate; the first output end of the at least one second OR gate is connected to the output end of the state maintenance circuit, and the first output end of the at least one second OR gate is connected to the lower bridge output end in the logic chip circuit.

9. The overvoltage protection circuit according to claim 4, characterized in that: The lower bridge logic circuit includes a second switch tube and at least one third switch tube; The gate of the second switch tube is connected to the output end of the state maintaining circuit and is used to receive an active short-circuit driving signal; The drain of the second switch tube is connected to the gate of the at least one third switch tube, and the drain of the at least one third switch tube is connected to the lower bridge output end of the logic chip circuit through a resistor; The source of the second switch tube is connected to the gate of the second switch tube through a resistor and a capacitor.

10. The overvoltage protection circuit according to claim 4, characterized in that: The lower bridge logic circuit includes a coil and at least one magnetic switch; The coil is connected in parallel between the output terminal of the state maintaining circuit and the ground, and is used to generate a magnetic attraction force based on the active short-circuit driving signal; The at least one magnetic switch is connected to the lower bridge output terminal of the logic chip circuit, and is used to output the lower bridge drive signal to the lower bridge circuit under the control of the magnetic attraction force.

11. The overvoltage protection circuit according to claim 10, characterized in that: The lower bridge logic circuit also includes a fourth switch tube; The coil is connected in series to the drain of the fourth switch tube, the gate of the fourth switch tube is connected to the output end of the state maintaining circuit, and the source of the fourth switch tube is connected to the gate of the fourth switch tube through a resistor and a capacitor.

12. The overvoltage protection circuit according to any one of claims 1 to 11, characterized in that: The overvoltage protection circuit also includes: an independent power supply, which is used to provide a voltage signal for the active short circuit maintaining circuit.

13. A power conversion device, characterized in that: The power conversion device comprises a driving signal generating circuit, at least one overvoltage protection circuit according to any one of claims 1 to 12, and a bridge circuit connected in series, wherein the bridge circuit comprises at least one switching device.

14. A control method applied to the power conversion device according to claim 13, characterized in that: The control method comprises: When determining that the bus voltage is over-voltage, generating and outputting an active maintenance signal; Based on the active short-circuit maintaining signal, the lower bridge driving signal generated by the driving signal generating circuit is controlled to be output to the lower bridge circuit in the bridge circuit; After the lower bridge driving signal is output to the lower bridge circuit, the active short circuit maintaining circuit controls the lower bridge driving signal to drive the lower bridge circuit and maintain it in an active short circuit state.

15. The control method of the power conversion device according to claim 14, characterized in that: The generating and outputting the active maintenance signal comprises: Generate an active short-circuit maintenance signal based on an overvoltage signal of a bus voltage overvoltage and a reset signal of the logic chip circuit; The active short circuit maintaining signal is output to the switch circuit in the logic chip circuit and the active short circuit maintaining circuit.

16. The control method of the power conversion device according to claim 15, characterized in that: The active short circuit maintaining circuit controls the lower bridge driving signal to drive the lower bridge circuit and maintain it in an active short circuit state, including: Generate an active short-circuit drive signal for the lower bridge circuit based on the overvoltage signal and the reset signal; The lower bridge circuit is driven based on the active short-circuit driving signal and the lower bridge driving signal, and is maintained in an active short-circuit state.

17. The control method of a power conversion device according to any one of claims 14 to 16, characterized in that: The control method further includes: When it is determined that the bus voltage is not over-voltage and a reset signal is detected, the active short-circuit maintenance circuit outputs an enable signal of the logic chip circuit based on the reset signal; The logic chip circuit is controlled to output a driving signal of the bridge circuit based on the enable signal.

Images