Charge pump design with low current ripple and low current mismatch

Abstract

The invention belongs to the technical field of integrated circuits, and discloses a charge pump design with low current mismatch and low current ripples in order to solve the problem of current ripples of a charge pump. In order to achieve the target, the charge pump comprises a current source circuit, a rail-to-rail operational amplifier circuit and a cascode circuit capable of being controlled by a switch. Wherein the rail-to-rail operational amplifier circuit can mirror the current of the circuit to reduce current ripples caused by a charge sharing effect; two switch tubes at the upper end of the switch-controlled cascode circuit are controlled through UP and UPbar signals, and two switch tubes at the lower end of the switch-controlled cascode circuit are controlled through DN and DNbar signals. According to the invention, stable charging and discharging current can be provided for the phase-locked loop circuit.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, and in particular to the design of a charge pump with lower requirements on current mismatch and current noise. Background Art

[0002] In integrated circuit design, a charge pump is a key circuit module that uses the charge accumulation characteristics of a capacitor to generate voltage. It converts the input signal into charge and uses a switch-controlled current source to charge or discharge the capacitor at the output to form the required output voltage signal. Charge pumps play an important role in systems such as phase-locked loops (PLLs), especially in applications such as frequency synthesis, clock recovery, and phase synchronization. Its performance directly affects the stability and accuracy of the entire system.

[0003] The core working principle of the charge pump relies on the charging and discharging process of the capacitor. When the input signal controls the switch to switch, the current source pumps charge into or out of the capacitor, resulting in a voltage change at the output. This process requires precise timing control and current matching to ensure the stability and accuracy of the output voltage. The performance indicators of the charge pump, such as the matching degree of the current source, power consumption, response speed, and noise characteristics, will have a significant impact on the quality of the output signal. For example, the mismatch of the current source will cause the output voltage to deviate, while excessive power consumption or slow response speed will limit the use of the charge pump in high-frequency or low-power applications. Summary of the invention

[0004] In order to overcome the deficiencies of the prior art, the present invention provides a charge pump design method with low current ripple and low current mismatch.

[0005] The present invention is achieved through the following scheme:

[0006] A charge pump design with low current ripple and low current mismatch includes a current source circuit, a rail-to-rail operational amplifier circuit and a switch-controlled common-source and common-gate circuit.

[0007] Further, the current source circuit includes a DC current source I1, a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a fifth NMOS tube M5, a sixth NMOS tube M6, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, and a fourth PMOS tube P4;

[0008] The first output end of the DC current source I1 and the sources of the first, third and fourth PMOS tubes P1, P3 and P4 are connected to the positive power supply voltage, the second output end of the DC current source I1 is connected to the drain of the first NMOS tube M1 and the gates of the first, second and fourth NMOS tubes M1, M2 and M4, the sources of the first, second and fourth NMOS tubes M1, M2 and M4 are connected to the negative power supply voltage, the drain of the second NMOS tube M2 is connected to the source of the third NMOS tube M3, the gate of the third NMOS tube M3 is connected to the signal EN, the drain of the third NMOS tube M3 is connected to the drain of the second PMOS tube P2 The gate of the second PMOS tube P2 is connected to the signal EN_bar, the source of the second PMOS tube P2 is connected to the gate and drain of the first PMOS tube P1, and the gate of the sixth PMOS tube is connected to the second lower end of the capacitor C1.

[0009] Further, the switch-controlled cascode circuit includes a seventh NMOS tube M7, an eighth NMOS tube M8, a ninth NMOS tube M9, a fifth PMOS tube P5, a sixth PMOS tube P6, and a seventh PMOS tube P7;

[0010] The gate of the seventh NMOS tube M7 is connected to the gate of the first NMOS tube in the current source circuit, the drain of the seventh NMOS tube M7 is connected to the source of the eighth and ninth NMOS tubes M8 and M9, the gate of the eighth NMOS tube M8 is connected to the signal DN, the gate of the ninth NMOS tube M9 is connected to the signal DN_bar, the drain of the eighth NMOS tube M8 is connected to the output end and the inverting input end of the rail-to-rail operational amplifier circuit and the drain of the sixth PMOS tube P6, the drain of the ninth NMOS tube M9 is connected to the drain of the seventh PMOS tube P7, the non-inverting input end of the rail-to-rail operational amplifier circuit and the output signal Vctrl, the gate of the fifth PMOS tube P5 is connected to the gate of the first PMOS tube P1 in the current source circuit, the drain of the fifth PMOS tube P5 is connected to the source of the sixth and seventh PMOS tubes P6 and P7, the gate of the sixth PMOS tube P6 is connected to the signal UP, and the gate of the seventh PMOS tube P7 is connected to the signal UP_bar.

[0011] Further, the rail-to-rail operational amplifier circuit includes a first DC voltage source V1, a second DC voltage source V2, a third DC voltage source V3, a fourth DC voltage source V4, a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a fifth NMOS tube M5, a sixth NMOS tube M6, a seventh NMOS tube M7, an eighth NMOS tube M8, a ninth NMOS tube M9, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, and a seventh PMOS tube P7;

[0012] The sources of the first and second PMOS tubes P1 and P2 are connected, the gate of the seventh NMOS tube M7 is connected to the second output end of the fourth DC voltage source V4, the source of the seventh NMOS tube M7 is connected to the gates of the eighth and ninth NMOS tubes M8 and M9, and the drain of the eighth NMOS tube M8, the drain of the ninth NMOS tube M9 is connected to the sources of the first and second NMOS tubes M1 and M2, the drain of the first NMOS tube M1 is connected to the drain of the fourth PMOS tube P4 and the source of the sixth PMOS tube P6 The drain of the second NMOS tube M2 is connected to the drain of the third PMOS tube P3 and the source of the fifth PMOS tube P5. The sources of the third and fourth PMOS tubes P3 and P4 are connected to the power supply voltage. The drain of the first PMOS tube P1 is connected to the source of the sixth NMOS tube M6 and the drain of the fourth NMOS tube M4. The source of the second PMOS tube P2 is connected to the source of the fifth NMOS tube M5 and the drain of the third NMOS tube M3. The fifth PMOS tube P5 and the fifth NMOS tube N5 are connected to the drain of the third NMOS tube M3. The drain is connected to the gate of the third NMOS tube N3 and the fourth NMOS tube N4, the gate of the third PMOS tube P3 and the gate of the fourth PMOS tube N4 are connected to the second output end of the first voltage source V1, the gate of the fifth PMOS tube P5 and the gate of the sixth PMOS tube P6 are connected to the second output end of the second voltage source V2, the gate of the fifth NMOS tube N5 and the gate of the sixth NMOS tube N6 are connected to the second output end of the third voltage source V3, the sources of the eighth, ninth, third and fourth NMOS tubes N8, N9, N3 and N4, the first output ends of the first, second, third and fourth DC voltage sources V1, V2, V3 and V4 are connected to the negative power supply voltage, the sources of the third and fourth PMOS tubes P3 and P4 are connected to the positive power supply voltage, the input end VN is connected to the gates of the first NMOS tube N1 and the first PMOS tube P1, the input end VP is connected to the gates of the second NMOS tube N2 and the second PMOS tube P2, and the output end Vout is connected to the drains of the sixth PMOS tube P6 and the sixth NMOS tube N6.

[0013] The advantages and positive effects of the present invention are: the present invention designs a charge pump with low current ripple and low current mismatch, the rail-to-rail operational amplifier can track the output voltage, so that the output voltage can cover a larger variation range, and the design of the current source circuit can reduce the error of the charging and discharging current. These two methods make the charge pump proposed by the present invention have a very high current matching degree. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 The structural block diagram of the overall circuit in the present invention is

[0015] Figure 2 The circuit diagram of the charge pump in the present invention is

[0016] Figure 3 The specific circuit diagram of the rail-to-rail operational amplifier circuit in the present invention is DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0018] PMOS refers to a MOS tube with an N-type substrate and a P-type channel, which transports current by the flow of holes;

[0019] NMOS refers to a MOS tube with a P-type substrate and an N-type channel, which relies on the flow of electrons to transport current.

[0020] like Figure 2 As shown, the current source circuit includes a DC current source I1, a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a fifth NMOS tube M5, a sixth NMOS tube M6, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, and a fourth PMOS tube P4;

[0021] The first output end of the DC current source I1 and the sources of the first, third and fourth PMOS tubes P1, P3 and P4 are connected to the positive power supply voltage, the second output end of the DC current source I1 is connected to the drain of the first NMOS tube M1 and the gates of the first, second and fourth NMOS tubes M1, M2 and M4, the sources of the first, second and fourth NMOS tubes M1, M2 and M4 are connected to the negative power supply voltage, the drain of the second NMOS tube M2 is connected to the source of the third NMOS tube M3, the gate of the third NMOS tube M3 is connected to the signal EN, the drain of the third NMOS tube M3 is connected to the drain of the second PMOS tube P2 The gate of the second PMOS tube P2 is connected to the signal EN_bar, the source of the second PMOS tube P2 is connected to the gate and drain of the first PMOS tube P1, and the gate of the sixth PMOS tube is connected to the second lower end of the capacitor C1.

[0022] In this embodiment, when the enable signal EN is at a low level and the EN_bar signal is at a high level, the third NMOS tube M3 and the second PMOS tube P2 are in an off state, and there is no current in the left circuit, so it cannot be mirrored to the common source and common gate circuit through the current mirror, and the entire circuit does not work. When the enable signal EN is at a high level and the EN_bar signal is at a low level, the third NMOS tube M3 and the second PMOS tube P2 are in an on state, and the circuit starts to work.

[0023] First, reduce the current mismatch caused by the channel length modulation effect. The current mirror composed of the first NMOS tube M1 and the second NMOS tube M2 copies the current of the DC current source I1 to the branch where the second and third NMOS tubes M2 and M3 and the first and second PMOS tubes P1 and P2 are located; secondly, since the second and seventh NMOS tubes M2 and M7 and the first and fifth PMOS tubes P1 and P5 are designed in equal proportion, the charging current of the fifth PMOS tube P5 and the discharging current of the seventh NMOS tube M7 should be equal in theory, but due to the channel length modulation effect, there is a deviation between the two currents; finally , a five-tube operational amplifier consisting of the fourth, fifth, and sixth NMOS tubes M4, M5, and M6 and the third and fourth PMOS tubes P3 and P4 is used to reduce the channel length modulation effect, the current mirror composed of the first and fourth NMOS tubes M1 and M4 provides a tail current for the five-tube operational amplifier, and the virtual short characteristic of the operational amplifier is used to make the drain end of the third NMOS tube M3 and the drain end of the ninth PMOS tube M9 equal in potential, so that the error of the mirror current of the seventh NMOS tube M7 and the fifth PMOS tube P5 caused by the channel length modulation effect can be reduced, thereby reducing the mismatch current.

[0024] Second, reduce the current mismatch caused by charge sharing. Conventional charge pump outputs usually have only one branch. When the MOS tube that controls the charge and discharge switch changes from off to on, due to the charge sharing effect, the potential of the output terminal Vctrl will redistribute the charge on the parasitic capacitance of the switch MOS tube and the current source MOS, causing jitter on the output voltage. Therefore, the present invention designs a mirror branch, and the eighth and ninth NMOS tubes M8 and M9 and the sixth and seventh PMOS tubes P6 and P7 are controlled by a pair of complementary signals DN and DN_bar and UP and UP_bar respectively. When the DN signal is high and the UP signal is high, the eighth NMOS tube M8 is turned on, the ninth NMOS tube M9 is turned off, the sixth PMOS tube P6 is turned off, and the seventh MOS tube P7 is turned on. At this time, the current mirrored by the charge pump through the fifth PMOS tube P5 flows through the seventh PMOS tube P7 to charge the capacitor C1, but due to the virtual short effect of the rail-to-rail operational amplifier, the voltage at the drain end of the eighth NMOS tube M8 is almost the same as the voltage at the output end Vctrl, so the current still flows through the seventh NMOS tube M7, and its drain-source voltage does not change with the switch, so there is no charge sharing problem.

[0025] In this embodiment, since the voltage variation of the output terminal Vctrl is relatively large, the input voltage range of the operational amplifier needs to be designed to be very wide, so a rail-to-rail input structure design is adopted. Figure 3As shown, the rail-to-rail operational amplifier circuit includes a first DC voltage source V1, a second DC voltage source V2, a third DC voltage source V3, a fourth DC voltage source V4, a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a fifth NMOS tube M5, a sixth NMOS tube M6, a seventh NMOS tube M7, an eighth NMOS tube M8, a ninth NMOS tube M9, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, and a seventh PMOS tube P7;

[0026] The sources of the first and second PMOS tubes P1 and P2 are connected, the gate of the seventh NMOS tube M7 is connected to the second output end of the fourth DC voltage source V4, the source of the seventh NMOS tube M7 is connected to the gates of the eighth and ninth NMOS tubes M8 and M9, and the drain of the eighth NMOS tube M8, the drain of the ninth NMOS tube M9 is connected to the sources of the first and second NMOS tubes M1 and M2, the drain of the first NMOS tube M1 is connected to the drain of the fourth PMOS tube P4 and the source of the sixth PMOS tube P6 The drain of the second NMOS tube M2 is connected to the drain of the third PMOS tube P3 and the source of the fifth PMOS tube P5. The sources of the third and fourth PMOS tubes P3 and P4 are connected to the power supply voltage. The drain of the first PMOS tube P1 is connected to the source of the sixth NMOS tube M6 and the drain of the fourth NMOS tube M4. The source of the second PMOS tube P2 is connected to the source of the fifth NMOS tube M5 and the drain of the third NMOS tube M3. The fifth PMOS tube P5 and the fifth NMOS tube N5 are connected to the drain of the third NMOS tube M3. The drain is connected to the gate of the third NMOS tube N3 and the fourth NMOS tube N4, the gate of the third PMOS tube P3 and the gate of the fourth PMOS tube N4 are connected to the second output end of the first voltage source V1, the gate of the fifth PMOS tube P5 and the gate of the sixth PMOS tube P6 are connected to the second output end of the second voltage source V2, the gate of the fifth NMOS tube N5 and the gate of the sixth NMOS tube N6 are connected to the second output end of the third voltage source V3, the sources of the eighth, ninth, third and fourth NMOS tubes N8, N9, N3 and N4, the first output ends of the first, second, third and fourth DC voltage sources V1, V2, V3 and V4 are connected to the negative power supply voltage, the sources of the third and fourth PMOS tubes P3 and P4 are connected to the positive power supply voltage, the input end VN is connected to the gates of the first NMOS tube N1 and the first PMOS tube P1, the input end VP is connected to the gates of the second NMOS tube N2 and the second PMOS tube P2, and the output end Vout is connected to the drains of the sixth PMOS tube P6 and the sixth NMOS tube N6.

[0027] In this embodiment, when the input voltage is close to the negative power supply voltage rail, the first NMOS tube M1 and the second NMOS tube M2 are turned off, and only the first PMOS tube P1 and the second PMOS tube P2 work. At this time, the signal is output through the first PMOS tube P1, the second PMOS tube P2, and the summing circuit composed of the third PMOS tube P3, the fourth PMOS tube P4, the fifth PMOS tube P5, the sixth PMOS tube P6, the third NMOS tube M3, the fourth NMOS tube M4, the fifth NMOS tube M5, and the sixth NMOS tube M6;

[0028] When the input voltage is near the middle value of the positive and negative power supply voltages, the first NMOS transistor M1, the second NMOS transistor M2, the first PMOS transistor P1, and the second PMOS transistor P2 are all in the on state, but since the two differential pairs are biased by the current mirror formed by the seventh PMOS transistor P7 and the first PMOS transistor P1 in the current source circuit, by reasonably selecting the value of the fourth DC voltage source V4, the current flowing through the PMOS differential pair and the current flowing through the NMOS differential pair are reasonably distributed, ensuring that the transconductance of the input stage is in a relatively constant region;

[0029] When the input voltage is close to the positive power supply voltage rail, the first PMOS tube P1 and the second PMOS tube P2 are turned off, and only the first NMOS tube M1 and the second NMOS tube M2 work. The current mirrored by the seventh PMOS tube P7 flows through the first NMOS tube M1 and the second NMOS tube M2 through the current mirror composed of the seventh NMOS tube M7, the eighth NMOS tube M8 and the ninth NMOS tube M9, and then outputs through the summing circuit composed of the third PMOS tube P3, the fourth PMOS tube P4, the fifth PMOS tube P5, the sixth PMOS tube P6, the third NMOS tube M3, the fourth NMOS tube M4, the fifth NMOS tube M5 and the sixth NMOS tube M6.

[0030] The above description is only a preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered by the protection scope of the present invention.

Claims

1. A charge pump with low current mismatch, characterized in that The invention comprises a current source circuit, a rail-to-rail operational amplifier circuit and a switch-controlled cascode circuit; wherein the current source circuit controls the working state of the circuit and provides charging and discharging current for the cascode circuit at the same time, the circuit starts to work when the EN signal is high, and the circuit is in the off state when the EN signal is low, and the output terminal Vctrl of the switch-controlled cascode circuit is connected to an external capacitor for charging and discharging operations; the upper and lower ends of the switch-controlled cascode circuit are respectively connected to four switch signals, the two switch tubes at the upper end are controlled by the input signals UP and UP_bar, and the two switch tubes at the lower end are controlled by the DN and DN_bar signals, when the UP signal is high and the DN signal is high, the output terminal Vctrl will charge the external capacitor; when the UP signal is low and the DN signal is low, the output terminal Vctrl will discharge the external capacitor; when the UP signal is high and the DN signal is low, all four switch tubes are closed, and the circuit remains balanced.

2. The low current mismatch charge pump according to claim 1, characterized in that The current source circuit includes a direct current source I1, a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a fifth NMOS tube M5, a sixth NMOS tube M6, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, and a fourth PMOS tube P4; The first output end of the DC current source I1 and the sources of the first, third and fourth PMOS tubes P1, P3 and P4 are connected to the positive power supply voltage, the second output end of the DC current source I1 is connected to the drain of the first NMOS tube M1 and the gates of the first, second and fourth NMOS tubes M1, M2 and M4, the sources of the first, second and fourth NMOS tubes M1, M2 and M4 are connected to the negative power supply voltage, the drain of the second NMOS tube M2 is connected to the source of the third NMOS tube M3, the gate of the third NMOS tube M3 is connected to the signal EN, the drain of the third NMOS tube M3 is connected to the drain of the second PMOS tube P2 The gate of the second PMOS tube P2 is connected to the signal EN_bar, the source of the second PMOS tube P2 is connected to the gate and drain of the first PMOS tube P1, and the gate of the sixth PMOS tube is connected to the second lower end of the capacitor C1.

3. The low current mismatch charge pump according to claim 1, characterized in that The switch-controlled cascode circuit includes a seventh NMOS tube M7, an eighth NMOS tube M8, a ninth NMOS tube M9, a fifth PMOS tube P5, a sixth PMOS tube P6, and a seventh PMOS tube P7; The gate of the seventh NMOS tube M7 is connected to the gate of the first NMOS tube in the current source circuit, the drain of the seventh NMOS tube M7 is connected to the source of the eighth and ninth NMOS tubes M8 and M9, the gate of the eighth NMOS tube M8 is connected to the signal DN, the gate of the ninth NMOS tube M9 is connected to the signal DN_bar, the drain of the eighth NMOS tube M8 is connected to the output end and the inverting input end of the rail-to-rail operational amplifier circuit and the drain of the sixth PMOS tube P6, the drain of the ninth NMOS tube M9 is connected to the drain of the seventh PMOS tube P7, the non-inverting input end of the rail-to-rail operational amplifier circuit and the output signal Vctrl, the gate of the fifth PMOS tube P5 is connected to the gate of the first PMOS tube P1 in the current source circuit, the drain of the fifth PMOS tube P5 is connected to the source of the sixth and seventh PMOS tubes P6 and P7, the gate of the sixth PMOS tube P6 is connected to the signal UP, and the gate of the seventh PMOS tube P7 is connected to the signal UP_bar.

4. The low current mismatch charge pump according to claim 1, wherein: The rail-to-rail operational amplifier circuit includes a first DC voltage source V1, a second DC voltage source V2, a third DC voltage source V3, a fourth DC voltage source V4, a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a fifth NMOS tube M5, a sixth NMOS tube M6, a seventh NMOS tube M7, an eighth NMOS tube M8, a ninth NMOS tube M9, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, and a seventh PMOS tube P7; The sources of the first and second PMOS tubes P1 and P2 are connected, the gate of the seventh NMOS tube M7 is connected to the second output end of the fourth DC voltage source V4, the source of the seventh NMOS tube M7 is connected to the gates of the eighth and ninth NMOS tubes M8 and M9, and the drain of the eighth NMOS tube M8, the drain of the ninth NMOS tube M9 is connected to the sources of the first and second NMOS tubes M1 and M2, the drain of the first NMOS tube M1 is connected to the drain of the fourth PMOS tube P4 and the source of the sixth PMOS tube P6 The drain of the second NMOS tube M2 is connected to the drain of the third PMOS tube P3 and the source of the fifth PMOS tube P5. The sources of the third and fourth PMOS tubes P3 and P4 are connected to the power supply voltage. The drain of the first PMOS tube P1 is connected to the source of the sixth NMOS tube M6 and the drain of the fourth NMOS tube M4. The source of the second PMOS tube P2 is connected to the source of the fifth NMOS tube M5 and the drain of the third NMOS tube M3. The fifth PMOS tube P5 and the fifth NMOS tube N5 are connected to the drain of the third NMOS tube M3. The drain is connected to the gate of the third NMOS tube N3 and the fourth NMOS tube N4, the gate of the third PMOS tube P3 and the gate of the fourth PMOS tube N4 are connected to the second output end of the first voltage source V1, the gate of the fifth PMOS tube P5 and the gate of the sixth PMOS tube P6 are connected to the second output end of the second voltage source V2, the gate of the fifth NMOS tube N5 and the gate of the sixth NMOS tube N6 are connected to the second output end of the third voltage source V3, the sources of the eighth, ninth, third and fourth NMOS tubes N8, N9, N3 and N4, the first output ends of the first, second, third and fourth DC voltage sources V1, V2, V3 and V4 are connected to the negative power supply voltage, the sources of the third and fourth PMOS tubes P3 and P4 are connected to the positive power supply voltage, the input end VN is connected to the gates of the first NMOS tube N1 and the first PMOS tube P1, the input end VP is connected to the gates of the second NMOS tube N2 and the second PMOS tube P2, and the output end Vout is connected to the drains of the sixth PMOS tube P6 and the sixth NMOS tube N6.

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