Multiphase digital orthogonal frequency mixing method and system

Abstract

The invention discloses a multiphase digital orthogonal frequency mixing method and system, relates to the technical field of modern digital signal processing, and is used for solving the problems of large resource consumption, large power consumption and large errors in the existing multiphase digital orthogonal frequency mixing scheme. The method is applied to a multiphase digital orthogonal frequency mixing system comprising an acquisition module and an FPGA (Field Programmable Gate Array) module, and comprises the following steps: carrying out initial configuration on the acquisition module through the FPGA module; if the acquisition module is determined to work normally and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is 3 / 4 or 1 / 4, performing preset multi-phase digital orthogonal frequency mixing logic processing on a sub-intermediate frequency signal corresponding to any channel through an FPGA module to obtain a sub-I signal and a sub-Q signal corresponding to the sub-intermediate frequency signal; wherein the preset multi-phase digital orthogonal frequency mixing logic processing only comprises holding, zero setting and negation, and complex operations such as multiplication are not needed any more, so that resource consumption, power consumption and errors of a multi-phase digital orthogonal frequency mixing scheme are reduced.

Description

Technical Field

[0001] The present application relates to the technical field of modern digital signal processing, and provides a multi-phase digital orthogonal mixer and system. Background Art

[0002] With the development of modern superheterodyne receivers, the frequency of intermediate frequency signals is getting higher and higher, and the bandwidth is getting larger and larger. In this case, multi-phase digital orthogonal mixing of intermediate frequency signals has become a common solution in the industry. Figure 1 As shown in the figure, it is an existing multi-phase digital orthogonal mixing scheme. Figure 1 It can be seen that the existing multi-phase digital orthogonal mixing scheme has the following defects: (1) Since a DDS core and two multipliers are required to calculate each sub-I and Q signal, a total of n DDS cores and 2n multipliers (n is the number of sub-IF signals) are required to complete the entire digital orthogonal mixing process. Therefore, if the IF signal of a receiver is very high and the bandwidth is very large, it is necessary to separate many sub-IF signals. At this time, the resource consumption is very large, which leads to excessive power consumption; (2) Since the DDS core is ultimately a digital circuit, it has quantization errors and cannot accurately generate sub-LO signals of specified frequency and initial phase. Therefore, strictly speaking, the sub-I and Q signals obtained by multiplying the sub-LO signal generated by the DDS core by the sub-IF signal have errors, and the errors can only be reduced but not completely eliminated.

[0003] Therefore, how to reduce the resource consumption, power consumption and error of multi-phase digital orthogonal mixing schemes has become a problem that needs to be solved urgently. Summary of the invention

[0004] The present application provides a multi-phase digital orthogonal mixing method and system, which are used to solve the problems of large resource consumption, power consumption and error in existing multi-phase digital orthogonal mixing solutions.

[0005] On the one hand, a multi-phase digital orthogonal mixing method is provided, and the method is applied to a multi-phase digital orthogonal mixing system including an acquisition module and an FPGA module, comprising: For any channel, the acquisition module is initialized and configured through the FPGA module; Determine whether the acquisition module works normally and whether the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio; wherein the preset ratio is three quarters or one quarter; If it is determined that the acquisition module is operating normally, and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, the sub-intermediate frequency signal corresponding to any channel is subjected to a preset multi-phase digital orthogonal mixing logic processing through the FPGA module to obtain a sub-I signal and a sub-Q signal corresponding to the sub-intermediate frequency signal; wherein the preset multi-phase digital orthogonal mixing logic processing only includes holding, setting to 0, and inverting.

[0006] Optionally, the step of initializing the configuration of the acquisition module through the FPGA module includes: The clock chip and ADC chip of the acquisition module are initialized and configured through the acquisition module control logic of the FPGA module.

[0007] Optionally, the step of initializing and configuring the clock chip and the ADC chip of the acquisition module through the acquisition module control logic of the FPGA module includes: Controlling the clock chip to generate a sampling clock through a control protocol in the acquisition module control logic; wherein the control protocol is determined according to the ADC chip used; The sampling frequency of the ADC chip is initialized and set according to the control protocol, the sampling clock and the center frequency of the sub-intermediate frequency signal of any channel.

[0008] Optionally, if it is determined that the acquisition module is operating normally, and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, the step of performing a preset multi-phase digital orthogonal mixing logic processing on the sub-intermediate frequency signal corresponding to any channel through the FPGA module to obtain a sub-I signal and a sub-Q signal corresponding to the sub-intermediate frequency signal includes: If it is determined that the acquisition module is operating normally and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, the digital orthogonal mixing logic of the FPGA module is used to perform preset multi-phase digital orthogonal mixing logic processing on the sub-intermediate frequency signal corresponding to any channel according to the number to obtain the sub-I signal and sub-Q signal corresponding to the sub-intermediate frequency signal.

[0009] Optionally, after determining whether the acquisition module works normally and whether the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, the method further includes: If it is determined that the acquisition module does not work normally, or the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is not a preset ratio, the acquisition module is reconfigured through the FPGA module.

[0010] Optionally, after performing a preset multi-phase digital orthogonal mixing logic process on the sub-IF signal corresponding to any one of the channels through the FPGA module to obtain a sub-I signal and a sub-Q signal corresponding to the sub-IF signal, the method further includes: If the working channel changes, the acquisition module is reconfigured through the FPGA module.

[0011] Optionally, the sub-I signal is expressed by the following formula (1): (1) The sub-Q signal is expressed by the following formula (2): (2) in, is the sub-I signal corresponding to the k-th channel; is the sub-I signal corresponding to the k-th channel; f is the center frequency of the intermediate frequency signal; fc is the frequency of the digital local oscillator signal of the k-th channel; t is the time, is the initial phase corresponding to the kth sub-signal.

[0012] On the one hand, a multi-phase digital orthogonal mixing system is provided, which includes an acquisition module and an FPGA module; wherein the acquisition module is used to acquire intermediate frequency signals; and the FPGA module is responsible for controlling the acquisition module and multi-phase digital orthogonal mixing processing.

[0013] Optionally, the acquisition module includes a clock chip and an ADC chip; wherein the clock chip is used to provide a stable sampling clock; and the ADC chip is used to acquire and convert the intermediate frequency signal according to the sampling clock.

[0014] Optionally, the FPGA module includes acquisition module control logic and digital orthogonal mixing logic; wherein, the acquisition module control logic is used to control each chip in the acquisition module through a control protocol, so that the acquisition module works normally and ensures that the center frequency of the output intermediate frequency signal data is fixed to three quarters or one quarter of the ADC chip sampling rate; the digital orthogonal mixing logic is used to perform preset multi-phase digital orthogonal mixing logic processing on the sub-intermediate frequency signals corresponding to each channel to obtain sub-I signals and sub-Q signals corresponding to each sub-intermediate frequency signal.

[0015] Compared with the prior art, the beneficial effects of this application are: In the present application, for any channel, first, the acquisition module can be initialized and configured through the FPGA module; then, it can be determined whether the acquisition module is working normally and whether the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio; wherein the preset ratio is three quarters or one quarter; finally, if it is determined that the acquisition module is working normally and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, the sub-intermediate frequency signal corresponding to any channel can be subjected to a preset multi-phase digital orthogonal mixing logic processing through the FPGA module to obtain a sub-I signal and a sub-Q signal corresponding to the sub-intermediate frequency signal; wherein the preset multi-phase digital orthogonal mixing logic processing only includes the three simplest operations of hold, set to 0 and invert.

[0016] Therefore, in the present application, since the properties of the special points of trigonometric functions are fully utilized in principle, the DDS core is no longer needed, and the multiplication operation is simplified to the three simplest operations of preset hold, set to 0 and negate to obtain the sub-I signal and sub-Q signal corresponding to the sub-intermediate frequency signal. Therefore, compared with the prior art, the present application has technical advantages such as less resource consumption, low power consumption, and low delay, and there is no quantization error. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0018] Figure 1 A schematic diagram of an existing multi-phase digital orthogonal mixing solution provided in an embodiment of the present application; Figure 2 An electronic device provided in an embodiment of the present application; Figure 3 A schematic diagram of a framework of a multi-phase digital orthogonal mixing system provided in an embodiment of the present application; Figure 4 A schematic diagram of a multi-phase digital orthogonal mixing method provided in an embodiment of the present application; Figure 5 A schematic diagram of a multi-phase digital orthogonal mixing solution provided in an embodiment of the present application.

[0019] Markings in the figure: 20 - multi-phase digital orthogonal mixer, 201 - processor, 202 - memory, 203 - I / O interface, 204 - database. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme in the embodiment of the present application will be clearly and completely described below in conjunction with the drawings in the embodiment of the present application. Obviously, the described embodiment is only a part of the embodiment of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other arbitrarily. In addition, although the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in an order different from that here.

[0021] Glossary: Intermediate frequency signal, in modern digital superheterodyne receivers, is the signal obtained after the RF signal undergoes multiple stages of frequency conversion at the RF front end.

[0022] With the development of modern superheterodyne receivers, the frequency of intermediate frequency signals is getting higher and higher, and the bandwidth is getting larger and larger. In this case, multi-phase digital orthogonal mixing of intermediate frequency signals has become a common solution in the industry. Figure 1 As shown in the figure, it is an existing multi-phase digital orthogonal mixing scheme, in which the digitized intermediate frequency signal is first divided into multiple sub-intermediate frequency signals with fixed initial phases but different; then, multiple direct digital synthesizer (DDS) cores inside a programmable logic gate array (Field Programmable Gate Array, FPGA) are used to generate multiple sub-local oscillator signals with fixed initial phases but different, the sub-local oscillator signals and the initial phases of the sub-intermediate frequency signals correspond one to one, and each sub-local oscillator signal includes a cosine sub-local oscillator signal and a sine sub-local oscillator signal; finally, each initially corresponding cosine sub-local oscillator signal is multiplied with the sub-intermediate frequency signal to obtain a sub-I signal, and each initially corresponding sine sub-local oscillator signal is multiplied with the sub-intermediate frequency signal to obtain a sub-Q signal, thereby realizing multi-phase digital orthogonal mixing.

[0023] Depend on Figure 1It can be seen that the existing multi-phase digital orthogonal mixing scheme has the following defects: (1) Since a DDS core and two multipliers are required to calculate each sub-I and Q signal, the entire digital orthogonal mixing process requires a total of n DDS cores and 2n multipliers (n is the number of sub-IF signals). Therefore, if the frequency and bandwidth of a receiver IF signal are very high, it is necessary to separate many sub-IF signals. At this time, the resource consumption will be very large, resulting in an increase in power consumption. (2) Since the DDS core is a digital circuit after all, it has quantization errors and cannot accurately generate sub-LO signals of specified frequency and initial phase. Therefore, the sub-I and Q signals obtained by multiplying the sub-LO signals generated by the DDS core by the sub-IF signals strictly have errors. Although the quantization error can be reduced by increasing the quantization bit width of the frequency control word and phase control word of the DDS core, this can only reduce the error and cannot completely eliminate the error. Moreover, as the quantization bit width increases, the resources consumed to implement the DDS core will also increase, further exacerbating the first defect.

[0024] Based on this, an embodiment of the present application provides a multi-phase digital orthogonal mixing method, in which, for any channel, first, the acquisition module can be initialized and configured through the FPGA module; then, it can be determined whether the acquisition module is working normally, and whether the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio; wherein the preset ratio is three quarters or one quarter; finally, if it is determined that the acquisition module is working normally, and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, the sub-intermediate frequency signal corresponding to any channel can be subjected to a preset multi-phase digital orthogonal mixing logic processing through the FPGA module to obtain a sub-I signal and a sub-Q signal corresponding to the sub-intermediate frequency signal; wherein the preset multi-phase digital orthogonal mixing logic processing only includes the three simplest operations of hold, set to 0 and invert. Therefore, in the present application, since the properties of the special points of trigonometric functions are fully utilized in principle, the DDS core is no longer needed, and the multiplication operation is simplified to the three simplest operations of preset hold, set to 0 and negate to obtain the sub-I signal and sub-Q signal corresponding to the sub-intermediate frequency signal. Therefore, compared with the prior art, the present application has technical advantages such as less resource consumption, low power consumption, and low delay, and there is no quantization error.

[0025] After introducing the design ideas of the embodiments of the present application, the following briefly introduces the application scenarios to which the technical solutions of the embodiments of the present application can be applied. It should be noted that the application scenarios introduced below are only used to illustrate the embodiments of the present application and are not limited. In the specific implementation process, the technical solutions provided by the embodiments of the present application can be flexibly applied according to actual needs.

[0026] like Figure 2As shown, an electronic device provided in an embodiment of the present application is shown, and the electronic device may specifically be a multi-phase digital orthogonal mixer 20 .

[0027] The multi-phase digital orthogonal mixer 20 can be used to perform multi-phase digital orthogonal mixing on each sub-IF signal, for example, a personal computer (PC), a server, a laptop, etc. The multi-phase digital orthogonal mixer 20 may include one or more processors 201, a memory 202, an I / O interface 203, and a database 204. Specifically, the processor 201 may be a central processing unit (CPU), or a digital processing unit, etc. The memory 202 may be a volatile memory, such as a random-access memory (RAM); the memory 202 may also be a non-volatile memory, such as a read-only memory, a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD); or the memory 202 may be any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 202 may be a combination of the above memories. The memory 202 may store some program instructions of the multi-phase digital orthogonal mixing method provided in the embodiment of the present application, and these program instructions can be used to implement the steps of the multi-phase digital orthogonal mixing method provided in the embodiment of the present application when executed by the processor 201, so as to solve the problems of large resource consumption, power consumption and error in the existing multi-phase digital orthogonal mixing scheme. The database 204 may be used to store the frequency, sampling frequency, center frequency, preset ratio and other data of the digital local oscillator signal involved in the scheme provided in the embodiment of the present application.

[0028] In the embodiment of the present application, the multi-phase digital orthogonal mixer device 20 can obtain the intermediate frequency signal through the I / O interface 203, and then the processor 201 of the multi-phase digital orthogonal mixer device 20 will reduce the resource consumption, power consumption and error of the multi-phase digital orthogonal mixer solution according to the program instructions of the multi-phase digital orthogonal mixer method provided in the embodiment of the present application in the memory 202. In addition, the frequency, sampling frequency, center frequency and preset ratio of the digital local oscillator signal can also be stored in the database 204.

[0029] Of course, the method provided in the embodiment of the present application is not limited to Figure 2 The application scenarios shown can also be used in other possible application scenarios, and the embodiments of the present application are not limited thereto. Figure 2The functions that can be realized by each device in the application scenario shown will be described in the subsequent method embodiments, and will not be described in detail here. Below, the method of the embodiment of the present application will be introduced in conjunction with the accompanying drawings.

[0030] like Figure 3 As shown, it is a framework schematic diagram of the multi-phase digital orthogonal mixing system provided in an embodiment of the present application. Specifically, the multi-phase digital orthogonal mixing system includes an acquisition module and an FPGA module; wherein the acquisition module can be used to acquire the intermediate frequency signal; the FPGA module can be responsible for controlling the acquisition module and the multi-phase digital orthogonal mixing processing.

[0031] In a possible implementation, the acquisition module includes a clock chip and an ADC chip; wherein the clock chip can be used to provide a stable sampling clock; and the ADC chip can be used to acquire and convert the intermediate frequency signal according to the sampling clock.

[0032] In one possible implementation, the FPGA module includes an acquisition module control logic and a digital orthogonal mixing logic; wherein the acquisition module control logic can be used to control each chip in the acquisition module through a control protocol, so that the acquisition module works normally and ensures that the center frequency of the output intermediate frequency signal data is fixed to three quarters or one quarter of the ADC chip sampling rate; the digital orthogonal mixing logic can be used to perform preset multi-phase digital orthogonal mixing logic processing on the sub-intermediate frequency signals corresponding to each channel to obtain sub-I signals and sub-Q signals corresponding to each sub-intermediate frequency signal.

[0033] like Figure 4 As shown, it is a schematic diagram of a multi-phase digital orthogonal mixing method provided by an embodiment of the present application, and the method is applied to Figure 3 In the multiphase digital quadrature mixer system shown in the figure, Figure 2 The multi-phase digital orthogonal mixer 20 is used to perform the method. Specifically, the process of the method is described as follows.

[0034] Step 401: For any channel, the acquisition module is initialized and configured through the FPGA module.

[0035] In the embodiments of the present application, Figure 3As shown, the acquisition module includes a clock chip and an analog-to-digital converter (ADC) chip, etc. The clock chip can provide a stable sampling clock for the ADC chip. The FPGA module includes an acquisition module control logic and a digital orthogonal mixing logic. Furthermore, in an embodiment of the present application, when the acquisition module is initialized and configured through a field programmable gate array (FPGA) module, the acquisition module control logic of the FPGA module can be used to initialize and configure the clock chip and ADC chip of the acquisition module.

[0036] Furthermore, in order to ensure the accuracy of the initialization configuration, in an embodiment of the present application, when the clock chip and the ADC chip of the acquisition module are initialized and configured through the acquisition module control logic of the FPGA module, the clock chip can be controlled to generate a sampling clock through the control protocol in the acquisition module control logic; wherein the control protocol used is determined according to the ADC chip, and can generally be a serial peripheral interface (Serial Peripheral Interface, SPI) protocol or an integrated circuit bus (Inter-Integrated Circuit, IIC) protocol, etc.; then, the sampling frequency of the ADC chip can be initialized and set according to the control protocol, the sampling clock, and the center frequency of the sub-intermediate frequency signal of any channel. For example, the intermediate frequency signal of receiver A is divided into three channels. The center frequency of the first channel is 5.625 GHz, the center frequency of the second channel is 2.25 GHz, and the center frequency of the third channel is 0.75 GHz. According to the control protocol, sampling clock, and the center frequency of the sub-intermediate frequency signals of each channel, "center frequency / sampling frequency = 3 / 4 or 1 / 4" can be used. Then, the sampling frequency of the ADC chip in the first channel can be 7.5 GHz, and the sampling frequencies in the second and third channels can be 3 GHz.

[0037] Step 402: Determine whether the acquisition module works normally and whether the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio.

[0038] In the embodiment of the present application, the preset ratio is three quarters or one quarter.

[0039] Step 403: If it is determined that the acquisition module is operating normally, and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, the sub-intermediate frequency signal corresponding to any channel is processed by the FPGA module using a preset multi-phase digital orthogonal mixing logic to obtain a sub-I signal and a sub-Q signal corresponding to the sub-intermediate frequency signal.

[0040] In the embodiment of the present application, the preset multi-phase digital orthogonal mixing logic processing only includes the three simplest operations of hold, set to 0 and negate. Figure 3 As shown, if it is determined that the acquisition module is working normally, and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, the digital orthogonal mixing logic of the FPGA module can be used to perform a preset multi-phase digital orthogonal mixing logic process on the sub-IF signal corresponding to any channel according to the number, so as to obtain the sub-I signal and sub-Q signal corresponding to the sub-IF signal. Specifically, for the sub-I signal, the operations of holding, setting to 0, negating, and setting to 0 are performed in a loop in sequence according to the channel number until all the sub-I signals are obtained; for the sub-Q signal, the operations of setting to 0, holding, setting to 0, and negating are performed in a loop in sequence according to the channel number until all the sub-Q signals are obtained. For example, the sub-IF signal of the first channel is held to obtain the first sub-I signal, the sub-IF signal of the second channel is set to 0 to obtain the second sub-I signal, the sub-IF signal of the third channel is negated to obtain the third sub-I signal, the sub-IF signal of the fourth channel is set to 0 to obtain the fourth sub-I signal, and the sub-IF signal of the fifth channel is held again to obtain the fifth sub-I signal..., as shown in FIG. Figure 5 , which is a schematic diagram of a multi-phase digital orthogonal mixing solution provided in an embodiment of the present application.

[0041] In a possible implementation, after determining whether the acquisition module is working normally and whether the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, if it is determined that the acquisition module is not working normally, or the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is not a preset ratio, the acquisition module can be reconfigured through the FPGA module.

[0042] In a possible implementation, after the sub-IF signal corresponding to any channel is processed by the FPGA module using a preset multi-phase digital orthogonal mixing logic to obtain the sub-I signal and the sub-Q signal corresponding to the sub-IF signal, if the working channel of the sub-IF signal changes, the acquisition module is reconfigured through the FPGA module. That is, when the working channel changes, the acquisition module control logic of the FPGA module can reconfigure the internal registers of the clock chip, ADC chip, etc. through the control protocol. During this period, other parts of the device are suspended until the acquisition module works normally again and the frequency of the digital local oscillator signal of the current channel is fixed to three quarters or one quarter of the sampling rate of the ADC chip. Specific embodiment: Assuming that the sampling rate of the ADC chip is fs, the center frequency of the intermediate frequency signal is f, the frequency of the digital local oscillator signal is fc, and the time is t, the intermediate frequency signal is divided into n sub-intermediate frequency signals after being digitized. According to the existing multi-phase digital orthogonal mixing scheme, the kth sub-I signal can be expressed by the following formula (1): (1) The kth sub-Q signal is expressed using the following formula (2): (2) in, is the initial phase corresponding to the kth sub-signal.

[0044] make: (3) as well as, (4) in, is the sub-I signal corresponding to the k-th channel of the digitally controlled oscillator (NCO), It is the sub-Q signal corresponding to the kth channel of NCO.

[0045] Initialization configuration (let fc and fs satisfy the following relationship): (5) or, (6) Furthermore, according to formulas (3)-(6), we can get: (7) (8) Furthermore, according to formulas (1), (3) and (7), the sub-I signal corresponding to any sub-IF signal of the present application can be obtained: (9) Similarly, according to formulas (1), (4) and (8), the sub-Q signal corresponding to any sub-IF signal of the present application can be obtained: (10) In summary, compared with the prior art, the present application has the following advantages: (1) Low power consumption: The more sub-IF signals are separated, the more obvious the advantage of low power consumption is.

[0046] Specifically, on the one hand, since the logic implementation of multi-phase digital orthogonal mixing does not require a DDS core and a multiplier at all, the static power consumption caused by the DDS core and the multiplier is eliminated; On the other hand, since the sampling frequency of the ADC chip in different channels is configurable, and the number of sub-IF signals separated when the FPGA implements multi-phase digital orthogonal mixing is unchanged, the lower the center frequency of the IF signal, the lower the clock frequency of calculation and processing in the FPGA, thereby reducing the dynamic power consumption brought by the FPGA when performing digital signal processing. For example, the IF signal of a certain receiver is divided into three channels, the center frequency of the first channel is 5.625 GHz, the center frequency of the second channel is 2.25 GHz, and the center frequency of the third channel is 0.75 GHz. If the sampling frequency of the ADC chip is fixed to 7.5 GHz, and the number of separated sub-IF signals is fixed to 32, then, based on the existing multi-phase digital orthogonal mixing scheme, no matter which channel the receiver works in, the clock frequency of calculation and processing in the FPGA is 234.375 MHz; however, if the multi-phase digital orthogonal mixing scheme of the present application is adopted, then the sampling frequency of the second channel and the third channel will only reach 3 GHz, so that when the receiver works in the second channel and the third channel, the clock frequency of calculation and processing in the FPGA only needs to be 93.75 MHz.

[0047] (2) There is no quantization error and almost no processing delay.

[0048] Specifically, on one hand, as mentioned above, the multi-phase digital orthogonal mixing scheme of the present application does not need to use a DDS core to generate a digital local oscillator signal, and naturally there will be no quantization error, that is, the quantization error is fundamentally eliminated.

[0049] On the other hand, since the multi-phase digital orthogonal mixing scheme of the present application only has three operations of hold, reset and invert for each sub-IF signal, and in the FPGA, the logical implementation of these three operations is very simple (the hold operation only needs to assign the sub-IF signal directly to the corresponding sub-I signal or sub-Q signal; the reset operation only needs to assign the corresponding sub-I signal or sub-Q signal directly to the constant 0; the invert operation only needs to assign the inverse code of the sub-IF signal to the corresponding sub-I signal or sub-Q signal), therefore, compared with the calculation delay of dozens of clock cycles of the DDS core, the present application greatly improves the processing efficiency.

[0050] It can be seen that the multi-phase digital orthogonal mixing solution of the present application is very practical and has certain value for multi-phase digital orthogonal mixing processing of large-bandwidth intermediate frequency signals.

[0051] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0052] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A multi-phase digital quadrature mixing method, characterized in that: The method is applied to a multi-phase digital orthogonal mixing system including an acquisition module and an FPGA module, and includes: For any channel, the acquisition module is initialized and configured through the FPGA module; Determine whether the acquisition module works normally and whether the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio; wherein the preset ratio is three quarters or one quarter; If it is determined that the acquisition module is operating normally, and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, the sub-intermediate frequency signal corresponding to any channel is subjected to a preset multi-phase digital orthogonal mixing logic processing through the FPGA module to obtain a sub-I signal and a sub-Q signal corresponding to the sub-intermediate frequency signal; wherein the preset multi-phase digital orthogonal mixing logic processing only includes holding, setting to 0, and inverting.

2. The method according to claim 1, characterized in that The step of initializing the configuration of the acquisition module through the FPGA module includes: The clock chip and ADC chip of the acquisition module are initialized and configured through the acquisition module control logic of the FPGA module.

3. The method according to claim 2, characterized in that The step of initializing and configuring the clock chip and the ADC chip of the acquisition module through the acquisition module control logic of the FPGA module includes: Controlling the clock chip to generate a sampling clock through a control protocol in the acquisition module control logic; wherein the control protocol is determined according to the ADC chip used; The sampling frequency of the ADC chip is initialized and set according to the control protocol, the sampling clock and the center frequency of the sub-intermediate frequency signal of any channel.

4. The method according to claim 1, characterized in that If it is determined that the acquisition module is operating normally, and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, the step of performing a preset multi-phase digital orthogonal mixing logic process on the sub-intermediate frequency signal corresponding to any channel through the FPGA module to obtain a sub-I signal and a sub-Q signal corresponding to the sub-intermediate frequency signal includes: If it is determined that the acquisition module is operating normally and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, the digital orthogonal mixing logic of the FPGA module is used to perform preset multi-phase digital orthogonal mixing logic processing on the sub-intermediate frequency signal corresponding to any channel according to the number to obtain the sub-I signal and sub-Q signal corresponding to the sub-intermediate frequency signal.

5. The method according to claim 1, characterized in that After determining whether the acquisition module works normally and whether the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, the method further includes: If it is determined that the acquisition module does not work normally, or the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is not a preset ratio, the acquisition module is reconfigured through the FPGA module.

6. The method according to claim 1, characterized in that After performing preset multi-phase digital orthogonal mixing logic processing on the sub-IF signal corresponding to any one of the channels through the FPGA module to obtain a sub-I signal and a sub-Q signal corresponding to the sub-IF signal, the method further includes: If the working channel changes, the acquisition module is reconfigured through the FPGA module.

7. The method according to claim 1, characterized in that The sub-I signal is expressed by the following formula (1): （1） The sub-Q signal is expressed by the following formula (2): （2） in, is the sub-I signal corresponding to the k-th channel; is the sub-I signal corresponding to the k-th channel; f is the center frequency of the intermediate frequency signal; fc is the frequency of the digital local oscillator signal of the k-th channel; t is the time, is the initial phase corresponding to the kth sub-signal.

8. A multi-phase digital quadrature mixing system, characterized in that: The system comprises an acquisition module and an FPGA module; wherein the acquisition module is used to acquire intermediate frequency signals; and the FPGA module is responsible for controlling the acquisition module and multi-phase digital orthogonal mixing processing.

9. The system according to claim 8, characterized in that The acquisition module includes a clock chip and an ADC chip; wherein the clock chip is used to provide a stable sampling clock; and the ADC chip is used to acquire and convert the intermediate frequency signal according to the sampling clock.

10. The system according to claim 9, characterized in that The FPGA module includes an acquisition module control logic and a digital orthogonal mixing logic; wherein the acquisition module control logic is used to control each chip in the acquisition module through a control protocol, so that the acquisition module works normally and ensures that the center frequency of the output intermediate frequency signal data is fixed to three quarters or one quarter of the sampling rate of the ADC chip; the digital orthogonal mixing logic is used to perform preset multi-phase digital orthogonal mixing logic processing on the sub-intermediate frequency signals corresponding to each channel to obtain sub-I signals and sub-Q signals corresponding to each sub-intermediate frequency signal.

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