Oscillator with fuse trimming oscillation frequency

Abstract

The invention discloses an oscillator with a fuse trimming oscillation frequency, which belongs to the technical field of integrated circuits, and comprises two current sources, an NAND gate, a NOT gate, resistors R1 and R2, capacitors C1 and C2, two comparators, first to sixth PMOS (P-channel Metal Oxide Semiconductor) tubes and NMOS (N-channel Metal Oxide Semiconductor) tubes, and a fuse connected in parallel with the resistor R2, the first current source is connected with the resistor R1 and the resistor R2, generates voltage and inputs the voltage into the two comparators. The output current I2 of the second current source is input to the third PMOS tube and the fourth PMOS tube; the third PMOS tube is connected with a capacitor C1, and the fourth PMOS tube is connected with a capacitor C2; the capacitor C1 is charged by the current I2, the capacitor C2 is discharged when the capacitor C1 is charged through circulation, the capacitor C2 is charged when the capacitor C1 is discharged, and an oscillation signal is generated and output through the NOT gate. According to the oscillator provided by the invention, the frequency of the oscillator can be adjusted by fusing the built-in fuse wire after a chip is manufactured, so that the high-precision requirement of a system on the oscillation frequency is met.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an oscillator with a fuse for adjusting the oscillation frequency. Background Art

[0002] An oscillator is an electronic device that can generate a periodic signal through self-oscillation of the circuit without an external input signal. It plays a vital role in many electronic systems, such as clock generation, signal modulation, frequency synthesis, etc. With the continuous advancement of integrated circuit technology, the application of high-precision oscillators in digital and mixed-signal integrated circuits has become increasingly important.

[0003] However, due to non-ideal factors in the manufacturing process, such as slight differences in material properties and deviations in the manufacturing process, the actual oscillator frequency often deviates from the design value. This frequency deviation may cause the performance of the entire electronic system to deteriorate or even fail to meet the design requirements. Therefore, how to accurately adjust the oscillation frequency after chip manufacturing has become an urgent problem to be solved.

[0004] Traditional frequency adjustment methods usually rely on external components or complex circuit design, which not only increases system complexity and cost, but also may introduce additional noise and errors.

[0005] On the other hand, fuse trimming technology is a method of adjusting circuit parameters by setting fusible conductive connections (fuses) in the circuit and by fusing or retaining these connections after chip manufacturing. It has the advantages of high adjustment accuracy, simple operation, and little impact on circuit performance.

[0006] Therefore, by introducing fuse trimming technology into the oscillator design and integrating fuse elements inside the chip, the oscillation frequency can be accurately adjusted after the chip is actually manufactured, thereby improving the accuracy and reliability of the oscillator. Summary of the invention

[0007] In view of the problems in the background technology, the present invention provides an oscillator with fuse-adjustable oscillation frequency. After the chip is manufactured, the frequency of the oscillator is adjusted by blowing the built-in fuse to meet the system's high-precision requirements for the oscillation frequency.

[0008] The present invention adopts the following technical solution: an oscillator with fuse-adjusted oscillation frequency, comprising: a first current source, a second current source, a NAND gate NAND1, an invertor INV1, a resistor string, a capacitor C1, a capacitor C2, a first comparator CM1, a second comparator CM2, first to sixth PMOS tubes, first to sixth NMOS tubes, and a fuse.

[0009] The first current source and the second current source are both connected to a power source VCC. The other end of the first current source is connected to a resistor string, which includes resistors R1 and R2 connected in series, and a fuse and resistor R2 are connected in parallel.

[0010] The power source VCC outputs a current I1 through the first current source, and generates a voltage VC1 on the resistor string; the voltage VC1 is input to the negative input terminal of the first comparator CM1 and the second comparator CM2; one end of the capacitor C2 is grounded, and the other end is connected to the positive input terminal of the first comparator CM1, and a voltage A1 is generated at the output terminal of the first comparator CM1, and is input to the gate of the first NMOS tube NM1; one end of the capacitor C1 is grounded, and the other end is connected to the positive input terminal of the second comparator CM2, and a voltage B1 is generated at the output terminal of the second comparator CM2, and is input to the gate of the sixth NMOS tube NM6; the drain of the first NMOS tube NM1 generates a voltage A2, which is connected to the drain of the second NMOS tube NM2 and the drain of the second PMOS tube PM2; the drain of the sixth NMOS tube NM6 generates a voltage B2, which is connected to the drain of the fifth NMOS tube NM5 and the drain of the fifth PMOS tube PM5.

[0011] The power source VCC outputs a current I2 through the second current source, which is input into the source of the third PMOS tube PM3 and the source of the fourth PMOS tube PM4; the drain of the third PMOS tube PM3 is connected to the capacitor C1, the current I2 charges the capacitor C1, and a voltage A3 is generated between the third PMOS tube PM3 and the capacitor C1; the drain of the fourth PMOS tube PM4 is connected to the capacitor C2, and a voltage B3 is generated between the fourth PMOS tube PM4 and the capacitor C2.

[0012] When the voltage A3 is greater than the voltage VC1, the capacitor C1 stops charging, and the third NMOS tube NM3 turns on the capacitor C1 to discharge; the current I2 charges the capacitor C2, and when the voltage B3 is greater than the voltage VC1, the capacitor C2 stops charging; the fourth NMOS tube NM4 turns on the capacitor C2 to discharge, and the capacitor C1 is charged; the cycle is repeated in sequence, when the capacitor C1 is charged, the capacitor C2 is discharged, and when the capacitor C1 is discharged, the capacitor C2 is charged, and an oscillation signal is generated and output through the invertor INV1.

[0013] Preferably, in the resistor string, one end of the resistor R2 is connected to the resistor R1, and the other end is grounded; one end of the fuse is connected between the resistor R1 and the resistor R2, and the other end is connected between the resistor R2 and the ground, and the oscillator frequency is adjusted by blowing the fuse; When the fuse is not blown, the resistor R2 is equivalent to a short circuit, and the effective resistance value of the resistor string is the resistance value of the resistor R1; when the fuse is blown, the fuse is equivalent to an open circuit, and the effective resistance value is the sum of the resistance values ​​of the resistors R1 and R2.

[0014] Preferably, the source of the second PMOS transistor PM2 is connected to the power supply VCC, the gate is connected to the gate of the second NMOS transistor NM2, and the drain is connected to the drain of the second NMOS transistor NM2; The source of the fifth PMOS transistor PM5 is connected to the power supply VCC, and the gate is connected to the gate of the fifth NMOS transistor NM5 and then to the gate of the third NMOS transistor NM3, the voltage A2 and the gate of the third PMOS transistor PM3.

[0015] Preferably, the voltage A2 is input to the gate of the third PMOS transistor PM3 and the gate of the third NMOS transistor NM3, the source of the third PMOS transistor PM3 inputs the current I2, and the drain of the third PMOS transistor PM3 is connected to the capacitor C1 and the drain of the third NMOS transistor NM3; The voltage B2 is input to the gate of the fourth PMOS transistor PM4 and the gate of the fourth NMOS transistor NM4, the source of the fourth PMOS transistor PM4 inputs the current I2, and the drain of the fourth PMOS transistor PM4 is connected to the capacitor C2 and the drain of the fourth NMOS transistor NM3.

[0016] Preferably, the input terminal of the NAND gate NAND1 inputs the voltage A3 and the voltage B3, and the output terminal is connected to the gate of the first PMOS transistor PM1 and the gate of the sixth PMOS transistor PM6, and the first PMOS transistor PM1 and the sixth PMOS transistor PM6 are controlled by the NAND gate NAND1; The source of the first PMOS tube PM1 is connected to the power supply VCC, and the drain of the first PMOS tube is connected to the voltage A3 and the drain of the third NMOS tube NM3; the source of the sixth PMOS tube PM6 is connected to the power supply VCC, and the drain of the sixth PMOS tube is sequentially connected to the gate of the fourth PMOS tube PM4, the voltage B2 and the gate of the fourth NMOS tube NM4.

[0017] Preferably, when the current I2 charges the capacitor C1, the voltage A3 gradually increases. When the voltage A3 is greater than the voltage VC1, the voltage B1 at the output end of the second comparator CM2 is high, the sixth NMOS tube NM6 is turned on, and the voltage B2 is pulled down; the second PMOS tube PM2 is turned on, the second NMOS tube NM2 is turned off, and the voltage A2 is high; the third PMOS tube PM3 is turned off, and the current I2 stops charging the capacitor C1; the third NMOS tube NM3 is turned on, and the capacitor C1 is discharged.

[0018] Preferably, when the capacitor C1 is discharged, the fourth PMOS tube PM4 is turned on and the fourth NMOS tube NM4 is turned off, and the current I2 charges the capacitor C2, gradually increasing the voltage B3; when the voltage B3 is greater than the voltage VC1, the first comparator CM1 outputs a high voltage A1, the first NMOS tube NM1 is turned on, and the voltage A2 is pulled down; the fifth PMOS tube PM5 is turned on and the fifth NMOS tube NM5 is turned off, the voltage B2 is high, the fourth PMOS tube PM4 is turned off, and the current I2 stops charging the capacitor C2; the fourth NMOS tube NM4 is turned on, the capacitor C2 is discharged, the third PMOS tube PM3 is turned on and the third NMOS tube NM3 is turned off, and the current I2 charges the capacitor C1.

[0019] Preferably, sources of the first to sixth NMOS transistors are all grounded.

[0020] Preferably, the gate of the second PMOS transistor PM2, the gate of the second NMOS transistor NM2, the gate of the fourth PMOS transistor PM4 and the gate of the fourth NMOS transistor NM4 are all connected to the input end of the invertor INV1, and the output end of the invertor INV1 outputs the oscillation signal of the oscillator.

[0021] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects: 1. The oscillator of the present invention uses a fuse built into the chip. After the chip is manufactured, the frequency of the oscillator is adjusted by blowing the fuse, thereby meeting the system's high-precision requirements for the oscillation frequency.

[0022] 2. The present invention controls PMOS tubes PM1 and PM6 through NAND gate NAND1, thereby preventing voltages A3 and B3 from being overcharged and causing circuit function errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 An oscillator circuit diagram for adjusting the oscillation frequency of the fuse of the present invention; Figure 2 This is a timing waveform diagram of an oscillator whose oscillation frequency is adjusted by a fuse according to the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the application is further elaborated in detail below in conjunction with the accompanying drawings. The described embodiments are only a part of the embodiments involved in the present invention. All non-innovative embodiments of other researchers in the field on this embodiment belong to the protection scope of the present invention. At the same time, for the step numbering in the embodiment of the present invention, it is only set for the convenience of explanation, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0025] In one embodiment of the present invention, an oscillator with fuse-adjusted oscillation frequency, such as Figure 1 As shown, it includes: a first current source, a second current source, a NAND gate NAND1, an invertor INV1, a resistor string, a capacitor C1, a capacitor C2, a first comparator CM1, a second comparator CM2, first to sixth PMOS tubes, first to sixth NMOS tubes, and a fuse; The first current source and the second current source are both connected to a power source VCC. The other end of the first current source is connected to a resistor string, which includes resistors R1 and R2 connected in series. The fuse is connected in parallel to the resistor R2.

[0026] The power source VCC outputs a current I1 through the first current source, generating a voltage VC1 on the resistor string.

[0027] The negative input terminal of the first comparator CM1 is connected to the voltage VC1, the positive input terminal is connected to one end of the capacitor C2, and the other end of the capacitor C2 is grounded; the output terminal of the first comparator CM1 outputs the voltage A1.

[0028] The negative input terminal of the second comparator CM2 is connected to the voltage VC1 , the positive input terminal is connected to one end of the capacitor C1 , and the other end of the capacitor C1 is grounded; the output terminal of the second comparator CM2 outputs the voltage B1 .

[0029] The voltage A1 is input to the gate of the first NMOS transistor NM1 . The source of the first NMOS transistor NM1 is grounded. The drain generates a voltage A2 which is input to the drain of the second NMOS transistor NM2 and the drain of the second PMOS transistor PM2 .

[0030] The gate of the second NMOS transistor NM2 is connected to the gate of the second PMOS transistor PM2, the source of the second NMOS transistor NM2 is grounded, and the source of the second PMOS transistor PM2 is connected to the power supply VCC.

[0031] The voltage B1 is input to the gate of the sixth NMOS transistor NM6 . The source of the sixth NMOS transistor NM6 is grounded. The drain generates a voltage B2 which is input to the drain of the fifth NMOS transistor NM5 and the drain of the fifth PMOS transistor PM5 .

[0032] The gate of the fifth NMOS transistor NM5 is connected to the gate of the fifth PMOS transistor PM5 , the source of the fifth NMOS transistor NM5 is grounded, and the source of the fifth PMOS transistor PM5 is connected to the power supply VCC.

[0033] The power source VCC outputs a current I2 through the second current source, and inputs the current into the source of the third PMOS transistor PM3 and the source of the fourth PMOS transistor PM4.

[0034] The drain of the third PMOS transistor PM3 is connected to the capacitor C1, and the current I2 charges the capacitor C1, so that a voltage A3 is generated between the third PMOS transistor PM3 and the capacitor C1.

[0035] The gate of the third PMOS transistor PM3 is connected to the gate of the third NMOS transistor NM3 , the source of the third NMOS transistor NM3 is grounded, and the drain of the third NMOS transistor NM3 is connected to the drain of the first PMOS transistor PM1 .

[0036] The drain of the fourth PMOS transistor PM4 is connected to the capacitor C2, and a voltage B3 is generated between the fourth PMOS transistor PM4 and the capacitor C2; the gate of the fourth PMOS transistor PM4 is connected to the gate of the fourth NMOS transistor NM4.

[0037] The two input terminals of the NAND gate NAND1 are respectively input with voltage A3 and voltage B3, and the output terminal is connected with the gate of the first PMOS transistor PM1 and the gate of the sixth PMOS transistor PM6, and the first PMOS transistor PM1 and the sixth PMOS transistor PM6 are controlled by the NAND gate NAND1.

[0038] The source of the first PMOS tube PM1 is connected to the power supply VCC, and the drain of the first PMOS tube is connected to the voltage A3 and the drain of the third NMOS tube NM3; the source of the sixth PMOS tube PM6 is connected to the power supply VCC, and the drain of the sixth PMOS tube is sequentially connected to the gate of the fourth PMOS tube PM4, the voltage B2 and the gate of the fourth NMOS tube NM4.

[0039] The gate of the second PMOS transistor PM2, the gate of the second NMOS transistor NM2, the drain of the sixth PMOS transistor PM6, the gate of the fourth PMOS transistor PM4 and the gate of the fourth NMOS transistor NM4 are all connected to the input end of the invertor INV1, and the output end of the invertor INV1 outputs the oscillation signal OSC_OUT of the oscillator.

[0040] The timing waveform of the oscillator is as follows Figure 2 As shown, the specific controls are as follows: In the initial state, the power supply VCC is 0, and the voltage across capacitors C1 and C2 is also 0.

[0041] After the power supply VCC is powered on, the first current source outputs current I1 to generate voltage VC1 on the resistor string, and the second current source outputs current I2. Current I2 charges capacitor C1 through the third PMOS transistor PM3 to gradually increase voltage A3.

[0042] When the voltage A3 is greater than the voltage VC1, the second comparator CM2 outputs a high voltage B1, the sixth NMOS tube NM6 is turned on, and the voltage B2 is pulled down; the second PMOS tube PM2 is turned on, the second NMOS tube NM2 is turned off, the voltage A2 is high, the third PMOS tube PM3 is turned off, and the current stops charging the capacitor C1.

[0043] The third NMOS tube NM3 is turned on, and the capacitor C1 is discharged. Meanwhile, the fourth PMOS tube PM4 is turned on, and the fourth NMOS tube NM4 is turned off. The current charges the capacitor C2, and the voltage B3 is gradually increased.

[0044] When the voltage B3 is greater than the voltage VC1, the first comparator CM1 outputs a high voltage A1, the first NMOS tube NM1 is turned on, and the voltage A2 is pulled down; the fifth PMOS tube PM5 is turned on, the fifth NMOS tube NM5 is turned off, the voltage B2 is high, the fourth PMOS tube PM4 is turned off, and the current stops charging the capacitor C2.

[0045] The fourth NMOS tube NM4 is turned on, and the capacitor C2 is discharged. At the same time, the third PMOS tube PM3 is turned on, and the third NMOS tube NM3 is turned off. The current charges the capacitor C1, and the voltage A3 is gradually increased.

[0046] In this cycle, when capacitor C1 is discharged, capacitor C2 is charged; when capacitor C1 is charged, capacitor C2 is discharged, and an oscillation signal is generated and output through INV1.

[0047] Furthermore, in this embodiment, the voltages A3 and B3 are input into the NAND gate NAND1 to control the first PMOS transistor PM1 and the sixth PMOS transistor PM6 to prevent the voltages A3 and B3 from being overcharged and causing circuit function errors.

[0048] In particular, the frequency of the oscillator in this embodiment is: ; In the formula, F is the oscillation frequency, T is the charge and discharge time of the capacitor, C is the capacitance value, VC 1 is voltage, I 1 is the current of the first current source, I 2 is the current of the second current source, R is the resistance value of the resistor string.

[0049] In this embodiment, the resistance of the fuse is relatively small compared to the resistance and can be ignored. When the fuse is not blown, the resistor R2 is equivalent to a short circuit, and the resistance of the resistor string is the resistance of R1; after the fuse is blown, the fuse is equivalent to an open circuit, and the resistance of the resistor string is the sum of the resistances of R1 and R2. Therefore, the oscillator frequency can be adjusted by blowing the fuse.

[0050] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An oscillator with fuse-adjusted oscillation frequency, characterized in that: include: A first current source, a second current source, a NAND gate NAND1, an invertor INV1, a resistor string, a capacitor C1, a capacitor C2, a first comparator CM1, a second comparator CM2, first to sixth PMOS transistors, first to sixth NMOS transistors, and a fuse; One end of the first current source and the second current source are both connected to a power source VCC, and the other end of the first current source is connected to a resistor string, wherein the resistor string includes resistors R1 and R2 connected in series, and a fuse and resistor R2 are connected in parallel; The power source VCC outputs a current I1 through the first current source, generating a voltage VC1 on the resistor string; the voltage VC1 is input to the negative input terminal of the first comparator CM1 and the second comparator CM2; one end of the capacitor C2 is grounded and the other end is connected to the positive input terminal of the first comparator CM1, generating a voltage A1 at the output terminal of the first comparator CM1, and inputting the gate of the first NMOS tube NM1; one end of the capacitor C1 is grounded and the other end is connected to the positive input terminal of the second comparator CM2, generating a voltage B1 at the output terminal of the second comparator CM2, and inputting the gate of the sixth NMOS tube NM6; the drain of the first NMOS tube NM1 generates a voltage A2, which is connected to the drain of the second NMOS tube NM2 and the drain of the second PMOS tube PM2; the drain of the sixth NMOS tube NM6 generates a voltage B2, which is connected to the drain of the fifth NMOS tube NM5 and the drain of the fifth PMOS tube PM5; The power source VCC outputs a current I2 through the second current source, and inputs the source of the third PMOS transistor PM3 and the source of the fourth PMOS transistor PM4; the drain of the third PMOS transistor PM3 is connected to the capacitor C1, and the current I2 charges the capacitor C1, and a voltage A3 is generated between the third PMOS transistor PM3 and the capacitor C1; the drain of the fourth PMOS transistor PM4 is connected to the capacitor C2, and a voltage B3 is generated between the fourth PMOS transistor PM4 and the capacitor C2; When the voltage A3 is greater than the voltage VC1, the capacitor C1 stops charging, and the third NMOS tube NM3 turns on the capacitor C1 to discharge; the current I2 charges the capacitor C2, and when the voltage B3 is greater than the voltage VC1, the capacitor C2 stops charging; the fourth NMOS tube NM4 turns on the capacitor C2 to discharge, and the capacitor C1 is charged; the cycle is repeated in sequence, when the capacitor C1 is charged, the capacitor C2 is discharged, and when the capacitor C1 is discharged, the capacitor C2 is charged, and an oscillation signal is generated and output through the invertor INV1.

2. The oscillator with fuse-adjusted oscillation frequency according to claim 1, characterized in that: In the resistor string, one end of the resistor R2 is connected to the resistor R1, and the other end is grounded; one end of the fuse is connected between the resistor R1 and the resistor R2, and the other end is connected between the resistor R2 and the ground, and the oscillator frequency is adjusted by blowing the fuse; When the fuse is not blown, the resistor R2 is equivalent to a short circuit, and the effective resistance value of the resistor string is the resistance value of the resistor R1; when the fuse is blown, the fuse is equivalent to an open circuit, and the effective resistance value of the resistor string is the sum of the resistance values ​​of the resistors R1 and R2.

3. The oscillator with fuse-adjusted oscillation frequency according to claim 1, characterized in that: The source of the second PMOS transistor PM2 is connected to the power supply VCC, the gate is connected to the gate of the second NMOS transistor NM2, and the drain is connected to the drain of the second NMOS transistor NM2; The source of the fifth PMOS transistor PM5 is connected to the power supply VCC, and the gate is connected to the gate of the fifth NMOS transistor NM5 and then to the gate of the third NMOS transistor NM3, the voltage A2 and the gate of the third PMOS transistor PM3.

4. The oscillator with fuse-adjusted oscillation frequency according to claim 3, characterized in that: The voltage A2 is input to the gate of the third PMOS transistor PM3 and the gate of the third NMOS transistor NM3, the source of the third PMOS transistor PM3 inputs the current I2, and the drain of the third PMOS transistor PM3 is connected to the capacitor C1 and the drain of the third NMOS transistor NM3; The voltage B2 is input to the gate of the fourth PMOS transistor PM4 and the gate of the fourth NMOS transistor NM4, the source of the fourth PMOS transistor PM4 inputs the current I2, and the drain of the fourth PMOS transistor PM4 is connected to the capacitor C2 and the drain of the fourth NMOS transistor NM3.

5. The oscillator with fuse-adjusted oscillation frequency according to claim 4, characterized in that: The two input ends of the NAND gate NAND1 are respectively input with voltage A3 and voltage B3, and the output end is connected with the gate of the first PMOS transistor PM1 and the gate of the sixth PMOS transistor PM6, and the first PMOS transistor PM1 and the sixth PMOS transistor PM6 are controlled by the NAND gate NAND1; The source of the first PMOS tube PM1 is connected to the power supply VCC, and the drain of the first PMOS tube is connected to the voltage A3 and the drain of the third NMOS tube NM3; the source of the sixth PMOS tube PM6 is connected to the power supply VCC, and the drain of the sixth PMOS tube is sequentially connected to the gate of the fourth PMOS tube PM4, the voltage B2 and the gate of the fourth NMOS tube NM4.

6. The oscillator with fuse-adjusted oscillation frequency according to claim 5, characterized in that: When the current I2 charges the capacitor C1, the voltage A3 gradually increases. When the voltage A3 is greater than the voltage VC1, the voltage B1 at the output end of the second comparator CM2 is high, the sixth NMOS tube NM6 is turned on, and the voltage B2 is pulled down; the second PMOS tube PM2 is turned on, the second NMOS tube NM2 is turned off, and the voltage A2 is high; the third PMOS tube PM3 is turned off, and the current I2 stops charging the capacitor C1; the third NMOS tube NM3 is turned on, and the capacitor C1 is discharged.

7. The oscillator with fuse-adjusted oscillation frequency according to claim 6, characterized in that: When the capacitor C1 is discharged, the fourth PMOS tube PM4 is turned on and the fourth NMOS tube NM4 is turned off, and the current I2 charges the capacitor C2, gradually increasing the voltage B3; when the voltage B3 is greater than the voltage VC1, the first comparator CM1 outputs a high voltage A1, the first NMOS tube NM1 is turned on, and the voltage A2 is pulled down; the fifth PMOS tube PM5 is turned on and the fifth NMOS tube NM5 is turned off, the voltage B2 is high, the fourth PMOS tube PM4 is turned off, and the current I2 stops charging the capacitor C2; the fourth NMOS tube NM4 is turned on, the capacitor C2 is discharged, the third PMOS tube PM3 is turned on and the third NMOS tube NM3 is turned off, and the current I2 charges the capacitor C1.

8. The oscillator with fuse-adjusted oscillation frequency according to claim 5, characterized in that: The sources of the first to sixth NMOS tubes are all grounded.

9. The oscillator with fuse-adjusted oscillation frequency according to claim 5, characterized in that: The gate of the second PMOS transistor PM2, the gate of the second NMOS transistor NM2, the gate of the fourth PMOS transistor PM4, and the gate of the fourth NMOS transistor NM4 are all connected to the input end of the invertor INV1, and the output end of the invertor INV1 outputs the oscillation signal of the oscillator.

10. The oscillator with fuse-adjusted oscillation frequency according to claim 9, characterized in that: The frequency of the oscillator is: ； In the formula, F is the oscillation frequency, T is the charge and discharge time of the capacitor, C is the capacitance value, VC1 is the voltage, I 1 is the current of the first current source, I 2 is the current of the second current source, R is the resistance value of the resistor string.

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