A high-precision MEMS clock taming method based on deep learning

Abstract

The present application discloses a high-precision MEMS clock training method and circuit based on deep learning. The method obtains a satellite second pulse signal and a 1Hz clock signal, and obtains a phase difference digital signal based on the satellite second pulse signal and the 1Hz clock signal; inputs the phase difference digital signal into a preset clock training deep learning network to obtain a predicted time-frequency signal; if the fluctuation value of the satellite second pulse signal is greater than a preset threshold, the time-frequency signal is used to control the MEMS resonator to generate a 1Hz clock signal; otherwise, the MEMS resonator is controlled to generate a 1Hz clock signal based on the phase difference digital signal. After judging that the fluctuation value of the satellite second pulse signal exceeds the threshold, the present application controls the MEMS resonator to generate a clock signal according to the predicted time-frequency signal or the phase difference digital signal, thereby solving the technical problems of high precision cost and large temperature influence of existing high-precision clock synchronization devices.

Description

Technical Field

[0001] The present application relates to the field of clock synchronization technology, and in particular to a high-precision MEMS clock taming method and circuit based on deep learning. Background Art

[0002] In recent years, the demand for high-precision clock synchronization devices in fields such as communications, power, metering, aerospace, and defense has increased, placing increasingly stringent demands on the accuracy and stability of time and frequency reference sources. Accurate clock sources are essential for the normal operation of many critical infrastructure systems in these fields.

[0003] Currently, the most common technical solution is to directly obtain accurate time as a reference using a Beidou or Global Positioning System (GPS) receiver. This is followed by continuous tracking, observation, and adjustment of the clock under test to achieve clock synchronization. The current mainstream solution uses a chip atomic clock + field-programmable gate array (FPGA) + quartz crystal oscillator + peripheral circuitry to achieve high-precision time and frequency signals. This approach has the following drawbacks: Because the reference signal obtained by the satellite receiver has large random jitter per second (typically on the order of tens of nanoseconds), long-term observation and processing (up to an hour) is required to achieve high-precision time and frequency training, significantly impacting work efficiency. The chip atomic clock + field-programmable gate array (FPGA) solution is expensive and costly, and the quartz crystal oscillator is significantly affected by temperature, resulting in large errors in the final output time and frequency signal. In remote areas, indoors, underground, and other locations with poor satellite signal strength, the clock training system struggles to operate effectively, resulting in poor accuracy or even failure to output time and frequency signals. Summary of the Invention

[0004] The main purpose of this application is to provide a high-precision MEMS clock taming method and circuit based on deep learning, aiming to solve the technical problems of high precision cost and large temperature influence of existing high-precision clock synchronization devices.

[0005] To achieve the above objectives, the present application provides a high-precision MEMS clock taming method based on deep learning, comprising:

[0006] Acquire a satellite second pulse signal and a 1 Hz clock signal, and obtain a phase difference digital signal based on the satellite second pulse signal and the 1 Hz clock signal; input the phase difference digital signal into a preset clock taming deep learning network to obtain a predicted time-frequency signal; if it is determined that the fluctuation value of the satellite second pulse signal is greater than a preset threshold, use the time-frequency signal to control the MEMS resonator to generate a 1 Hz clock signal; otherwise, control the MEMS resonator to generate a 1 Hz clock signal based on the phase difference digital signal, wherein the preset clock taming deep learning network includes an input layer, a pattern layer, a summation layer, and an output layer connected in sequence.

[0007] Optionally, each neuron in the pattern layer is a radial basis neuron, and the activation function expression of the radial basis neuron is:

[0008]

[0009] Among them, X n represents the nth input sample, c j represents the center of the jth radial basis neuron, σ represents the variance of the Gaussian kernel function;

[0010] Optionally, the summation layer includes a first group of neurons and a second group of neurons; wherein the input data of the first group of neurons is the output vector of each neuron in the pattern layer, and the output data is the sum value S of each output vector nk The input data of the second group of neurons is the output vector of each neuron in the pattern layer, and the output data is the weighted sum value S of each output vector Tn .

[0011] Optionally, the input data of each neuron in the output layer is the sum value S nk and the weighted sum S Tn , the output data is Where k is the label of the output layer neuron, n = 1, 2, ···, N, k = 1, 2, ···, K, N is the total number of training samples, and K is the total number of output layer neurons.

[0012] In addition, to achieve the above-mentioned purpose, the present application also provides a high-precision MEMS clock taming circuit based on deep learning, including: a GNSS satellite receiver for receiving a satellite second pulse signal; a MEMS oscillation circuit for generating an oscillation signal; a frequency divider, communicatively connected to the MEMS oscillation circuit, the frequency divider for dividing the oscillation signal to obtain a 1Hz clock signal; a phase detector, communicatively connected to the GNSS satellite receiver and the frequency divider, respectively, the phase detector inputs the 1Hz clock signal and the satellite second pulse signal, and outputs a first phase difference analog signal; an analog-to-digital converter, communicatively connected to the phase detector, the analog-to-digital converter is used to perform analog-to-digital conversion on the first phase difference digital signal to obtain a phase difference digital signal; a first digital-to-analog converter, communicatively connected to the analog-to-digital converter, the first digital-to-analog converter is used to perform analog-to-digital conversion on the phase difference digital signal to obtain to a second phase difference analog signal; a deep learning module, communicatively connected to the analog-to-digital converter, the deep learning module is used to process the phase difference digital signal according to the high-precision MEMS clock taming method based on deep learning to obtain a predicted time-frequency signal; a second digital-to-analog converter, communicatively connected to the deep learning module, the second digital-to-analog converter is used to perform digital-to-analog conversion on the predicted time-frequency signal to obtain an analog time-frequency signal; an FPGA, the input end of which is communicatively connected to the GNSS satellite receiver, the second digital-to-analog converter and the first digital-to-analog converter, and the output end of which is communicatively connected to the MEMS resonator, the FPGA is used to determine that the generated 1Hz clock signal is greater than a preset threshold, then control the MEMS resonator to generate a 1Hz clock signal according to the analog time-frequency signal; otherwise, control the MEMS resonator to generate a 1Hz clock signal according to the second phase difference analog signal.

[0013] Optionally, the MEMS oscillation circuit includes: a charge pump bias circuit, a MEMS resonator, a maintenance electric phase-locked loop circuit and a drive circuit that are communicatively connected in sequence, the output end of the drive circuit is feedback-communicatively connected to the phase-locked loop circuit, the input end of the drive circuit is also communicatively connected to the output end of the I / O circuit, the input end of the I / O circuit is also communicatively connected to the first signal input end, the output end of the I / O circuit is also communicatively connected to the input end of the OTP register, the output end of the OTP register is communicatively connected to the input end of the temperature control circuit, the input end of the temperature control circuit is also communicatively connected to the temperature acquisition circuit, and the output end of the temperature control circuit is also communicatively connected to the phase-locked loop circuit; wherein the charge pump bias circuit is used to output an electric field or current; the MEMS resonator is composed of a micro-cantilever beam, a suspended mass block or a thin film, and is used to generate a mechanical natural frequency using the micro-cantilever beam, the suspended mass block or the thin film according to the electric field or the current applied by the charge pump bias circuit. vibrate, and transmit the mechanical vibration to the maintaining circuit to form a stable oscillation signal; the sampling and holding circuit is used to sample the stable oscillation signal to obtain the phase of the stable oscillation signal, and output the phase of the stable oscillation signal; the phase-locked loop circuit is used to generate a target clock signal according to the phase synchronization of the stable oscillation signal, and the phase-locked loop circuit is also used to receive the temperature analog signal output by the temperature control circuit to perform temperature compensation on the phase-locked loop circuit; the temperature control circuit is used to generate a temperature analog signal according to the temperature collected by the temperature acquisition circuit 1029 of the received temperature compensation signal; the driving circuit is used to amplify the target clock signal output by the phase-locked loop circuit and output a clock signal; the OTP register is used to receive the signal output by the I / O circuit and output the temperature compensation signal; the I / O circuit is used to receive an enable signal / clock pulse signal, and send the enable signal / the clock pulse signal to the driving circuit and the OTP register.

[0014] Optionally, the deep learning module includes: an acquisition circuit for acquiring a satellite second pulse signal and a 1Hz clock signal, and obtaining a phase difference digital signal based on the satellite second pulse signal and the 1Hz clock signal; a clock taming deep learning network for processing the input phase difference digital signal and outputting a predicted time-frequency signal; a judgment circuit for judging that the fluctuation value of the satellite second pulse signal is greater than a preset threshold, then controlling the MEMS resonator to generate a 1Hz clock signal according to the time-frequency signal; otherwise, controlling the MEMS resonator to generate a 1Hz clock signal according to the phase difference digital signal; wherein, the clock taming deep learning network includes an input layer, a pattern layer, a summation layer and an output layer connected in sequence.

[0015] Optionally, the pattern layer is used to process input data using radial basis neurons to obtain an output vector, wherein the activation function expression of the radial basis neurons is:

[0016]

[0017] Where, X n represents the nth input sample, c j represents the center of the jth radial basis neuron, σ represents the variance of the Gaussian kernel function;

[0018] Optionally, the summation layer includes a first group of neurons and a second group of neurons; wherein the first group of neurons is used to sum the output vector to obtain a sum value S nk The second group of neurons is used to perform weighted summation on each of the output vectors to obtain a weighted sum value S Tn .

[0019] Optionally, each neuron in the output layer is used to calculate the sum of the input values ​​S nk and the weighted sum S Tn Processing is performed according to the preset second formula to output the predicted time-frequency signal, wherein the preset second formula is Where k is the number of neurons in the output layer, n = 1, 2, ···, N, k = 1, 2, ···, K, N is the total number of training samples, K is the total number of neurons in the output layer, y nk is the predicted time-frequency signal.

[0020] An embodiment of the present application proposes a high-precision MEMS clock training method and circuit based on deep learning, which obtains a satellite second pulse signal and a 1Hz clock signal, and obtains a phase difference digital signal based on the satellite second pulse signal and the 1Hz clock signal; inputs the phase difference digital signal into a preset clock training deep learning network to obtain a predicted time-frequency signal; determines that the fluctuation value of the satellite second pulse signal is greater than a preset threshold, then uses the time-frequency signal to control the MEMS resonator to generate a 1Hz clock signal; otherwise, controls the MEMS resonator to generate a 1Hz clock signal based on the phase difference digital signal, wherein the preset clock training deep learning network includes an input layer, a pattern layer, a summation layer and an output layer connected in sequence. After determining that the fluctuation value of the satellite second pulse signal exceeds the threshold, the present application uses the time-frequency signal to control the MEMS resonator to generate a 1Hz clock signal; otherwise, uses the phase difference digital signal to control the MEMS resonator to generate a 1Hz clock signal, thereby providing an alternative solution and solving the technical problems of high precision cost and large temperature influence of existing high-precision clock synchronization devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1A flowchart illustrating an embodiment of a high-precision MEMS clock taming method based on deep learning provided by this application;

[0022] Figure 2 A schematic diagram of an embodiment of a high-precision MEMS clock taming method based on deep learning provided by this application;

[0023] Figure 3 A structural block diagram of an embodiment of a high-precision MEMS clock taming circuit based on deep learning provided by this application;

[0024] Figure 4 This is a structural block diagram of a MEMS oscillation circuit provided in an embodiment of a high-precision MEMS clock taming circuit based on deep learning in this application.

[0025] The realization of the objectives, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0026] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0027] See also Figure 1 The present application provides a high-precision MEMS clock taming method based on deep learning. The method can be executed by a controller and may include the following execution steps:

[0028] S10, obtaining a satellite second pulse signal and a 1 Hz clock signal, and obtaining a phase difference digital signal based on the satellite second pulse signal and the 1 Hz clock signal;

[0029] S20, inputting the phase difference digital signal into a preset clock taming deep learning network to obtain a predicted time-frequency signal;

[0030] S30. If the fluctuation value of the satellite second pulse signal is determined to be greater than a preset threshold, the time-frequency signal is used to control the MEMS resonator to generate a 1Hz clock signal. Otherwise, the MEMS resonator is controlled to generate a 1Hz clock signal based on the phase difference digital signal. The preset clock taming deep learning network includes an input layer, a pattern layer, a summation layer, and an output layer connected in sequence.

[0031] Figure 2This is a schematic diagram of the high-precision MEMS clock taming method based on deep learning provided by the present application. Compared with the previous method, this method has an additional satellite signal access step. The present invention predicts the satellite second pulse signal to obtain a predicted time-frequency signal, and controls the MEMS resonator to generate a 1Hz clock signal according to the predicted time-frequency signal or the phase difference digital signal based on whether the fluctuation range of the satellite second pulse signal exceeds the threshold. This can ensure the short-term and long-term stability of the system output frequency, and can also ensure that in areas where the satellite signal is poor, the high-precision MEMS clock taming method based on deep learning proposed in this application can also efficiently achieve high-precision time-frequency signal output. The present invention introduces a deep learning algorithm to predict the time-frequency signal, so that the unstable time-frequency signal can reach stability and preset accuracy in a timely manner, thereby improving the efficiency and accuracy of the prediction of the present invention.

[0032] In an embodiment of the present application, a clock taming deep learning network may include an input layer, a pattern layer, a summation layer, and an output layer. Each neuron in the pattern layer is a radial basis neuron, and the activation function expression of the radial basis neuron is:

[0033]

[0034] Among them, X n represents the nth input sample, c j Represents the center of the jth radial basis neuron, σ represents the variance of the Gaussian kernel function; the summation layer performs weighted summation on the output results of all pattern layers; the output of the output layer neuron is Where k represents the kth output neuron, n = 1, 2, ···, N, k = 1, 2, ···, K, N is the total number of training samples, and K is the total number of neurons.

[0035] Specifically, the present application adopts a generalized regression neural network as a clock taming deep learning network. It should be noted that the clock taming deep learning network can also be a DBN (Deep Belief Network) deep belief network, a CNN (Convolution Neural Networks) convolutional neural network, an RNN (Recurrent Neural Network) recursive neural network, etc. Other deep learning networks are not included in the scope of this application. The generalized regression neural network algorithm execution process can specifically include the following processes: Data preparation: Acquire the time-frequency signal data set and perform standardization and normalization preprocessing steps on the data. Data processing: Perform generalized regression neural network calculations. Iterative training: Repeat the generalized regression neural network calculation process until the maximum number of iterations is reached or the loss function converges. The generalized regression neural network is specifically as follows: The generalized regression neural network has four layers of networks, namely the input layer, the pattern layer, the summation layer and the output layer.

[0036] Among them, the dimension M of the input vector in the training sample in the input layer is equal to the number of neurons, and the training set data is directly passed to the pattern layer.

[0037] The pattern layer neuron is a nonlinear function, and its neurons are radial basis neurons, which receive the output vector x of the input layer. n =(x n1 ,x n2 ,…,x nM ) T , that is, the input vector of the neuron (where n represents the nth training sample) and then calculate the input vector X n The Euclidean distance dist between the neuron and the center vector, the center vector is c j =(c j1 ,c j2 ,…,c jM )(where j represents the jth neuron).

[0038]

[0039] Finally, the distance dist between the input variable and the weight is used as the independent variable, multiplied by the threshold b, and then transmitted to the activation function of the neuron, that is, the transfer function. The radial basis function refers to the activation function of the radial basis neuron, and the expression of the activation function is:

[0040] R(n)=e -n2

[0041] The threshold b is used to adjust the sensitivity of the neuron. However, the radial basis function commonly used in radial basis neurons is the Gaussian kernel function, so the activation function of the radial basis neuron can be expressed as:

[0042]

[0043] Among them, X n represents the nth input sample; c j represents the center of the jth radial basis neuron; σ represents the variance of the Gaussian kernel function, that is, the smoothing factor. Then the output value of the jth neuron of the nth training sample input is P nj =R(X n -c j ).

[0044] In GRNN, some parameters of the pattern layer neurons are set in the following rules. First, the number of neurons in this layer is equal to the number of training samples N; second, Finally, σ is set manually when the network is established. The output vector of the pattern layer is:

[0045] P n =(Pn1 ,P n2 ,…,P nN ) T ,n=1,2,…,N,

[0046] Where n represents the nth training sample.

[0047] The summation layer includes two different types of neurons. One type of neuron performs arithmetic summation on the outputs of all pattern layer neurons, and its output is:

[0048]

[0049] The other type of neurons performs weighted summation of the outputs of all pattern layer neurons. The connection weight of this type of neurons is y jk , is the kth element in the jth output vector in the training sample. Its output is:

[0050]

[0051] Where n represents the training sample, k represents the summation neuron, n = 1, 2, ···, N, k = 1, 2, ···, K.

[0052] The number of neurons in the output layer is equal to the dimension K of the output vector in the learning sample. The output of each output layer neuron is:

[0053]

[0054] Where k represents the kth output neuron, n = 1, 2, ···, N, k = 1, 2, ···, K.

[0055] See also Figure 3On the basis of the above embodiments, the present application further provides a high-precision MEMS clock taming circuit based on deep learning, including a GNSS satellite receiver 101, a MEMS oscillator circuit 102, a frequency divider 103, a phase detector 104, an analog-to-digital converter 105, a first digital-to-analog converter 106, a deep learning module 107, a second digital-to-analog converter 108 and an FPGA 109, wherein the GNSS satellite receiver 101 is used to receive a satellite second pulse signal; the MEMS oscillator circuit 102 is used to generate an oscillation signal; the frequency divider 103 is communicatively connected to the MEMS oscillator circuit 102, and the frequency divider 103 is used to divide the oscillation signal to obtain a 1 Hz clock signal; the phase detector 104 is communicatively connected to the GNSS satellite receiver 101 and the frequency divider 103, and the phase detector 104 is used to calculate a first phase difference analog signal between the 1 Hz clock signal and the satellite second pulse signal; the analog-to-digital converter 105 is communicatively connected to the phase detector 104, and the analog-to-digital converter 105 is used to perform analog-to-digital conversion on the first phase difference digital signal to obtain a phase difference digital signal; the first A digital-to-analog converter 106 is communicatively connected to the analog-to-digital converter 105, and the first digital-to-analog converter 106 is used to perform analog-to-digital conversion on the phase difference digital signal to obtain a second phase difference analog signal; a deep learning module 107 is communicatively connected to the analog-to-digital converter 105, and the deep learning module 107 is used to process the phase difference digital signal using a high-precision MEMS clock training method based on deep learning to obtain a predicted time-frequency signal; a second digital-to-analog converter 108 is communicatively connected to the deep learning module 107, and the second digital-to-analog converter 108 is used to perform digital-to-analog conversion on the predicted time-frequency signal to obtain an analog time-frequency signal; an FPGA 109 has input ends communicatively connected to the GNSS satellite receiver 101, the second digital-to-analog converter 108, and the first digital-to-analog converter 106, respectively, and an output end communicatively connected to the MEMS resonator, and the FPGA 109 is used to determine whether the generated 1 Hz clock signal is greater than a preset threshold, and then control the MEMS resonator to generate a 1 Hz clock signal according to the analog time-frequency signal; otherwise, control the MEMS resonator to generate a 1 Hz clock signal using the second phase difference analog signal.

[0056] The high-precision MEMS clock taming circuit based on deep learning can perform the high-precision MEMS clock taming method based on deep learning according to the following steps:

[0057] S100 : The GNSS satellite receiver 101 receives 1PPS satellite signals.

[0058] S101 , the field programmable gate array FPGA 109 divides the frequency of the signal generated by the MEMS oscillation circuit 102 to generate a 1 Hz clock signal.

[0059] S102 , the field programmable gate array FPGA 109 performs a phase comparison between the 1 Hz clock signal and the 1PPS signal received by the GNSS satellite receiver 101 in the phase detector 104 to obtain a phase difference.

[0060] S103 , the analog-to-digital converter 105 converts the phase difference into a digital signal A and transmits it to the first digital-to-analog converter 106 .

[0061] S104, the first digital-to-analog converter 106 outputs analog signal A, and the field programmable logic gate array FPGA109 processes the analog signal A to obtain a voltage-controlled signal, and uses the voltage-controlled signal to control the frequency of the MEMS oscillation circuit 102 to form a phase-locked loop, so that the 1 Hz signal frequency generated by the MEMS oscillation circuit 102 gradually stabilizes within a preset range, thereby obtaining a second pulse that meets the preset conditions.

[0062] S105. In another branch, the deep learning module 107 in the controller uses a deep learning algorithm to predict the digital signal A to obtain a digital signal B, converts the digital signal B into an analog signal B through the second digital-to-analog converter 108, processes the analog signal B through the field programmable gate array FPGA109 to obtain a voltage-controlled signal, and controls the frequency of the MEMS oscillation circuit 102 through the voltage-controlled signal.

[0063] S106. Use the field programmable gate array FPGA109 to detect the satellite signal. If the 1PPS satellite signal fluctuates significantly and the fluctuation exceeds a preset threshold, the MEMS oscillation circuit 102 is controlled to generate a time-frequency signal based on the predicted voltage signal. If the satellite signal does not fluctuate significantly, the voltage-controlled signal output by the satellite signal through the phase-locked loop is used to control the MEMS resonator to generate a time-frequency signal.

[0064] In summary, the high-precision MEMS clock taming circuit based on deep learning proposed in this application avoids the prior art solution of chip atomic clock + MCU + quartz crystal oscillator + peripheral circuit, and adopts the field programmable logic gate array FPGA + MEMS resonator + peripheral circuit solution, which reduces costs, reduces the physical size of the system, and reduces the impact of temperature on the oscillator. This application uses deep learning algorithms to predict time-frequency signals and process unstable time-frequency signals, thereby improving the efficiency and accuracy of the present invention's predictions. This application predicts satellite signals while ensuring the short-term and long-term stability of the system's output frequency, allowing the system to efficiently achieve high-precision time-frequency signal output even in areas with poor satellite signals.

[0065] See also Figure 4In an embodiment of the present application, the MEMS oscillation circuit 102 includes: an electrical first data oscillator 10204, a voltage divider 10201, a MEMS resonator 10202, a transimpedance amplifier 10205, an analog-to-digital converter 10206, a voltage amplitude control circuit and a phase-locked loop circuit 10203, which are communicatively connected in sequence, a temperature control circuit communicatively connected to the phase-locked loop circuit 10203, and an OTP register 10207 communicatively connected to the temperature compensator circuit; the voltage divider 10201 is used to divide the received total voltage-controlled voltage to obtain a divided voltage control signal; the MEMS resonator 10202 is used to process the received divided voltage control signal to obtain a motional current; the transimpedance amplifier 10205 is used to generate an analog voltage signal based on the received motion current; the analog-to-digital converter 10206 is used to perform analog-to-digital conversion on the received analog voltage signal to obtain a first digital signal; the voltage amplitude control circuit performs amplitude control on the received first digital signal to obtain a second digital signal; the phase-locked loop circuit 10203 is used to process the received second digital signal to obtain an input signal of the voltage divider 10201; the temperature control circuit includes a temperature acquisition circuit 10209 and a temperature compensation circuit 10208 that are communicatively connected in sequence, and the temperature control circuit is used to perform temperature control on the phase-locked loop circuit to obtain a temperature compensation signal; the OTP register 10207 is used to store configuration parameters of the temperature control circuit.

[0066] Among them, the voltage amplitude control circuit includes a low-pass filter 10210, a PID control circuit 10212, an amplitude setting circuit 10213 and a second digitally controlled oscillator 10211 connected in series. The input end of the second digitally controlled oscillator 10211 is also communicatively connected to the analog-to-digital converter 10206, and the output end of the PID control circuit 1021 is connected to the phase-locked loop circuit 10203.

[0067] In an embodiment of the present application, the deep learning module includes: an acquisition circuit for acquiring a satellite second pulse signal and a 1Hz clock signal, and obtaining a phase difference digital signal based on the satellite second pulse signal and the 1Hz clock signal; a clock taming deep learning network for processing the input phase difference digital signal and outputting a predicted time-frequency signal; a judgment circuit for judging whether the fluctuation value of the satellite second pulse signal is greater than a preset threshold, then controlling the MEMS resonator to generate a 1Hz clock signal according to the time-frequency signal; otherwise, controlling the MEMS resonator to generate a 1Hz clock signal according to the phase difference digital signal; wherein, the clock taming deep learning network includes an input layer, a pattern layer, a summation layer and an output layer connected in sequence.

[0068] In an embodiment of the present application, the pattern layer is used to process input data using radial basis neurons to obtain an output vector, wherein the activation function expression of the radial basis neuron is:

[0069]

[0070] Where, X n represents the nth input sample, c j represents the center of the jth radial basis neuron, σ represents the variance of the Gaussian kernel function;

[0071] In an embodiment of the present application, the summation layer includes a first group of neurons and a second group of neurons; wherein the first group of neurons is used to sum the output vector to obtain a sum value S nk The second group of neurons is used to perform weighted summation of the output vectors to obtain the weighted sum value S Tn .

[0072] In the embodiment of the present application, each neuron in the output layer is used to calculate the sum of the input values ​​S nk and the weighted sum S Tn Process according to the preset second formula and output the predicted time-frequency signal, wherein the preset second formula is Where k is the number of neurons in the output layer, n = 1, 2, ···, N, k = 1, 2, ···, K, N is the total number of training samples, K is the total number of neurons in the output layer, y nk is the predicted time-frequency signal.

[0073] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A high-precision MEMS clock taming method based on deep learning, characterized in that: include: Acquire a satellite second pulse signal and a 1 Hz clock signal, and obtain a phase difference digital signal based on the satellite second pulse signal and the 1 Hz clock signal; Inputting the phase difference digital signal into a preset clock taming deep learning network to obtain a predicted time-frequency signal; If it is determined that the fluctuation value of the satellite second pulse signal is greater than a preset threshold, then controlling the MEMS oscillation circuit to generate a 1 Hz clock signal according to the time-frequency signal; otherwise, controlling the MEMS oscillation circuit to generate a 1 Hz clock signal according to the phase difference digital signal; The clock taming deep learning network includes an input layer, a pattern layer, a summation layer and an output layer connected in sequence.

2. The high-precision MEMS clock taming method based on deep learning according to claim 1, characterized in that: Each neuron in the pattern layer is a radial basis neuron, and the activation function expression of the radial basis neuron is: in, Indicates the input samples, Indicates the The center of the radial basis neurons, represents the variance of the Gaussian kernel function.

3. The high-precision MEMS clock taming method based on deep learning according to claim 1, characterized in that: The summation layer includes a first group of neurons and a second group of neurons; The input data of the first group of neurons is the output vector of each neuron in the pattern layer, and the output data is the sum of the output vectors. S nk ; The input data of the second group of neurons is the output vector of each neuron in the pattern layer, and the output data is the weighted sum of each output vector. S Tn .

4. The high-precision MEMS clock taming method based on deep learning according to claim 1, characterized in that: The input data of each neuron in the output layer is the sum value S nk and weighted sum S Tn , the output data is ,in, is the label of the output layer neuron, , N is the total number of training samples, K is the total number of neurons in the output layer.

5. A high-precision MEMS clock taming circuit based on deep learning, characterized in that: include: GNSS satellite receiver, used to receive satellite pulse-second signals; A MEMS oscillation circuit for generating an oscillation signal; a frequency divider, communicatively connected to the MEMS oscillation circuit, and configured to divide the frequency of the oscillation signal to obtain a 1 Hz clock signal; a phase detector, communicatively connected to the GNSS satellite receiver and the frequency divider, the phase detector inputting the 1 Hz clock signal and the satellite pulse second signal, and outputting a first phase difference analog signal; an analog-to-digital converter, communicatively connected to the phase detector, and configured to perform analog-to-digital conversion on the first phase difference analog signal to obtain a phase difference digital signal; a first digital-to-analog converter, communicatively connected to the analog-to-digital converter, and configured to perform analog-to-digital conversion on the phase difference analog signal to obtain a second phase difference analog signal; A deep learning module, communicatively connected to the analog-to-digital converter, and configured to process the phase difference digital signal to obtain a predicted time-frequency signal; a second digital-to-analog converter, communicatively connected to the deep learning module, and configured to perform digital-to-analog conversion on the predicted time-frequency signal to obtain an analog time-frequency signal; The FPGA has an input end communicatively connected to the GNSS satellite receiver, the second digital-to-analog converter, and the first digital-to-analog converter, and an output end communicatively connected to the MEMS oscillation circuit. The FPGA is used to determine that the generated 1 Hz clock signal is greater than a preset threshold, and then control the MEMS oscillation circuit to generate a 1 Hz clock signal according to the analog time-frequency signal; otherwise, control the MEMS oscillation circuit to generate a 1 Hz clock signal according to the second phase difference analog signal.

6. The high-precision MEMS clock taming circuit based on deep learning according to claim 5, characterized in that: The MEMS oscillation circuit comprises: An electrical first data oscillator, a voltage divider, a MEMS oscillation circuit, a transimpedance amplifier, an analog-to-digital converter, a voltage amplitude control circuit, and a phase-locked loop circuit, the output end of the previous circuit and the input end of the subsequent circuit being communicatively connected in sequence; a temperature control circuit being communicatively connected to the phase-locked loop circuit; and an OTP register being communicatively connected to the temperature control circuit; The voltage divider is used to perform voltage division processing on the received total voltage-controlled voltage to obtain a divided voltage control signal; The MEMS oscillation circuit is used to process the received voltage-dividing control signal to obtain a motion current; The transimpedance amplifier is used to generate an analog voltage signal according to the received motion current; The analog-to-digital converter is used to perform analog-to-digital conversion on the received analog voltage signal to obtain a first digital signal; The voltage amplitude control circuit is used to perform amplitude control on the received first digital signal to obtain a second digital signal; The phase-locked loop circuit is used to process the received second digital signal to obtain an input signal of the voltage divider; The temperature control circuit is used to perform temperature control on the phase-locked loop circuit to obtain a temperature compensation signal; The OTP register is used to store configuration parameters of the temperature control circuit.

7. The high-precision MEMS clock taming circuit based on deep learning according to claim 5, characterized in that: The deep learning module includes: an acquisition circuit, configured to acquire a satellite second pulse signal and a 1 Hz clock signal, and obtain a phase difference digital signal based on the satellite second pulse signal and the 1 Hz clock signal; A clock taming deep learning network is used to process the input phase difference digital signal and output a predicted time-frequency signal; a judgment circuit, configured to control a MEMS oscillation circuit to generate a 1 Hz clock signal according to the time-frequency signal if the fluctuation value of the satellite pulse-per-second signal is greater than a preset threshold; otherwise, control the MEMS oscillation circuit to generate a 1 Hz clock signal according to the phase difference digital signal; Among them, the clock taming deep learning network includes an input layer, a pattern layer, a summation layer and an output layer connected in sequence.

8. The high-precision MEMS clock taming circuit based on deep learning according to claim 7, characterized in that: The pattern layer is used to process the input data using each radial basis neuron to obtain an output vector, wherein the activation function expression of the radial basis neuron is: Where, Indicates the input samples, Indicates the The center of the radial basis neurons, represents the variance of the Gaussian kernel function.

9. The high-precision MEMS clock taming circuit based on deep learning according to claim 7, characterized in that: The summation layer includes a first group of neurons and a second group of neurons; The first group of neurons is used to sum the output vectors to obtain the sum value. S nk ; The second group of neurons is used to perform weighted summation on the output vectors to obtain a weighted sum value S Tn .

10. The high-precision MEMS clock taming circuit based on deep learning according to claim 9, characterized in that: The neurons in the output layer are used to sum the input values S nk and weighted sum S Tn Processing is performed according to a preset second formula to output the predicted time-frequency signal, wherein the preset second formula is ,in, is the label of the output layer neuron, , N is the total number of training samples, K is the total number of neurons in the output layer, is the predicted time-frequency signal.

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