Method for manufacturing a radio frequency power amplifier

Abstract

The application provides a preparation method of a radio frequency power amplifier, comprising: providing a substrate, which comprises a bottom silicon layer, a buried oxygen layer and a top silicon layer arranged in sequence from bottom to top; forming a shallow trench isolation structure in the top silicon layer, and adjacent active regions are isolated by the shallow trench isolation structure; and preparing a silicon germanium transistor in a first active region, comprising: etching part of the top silicon layer in the region to form an opening, and leaving a top silicon layer with a preset thickness between the bottom of the opening and the buried oxygen layer; doping the top silicon layer at the bottom of the opening to form a first heavily doped region as a collector region; growing a silicon germanium layer on the first heavily doped region as a base region; forming a second heavily doped region on the silicon germanium layer as an emitter region; and forming a metal interconnection structure. The technical scheme of the application is prepared on an SOI substrate, the size of the substrate can reach 12 inches, and the collector region, the base region and the emitter region of the silicon germanium transistor are arranged in the longitudinal direction, the occupation of the lateral space of the substrate is small, other devices can be arranged on the substrate, and the integration degree is high and the cost is low.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power amplifier technology, and in particular to a preparation method of a radio frequency power amplifier. BACKGROUND

[0002] The radio frequency power amplifier (RF PA) is a main part in a transmitting system. In the front-end circuit of the transmitter, the radio frequency signal power generated by the modulated oscillation circuit is very small, and needs to be amplified through a series of amplifiers to obtain sufficient radio frequency power before being fed to the antenna for radiation.

[0003] The main technical indicators of the radio frequency power amplifier are output power and efficiency. How to improve the output power and efficiency is the core of the design goal of the radio frequency power amplifier.

[0004] The existing radio frequency power amplifier processes include traditional CMOS technology, SOI technology and GaAs process. Among them, the traditional CMOS technology and SOI technology have the advantages of high integration and low cost, but their performance is poor, the electron mobility is low, and the withstand voltage is limited. The mainstream process of the current power amplifier is GaAs process, which has the advantages of high electron mobility and large power, but also has some disadvantages, such as: (1) complex process and high cost; (2) poor process integration.

[0005] Therefore, it is urgent to prepare a radio frequency amplifier with low cost, high process integration and good performance. SUMMARY

[0006] The present application provides a preparation method of a radio frequency power amplifier to solve the problems of high cost and poor process integration in the prior art.

[0007] To solve the above technical problems, the present application is realized by the following technical scheme:

[0008] The present application provides a preparation method of a radio frequency power amplifier, which comprises:

[0009] Step S0: providing a substrate, the substrate comprising a bottom silicon layer, a buried oxygen layer and a top silicon layer distributed in sequence from bottom to top;

[0010] Step S1: forming a shallow trench isolation structure in the top silicon layer, the shallow trench isolation structure being connected with the buried oxygen layer, and adjacent active regions of the top silicon layer being isolated by the shallow trench isolation structure;

[0011] Step S2: preparing a silicon germanium transistor in the first active region, comprising:

[0012] Etching part of the top silicon layer of the first active region to form an opening, and leaving a top silicon layer with a preset thickness between the bottom of the opening and the buried oxygen layer;

[0013] doping the top silicon layer of the opening bottom to form a first heavily doped region, the first heavily doped region as a collector region of the SiGe transistor;

[0014] growing a SiGe layer on the first heavily doped region, the SiGe layer as a base region of the SiGe transistor;

[0015] forming a second heavily doped region on the SiGe layer, the second heavily doped region as an emitter region of the SiGe transistor;

[0016] Step S3: forming a metal interconnection structure.

[0017] Optionally, the SiGe layer is a doped SiGe layer; the first heavily doped region and the second heavily doped region are of the same doping type; the SiGe layer is of a different doping type from the first heavily doped region and the second heavily doped region.

[0018] Optionally, forming a second heavily doped region on the SiGe layer specifically includes:

[0019] forming a cap silicon layer on the SiGe layer, the cap silicon layer being smaller in size than the SiGe layer;

[0020] doping the cap silicon layer to form the second heavily doped region, the second heavily doped region covering part of the surface of the SiGe layer.

[0021] Optionally, before Step S2, a well region is formed in the second active region.

[0022] Optionally, after Step S2 and before Step S3, a gate is formed on the second active region, and a source / drain region is formed in the well region on both sides of the gate to form a MOS tube.

[0023] Optionally, Step S3 specifically includes:

[0024] forming a first insulating layer on the substrate;

[0025] forming a plurality of first conductive structures in the first insulating layer, the surface of the plurality of first conductive structures being exposed by the first insulating layer, the plurality of first conductive structures including a first emitter region electrode structure and a first base region electrode structure of a SiGe transistor and a gate electrode structure, a source region electrode structure and / or a drain region electrode structure of a MOS tube, the bottom surface of the first emitter region electrode structure being in contact with the second heavily doped region, the bottom surface of the first base region electrode structure being in contact with the SiGe layer; wherein the source region / drain region electrode structure of the MOS tube is coupled with the first base region electrode structure of the SiGe transistor;

[0026] removing the bottom silicon layer, forming a first collector electrode structure on one side of the buried oxygen layer, the first collector electrode structure penetrating the buried oxygen layer and contacting the first heavily doped region.

[0027] Optionally, the method of forming a collector electrode structure on one side of the buried oxygen layer comprises:

[0028] forming a second insulating layer on the bottom of the buried oxygen layer;

[0029] forming a conductive via in the second insulating layer and the buried oxygen layer, one end of the conductive via contacting the first heavily doped region;

[0030] forming a metal layer in the second insulating layer, the bottom surface of the metal layer being exposed by the second insulating layer, and the top surface of the metal layer being electrically connected to the other end of the conductive via.

[0031] Optionally, the sidewall of the opening is separated from the sidewall of the shallow trench isolation structure by a preset distance, and a reserved area is formed between the two; step S2 specifically comprises:

[0032] etching part of the top silicon layer of the first active region to form an opening, and leaving a preset thickness of top silicon layer between the bottom of the opening and the buried oxygen layer;

[0033] forming an insulating layer on the bottom and sidewall of the opening;

[0034] doping the top silicon layer at the bottom of the opening to form a first heavily doped region, the first heavily doped region serving as a collector region of the silicon germanium triode;

[0035] removing the insulating layer at the bottom of the opening while retaining the insulating layer at the sidewall of the opening;

[0036] growing a silicon germanium layer on the first heavily doped region, the silicon germanium layer serving as a base region of the silicon germanium triode;

[0037] forming a second heavily doped region on the silicon germanium layer, the second heavily doped region serving as an emitter region of the silicon germanium triode;

[0038] forming a gate electrode on the second active region, heavily doping the reserved area and the well region on both sides of the gate electrode, forming source-drain regions in the well region on both sides of the gate electrode to form a MOS tube, and forming a third heavily doped region in the reserved area.

[0039] Optionally, step S3 specifically comprises:

[0040] forming a third insulating layer on the substrate;

[0041] Forming a plurality of second conductive structures in the third insulating layer, surfaces of the plurality of second conductive structures are exposed by the third insulating layer, the plurality of second conductive structures include a second emitter electrode structure, a second base electrode structure and a second collector electrode structure of a SiGe transistor, and a gate electrode structure, a source electrode structure and / or a drain electrode structure of a MOS tube, a bottom surface of the second emitter electrode structure contacts the second heavily doped region, a bottom surface of the second base electrode structure contacts the SiGe layer, and a bottom surface of the second collector electrode structure contacts the third heavily doped region; wherein the source / drain electrode structure of the MOS tube is coupled with the second base electrode structure of the SiGe transistor.

[0042] Optionally, the number of the MOS tubes is multiple, the plurality of MOS tubes are coupled by source / drain electrode structures to realize cascading, and the source / drain electrode structure of the MOS tube of the last stage is coupled with the first base electrode structure or the second base electrode structure of the SiGe transistor.

[0043] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0044] In the preparation method of the radio frequency power amplifier provided by the technical scheme of the present application, a method for forming a SiGe transistor on an SOI substrate is provided, so as to prepare a radio frequency power amplifier based on the SiGe transistor, thereby forming a radio frequency power amplifier which can provide greater power output and has high conversion effect, and which can be applied to a system with high communication frequency. Moreover, on the one hand, the SOI substrate has high selectivity in size, and can include sizes such as 6 inches, 8 inches and 12 inches; on the other hand, the collector region, the base region and the emitter region of the SiGe transistor are longitudinally arranged along the depth direction, thereby reducing the occupation of the SiGe transistor on the lateral space of the substrate, so as to provide more setting space, and to form the SiGe transistor and other devices (such as MOS tubes) on the same substrate, thereby realizing substrate-level packaging, improving the integration degree and reducing the cost. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical scheme in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0046] Figures 1-15 The cross-sectional schematic view of each step of the preparation method of the radio frequency power amplifier in an embodiment of the present application;

[0047] Figures 16-21 A cross-sectional view of some steps of a method of manufacturing a radio frequency power amplifier according to another embodiment of the present application;

[0048] Figures 22-25 A cross-sectional view of some steps of a method of manufacturing a radio frequency power amplifier according to another embodiment of the present application;

[0049] Figures 26-27 A cross-sectional view of some steps of a method of manufacturing a radio frequency power amplifier according to another embodiment of the present application;

[0050] Figure 28 A cross-sectional view of some steps of a method of manufacturing a radio frequency power amplifier according to another embodiment of the present application;

[0051] Figures 29-41 A cross-sectional view of some steps of a method of manufacturing a radio frequency power amplifier according to another embodiment of the present application; DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0053] In the description of the present application, it should be understood that the terms "upper", "lower", "upper end", "lower end", "lower surface", "upper surface" and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0054] In the description of the present application, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features.

[0055] In the description of the present application, the meaning of "a plurality of" is a plurality, for example, two, three, four, etc., unless otherwise explicitly specified.

[0056] The technical solutions of the present application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described in some embodiments.

[0057] Figures 1 to 15 is a schematic diagram of each step of the preparation method of the radio frequency power amplifier in an embodiment of the present application.

[0058] In this embodiment, the preparation method of the radio frequency power amplifier comprises:

[0059] Step S0: providing a substrate, the substrate comprising a bottom silicon layer 11, a buried oxygen layer 12 and a top silicon layer 13 arranged in sequence from bottom to top. As shown in Figure 1 .

[0060] As an implementation, the substrate can be an SOI substrate, comprising a bottom silicon layer 11, a buried oxygen layer 12 and a top silicon layer 13 arranged in sequence from bottom to top. The substrate can also be a silicon substrate, which serves as the bottom silicon layer, and the buried oxygen layer and the top silicon layer are sequentially deposited on the bottom silicon layer. The buried oxygen layer is silicon oxide, and the top silicon layer is single crystal silicon which is the same as the bottom silicon layer. Those skilled in the art can choose appropriate substrate materials, which are not limited here.

[0061] Step S1: forming a shallow trench isolation structure 131 in the top silicon layer 13, the shallow trench isolation structure 131 being connected with the buried oxygen layer 12, and adjacent active regions of the top silicon layer 13 being isolated by the shallow trench isolation structure 131, as shown in Figure 2 , the first active region 132 and the second active region 133 adjacent thereto are isolated by the shallow trench isolation structure 131.

[0062] Isolating adjacent active regions by the shallow trench structure is conducive to improving the electrical performance of the circuit.

[0063] Step S2: preparing a silicon germanium transistor (SiGe transistor) in the first active region 132, the specific steps can be referred to the description below.

[0064] Please refer to Figure 3 , a first mask layer 401 is prepared above the top silicon layer 13.

[0065] The first mask layer 401 comprises an oxide layer and a silicon nitride layer in sequence.

[0066] Specifically, an oxide layer is first prepared on the top silicon layer 13, and then a silicon nitride layer is prepared on the oxide layer. The oxide layer material is selected from SiO2, which provides a buffer layer for the subsequently formed silicon nitride layer. Specifically, the silicon nitride layer is directly formed on the substrate due to the relatively large stress, which causes dislocations on the surface of the substrate. However, the oxide layer is formed between the substrate and the silicon nitride layer, which avoids the defect of dislocations caused by directly forming the silicon nitride layer on the substrate. The oxide layer can be formed by using a thermal oxidation process. The thermal oxidation process can be performed by using an oxidation furnace. The silicon nitride layer is used as a stop layer for the subsequent chemical mechanical polishing process, and the silicon nitride layer forming process can be an existing chemical vapor deposition process.

[0067] Referring to Figure 4 A first photoresist layer 402 is formed on the first mask layer 401.

[0068] The first photoresist layer 402 is formed by forming a material of the first photoresist layer 402 on the surface of the first mask layer 401, and exposing and developing the material of the first photoresist layer 402.

[0069] The first photoresist layer 402 exposes part of the first mask layer 401 on the first active region 132.

[0070] The lateral dimension of the photoetching pattern of the first photoresist layer 402 is greater than or equal to the lateral dimension of the first active region 132.

[0071] Referring to Figure 5 The first mask layer 401 and the top silicon layer 13 are etched with the first photoresist layer 402 as a mask to etch part of the top silicon layer 13 of the first active region 132, and an opening 1321 is formed.

[0072] The etching stops in the top silicon layer, leaving a preset thickness of the top silicon layer 13 between the bottom of the opening 1321 and the buried oxygen layer 12, i.e., the top silicon layer 13 in this region still has a certain thickness.

[0073] Since the lateral dimension of the photoetching pattern of the first photoresist layer 402 is greater than or equal to the lateral dimension of the first active region 132, the sidewall of the opening 1321 exposes the shallow trench isolation structure 131, so that a SiGe layer 212 connected to the shallow trench isolation structure 131 can be formed in the subsequent process (as shown in Figure 7 ).

[0074] As an example, the lateral dimension of the photoetching pattern of the first photoresist layer is greater than the lateral dimension of the first active region 132, please refer to Figure 4 . Figure 5 The opening 1321 formed in the above process is a stepped structure with a wide top and a narrow bottom, which can be completed by one etching with different etching rates, or can be etched twice based on two photoresists.

[0075] After the etching, the first photoresist layer 402 is removed.

[0076] Referring to Figure 6 A second photoresist layer 4031 is formed on the first mask layer 401, and the top silicon layer 13 at the bottom of the opening 1321 is doped with the second photoresist layer 4031 as a mask to form a first heavily doped region 211. The first heavily doped region 211 is a collector region of the SiGe transistor.

[0077] As an embodiment, the first heavily doped region can be N-doped.

[0078] After forming the first heavily doped region 211, the second photoresist layer 4031 is removed.

[0079] Please refer to Figure 7 The SiGe layer 212 is grown on the first heavily doped region 211 as a base region of the SiGe transistor.

[0080] In some embodiments, the SiGe layer 212 is a doped SiGe layer, and the doping type of the SiGe layer is different from that of the first heavily doped region. For example, when the first heavily doped region is N-doped, the SiGe layer is P-doped. The doped SiGe layer can be grown by an epitaxial method, and can be doped while being grown.

[0081] As an example, the thickness of the SiGe layer can be any value between 10 nm and 100 nm.

[0082] Please refer to Figure 7 The cap-Si layer 404 is grown on the surface of the SiGe layer 212 at the same time when the SiGe layer 212 is grown, and the cap-Si layer 404 is located on the SiGe layer 212. Specifically, the cap-Si layer is grown by an epitaxial growth process, and the SiGe is doped at the same time when the SiGe is grown to form the SiGe layer 212, and then the Si is epitaxially grown to form the cap-Si layer 404. The total thickness of the first heavily doped region 211, the SiGe layer 212, and the cap-Si layer 404 is equal to the thickness of the complete top-Si layer of other active regions, so as to reduce the height difference of the substrate surface and ensure the flatness of the substrate to facilitate subsequent other process steps. Those skilled in the art can select appropriate thicknesses of the first heavily doped region 211, the SiGe layer 212, and the cap-Si layer 404 according to the performance requirements of the designed device, and ensure that the total thickness of the three is equal to the thickness of the complete top-Si layer of other active regions, which is not limited herein.

[0083] Please refer to Figure 8 The patterned third photoresist layer 405 is formed on the first mask layer 401 and the cap-Si layer 404, and the photoetching pattern on the third photoresist layer 405 corresponds to the region of the SiGe layer 212 that needs to be exposed.

[0084] Please refer to Figure 9 Based on the photoetching pattern of the third photoresist layer 405, the cap-Si layer 404 on the region of the SiGe layer that needs to be exposed is etched to expose part of the surface of the SiGe layer, which can be used for electrical lead-out of the base region. After this step, the cap-Si layer with a size smaller than that of the SiGe layer is formed on the SiGe layer.

[0085] Please refer toFigure 9 After etching the cap silicon layer 404 on the exposed region of the SiGe layer 212, the third photoresist layer 405 is removed.

[0086] Referring to Figure 10 A patterned fourth photoresist layer 406 is formed on the first mask layer 401, and the fourth photoresist layer 406 exposes the surface of the etched cap silicon layer 404.

[0087] Referring to Figure 11 The etched cap silicon layer 404 is doped to form a second heavily doped region 213 as an emitter region of the SiGe transistor. The method of doping the etched cap silicon layer 404 to form the second heavily doped region 213 includes ion implantation of the etched cap silicon layer 404 with the fourth photoresist layer 406 as a mask.

[0088] In some embodiments, the emitter region has the highest doping concentration, the collector region has a lower doping concentration than the emitter region, and the base region has a lower doping concentration than the collector region.

[0089] In other embodiments, for the sake of convenience, the emitter region and the collector region can have the same doping concentration, and the doping concentration can be any value between 1.0 x 1018cm-3and 1.0 x 1020cm-3. 14 -1.0 x 1020cm-3. 15 -3

[0090] After forming the second heavily doped region 213, the fourth photoresist layer 406 is removed, and a SiGe transistor is formed in the first active region.

[0091] After forming the SiGe transistor, the following steps can be further included:

[0092] Referring to Figure 12 A first oxide layer 407 is formed on the exposed SiGe layer 212 and the second heavily doped region 213. The first oxide layer 407 covers the exposed SiGe layer 212 and fills the gap of the shallow trench isolation structure 131.

[0093] Referring to Figure 13 After forming the first oxide layer 407, the first mask layer 401 is removed.

[0094] ​​In the above embodiment, a method for forming a SiGe transistor on a silicon-on-insulator (SOI substrate) is provided to prepare a radio frequency power amplifier based on a SiGe transistor, so that a radio frequency power amplifier with greater power output and high conversion effect can be formed, which can be particularly applied to a system with high communication frequency. In addition, since the SOI substrate is used, the size selectivity is high, including substrates with sizes of 6 inches, 8 inches, 12 inches, etc., and the collector region, the base region and the emitter region of the SiGe transistor are longitudinally arranged along the depth direction, so that the occupation of the SiGe transistor to the lateral space of the substrate is reduced, thereby providing more setting space to form the SiGe transistor and other devices (such as MOS tubes, etc.) on the same substrate, and the integration degree is improved and the cost is reduced.

[0095] In some embodiments, referring to Figure 2 , the top silicon layer is isolated into the first active region 132 and the second active region 133 by the shallow trench isolation structure, and the second active region 133 can be used for preparation of other devices (such as MOS tubes, etc.). After the preparation of the SiGe transistor, the surface of the SiGe transistor can be as level as possible with the surface of the top silicon layer in other regions, i.e., the surface of the second heavily doped region is as level as possible with the surface of the top silicon layer in other regions, so as to facilitate subsequent processes.

[0096] In this embodiment, after the SiGe transistor is formed, the following steps are further included:

[0097] Step S3: preparing a metal interconnection structure for electrically leading out the base region, the emitter region and the collector region of the SiGe transistor.

[0098] As an example, the base region and the emitter region of the SiGe transistor can be led out from the front side of the substrate, i.e., the side of the top silicon layer. Specifically, the following implementation manner can be adopted:

[0099] Referring to Figure 14 , after the SiGe transistor is formed, a first insulating layer 611 is formed on the substrate, and a plurality of first conductive structures are formed in the first insulating layer 611, the surfaces of the plurality of first conductive structures are exposed by the first insulating layer, and the plurality of first conductive structures include a first emitter region electrode structure 31 and a first base region electrode structure 32, the bottom surface of the first emitter region electrode structure 31 contacts the second heavily doped region, and the bottom surface of the first base region electrode structure 32 contacts the SiGe layer, i.e., the surface of the SiGe layer exposed by the second heavily doped region in Figure 9 .

[0100] It should be noted that the number of the first base region electrode structure can be two, as shown in Figure 14 , the two first base region electrode structures are respectively located on the two sides of the emitter region. Of course, the number of the first base region electrode structure can also be one, as shown in Figure 15 , which is located on one side of the emitter region.

[0101] In the embodiment, the collector region is led out from the back of the substrate. The collector electrode is led out from the back, which reduces the density of the metal interconnection structure on the front of the substrate, and the circuit is more stable. In addition, the collector electrode is led out from the back, which also reduces the lateral size of the SiGe transistor, and further reduces the occupied size of the substrate, so that more components can be arranged on the same size of substrate.

[0102] The collector region led out from the back of the substrate can adopt the following implementation:

[0103] Please refer to Figure 15 After the first conductive structure is formed, the bottom silicon layer is removed. After the bottom silicon layer is removed, the first collector region electrode structure 33 is formed on one side of the buried oxygen layer 12, and the first collector region electrode structure 33 penetrates the buried oxygen layer 12 and contacts the first heavily doped region.

[0104] As an implementation, please refer to Figure 15 After the bottom silicon layer is removed, a second insulating layer 71 can also be formed at the bottom of the buried oxygen layer. The conductive via 331 is formed in the second insulating layer 71 and the buried oxygen layer 12, one end of the conductive via 331 contacts the first heavily doped region 211. The metal layer 332 is prepared in the second insulating layer, the bottom surface of the metal layer 332 is exposed by the second insulating layer, and the top surface is electrically connected to the other end of the conductive via 331.

[0105] Specifically, the bottom silicon layer can be removed by a CMP process or an etching process to reduce the thickness of the back of the substrate, ensure subsequent process processing, and realize the preparation of the first collector region electrode structure. At the same time, the buried oxygen layer itself can also play an insulating role. The second insulating layer can be formed at the bottom of the buried oxygen layer to increase the thickness of the insulating layer, and the setting space of the collector region electrode structure is larger, and the insulating performance is better.

[0106] In different embodiments, the second insulating layer can also not be arranged, and the collector region electrode structure is directly formed in the buried oxygen layer.

[0107] Please refer to Figures 16-19 The preparation method of the radio frequency power amplifier of the embodiment of the application further includes: forming a MOS tube in the second active region on the same substrate. Specifically, it includes:

[0108] First, please refer to Figure 16After the steps S0 and S1 are completed, before the step S2 is performed, it further includes: forming a well region in the second active region. Specifically, the top silicon layer of the second active region 133 is doped to form an N-type well region or a P-type well region 221. When the first MOS transistor is an NMOS transistor, P-doping is performed in the top silicon layer of the corresponding region to form a P-type well region; when the first MOS transistor is a PMOS transistor, N-doping is performed in the top silicon layer of the corresponding region to form an N-type well region.

[0109] Please refer to Figures 3 to 13 The steps are schematically shown, and the step S2 is performed: preparing a SiGe transistor in the first active region.

[0110] After the SiGe transistor is prepared in the step S2, the first MOS transistor is then prepared in the second active region, a gate is formed on the second active region, and source-drain regions are formed in the well regions on both sides of the gate to form a MOS transistor. Specifically, it includes:

[0111] A gate is formed on the second active region. Please refer to Figure 17 A gate oxide layer 408 and a gate material layer 409 are sequentially formed on the front surface of the substrate. As an example, the gate oxide layer 408 can be grown on the substrate by a thermal oxidation process. Since the shallow trench isolation structure itself is an oxide layer, the gate oxide layer will not be deposited thereon. The exposed SiGe layer 212 will also not have the gate oxide layer deposited thereon because the first oxide layer has already been deposited thereon. The gate material layer can be a polysilicon material, which is formed on the substrate by a chemical vapor deposition process, as shown in Figure 17 .

[0112] Please refer to Figure 18 The excess gate oxide layer 408 and the gate material layer 409 are removed, leaving only the gate oxide layer 408 and the gate material layer 409 at the positions corresponding to the gate regions of the first MOS transistor. The gate material layer 409 is doped to form a gate. In some embodiments, when the first MOS transistor is an NMOS, the gate epitaxial layer is N-doped; when the first MOS transistor is a PMOS, the gate epitaxial layer is P-doped.

[0113] The source-drain regions are formed in the well regions on both sides of the gate to form a MOS transistor. Please refer to Figure 19 The N-type semiconductor or P-type semiconductor on both sides of the gate epitaxial layer 409 is doped to serve as a source region and a drain region (410, 411), respectively. When the first MOS transistor is an NMOS, the source region and the drain region are N-type. When the first MOS transistor is a PMOS, the source region and the drain region are P-type.

[0114] After the first MOS transistor is formed, step S3 is performed: forming a metal interconnection structure. The metal interconnection structure corresponding to the first MOS transistor and the metal interconnection structure corresponding to the SiGe transistor can be formed simultaneously.

[0115] In particular, referring to Figure 20 , after the first insulating layer 611 is formed on the substrate, the first conductive structures formed in the first insulating layer 611 further include electrode structures 34 of the first MOS transistor, such as gate electrode structures, source electrode structures, and / or drain electrode structures. The surfaces of the electrode structures 34 of the first MOS transistor are exposed by the first insulating layer 611, and the bottom surfaces of the electrode structures 34 of the first MOS transistor respectively contact the gate region and the source region and / or the drain region of the first MOS transistor. The first MOS transistor and the SiGe transistor are coupled through the source electrode structure or the drain electrode structure of the first MOS transistor and the base electrode structure of the SiGe transistor to form a radio frequency power amplifier, achieve multi-stage amplification, increase the output power of the radio frequency power amplifier, and improve the conversion efficiency of the radio frequency power amplifier. Further, the MOS transistor and the SiGe transistor are formed on the same substrate, and the combination of the SiGe transistor and the MOS does not need to be realized through bonding packaging, which improves the integration and reduces the cost. In addition, the adjacent active regions are isolated by the shallow trench isolation structure to prevent mutual interference between different devices and improve the electrical performance.

[0116] As an embodiment, referring to Figure 21 , the electrode structures of the drain region or the source region of the first MOS transistor and the base region of the SiGe transistor are electrically connected by the metal interconnection line 81 to realize the coupling of the MOS transistor and the SiGe transistor.

[0117] In some embodiments, before the conductive structures located on the front surface of the substrate are prepared, the surface of the electrode lead-out position of each region is provided with a metal silicide 91, referring to Figure 20 , each region is electrically connected to the metal interconnection structure through the metal silicide 91, so that the electrical connection performance is better.

[0118] The specific preparation steps of the metal silicide are described in detail in Figures 22 to 25 .

[0119] Referring to Figure 22 , a second mask layer 412 is prepared on the front surface of the substrate.

[0120] As an embodiment, the second mask layer includes an oxidation layer, and the material of the oxidation layer can be SiO2.

[0121] Referring to Figure 23After forming the second mask layer 412, a patterned fifth photoresist layer 413 is formed on the second mask layer 412, and the photoresist pattern on the fifth photoresist layer 413 corresponds to the electrode lead-out position of each region.

[0122] Please refer to Figure 24 After forming the patterned fifth photoresist layer 413, etching is performed using the fifth photoresist layer 413 as a mask, and the surface of the electrode lead-out position of each region is exposed, i.e., the region where the metal silicide needs to be formed is exposed.

[0123] Please refer to Figure 25 After etching, the second mask layer is removed, and a metal 91 is deposited on the electrode lead-out position of each region. The material of the metal 91 can be NiPt and TiN. After depositing the metal 91, high-temperature annealing is performed to form the metal silicide.

[0124] In some embodiments, the first MOS tube can be an NMOS tube, and when used for amplification, the drain region of the NMOS tube is electrically connected to the base region of the SiGe transistor.

[0125] In another embodiment, the first MOS tube can also be a PMOS tube, and when used for amplification, the source region of the PMOS tube is electrically connected to the base region of the SiGe transistor.

[0126] Preferably, the number of MOS tubes can be more than one, further improving the output power. All MOS tubes are cascaded, i.e., all MOS tubes are used as amplifying tubes to form a multi-stage amplification, and the output end of the last-stage MOS tube is electrically connected to the base region of the SiGe transistor.

[0127] In another embodiment, two MOS tubes are formed in the second active region, and the preparation method further includes: preparing a second MOS tube 22 in the second active region, please refer to Figure 26 A second MOS tube is also prepared on the same substrate, and the drain region or the source region of the second MOS tube is electrically connected to the source region or the drain region of the first MOS tube, further improving the output power.

[0128] Preferably, the preparation of the second MOS tube and the preparation of the first MOS tube can be performed simultaneously, and the method is referred to the preparation of the first MOS tube, which is not described here.

[0129] In some embodiments, after forming the second MOS tube, a metal interconnection structure is prepared for electrically leading out the second MOS tube. The preparation of the metal interconnection structure corresponding to the second MOS tube and the preparation of the metal interconnection structure corresponding to the SiGe transistor and the metal interconnection structure corresponding to the first MOS tube can be performed simultaneously. Please refer to Figure 27The second MOS transistor is cascaded with the first MOS transistor through source / drain electrode coupling, and the second MOS transistor, the first MOS transistor, and the SiGe transistor form a multi-stage amplification.

[0130] In one embodiment, the second MOSFET and the first MOSFET can be of the same type. For example, they can both be NMOS transistors, in which case the drain region of the second MOSFET is electrically connected to the source region of the first MOSFET, and the drain region of the first MOSFET is electrically connected to the base region of the SiGe transistor. In another example, the second MOSFET and the first MOSFET can both be PMOS transistors, in which case the source region of the second MOSFET is electrically connected to the drain region of the first MOSFET, and the source region of the first MOSFET is electrically connected to the base region of the SiGe transistor.

[0131] In another implementation, the second MOSFET and the first MOSFET can also be of different types, such as... Figure 26 As shown. For example, the second MOSFET can be an NMOS and the first MOSFET can be a PMOS. In this case, the drain region of the second MOSFET is electrically connected to the drain region of the first MOSFET, and the source region of the first MOSFET is electrically connected to the base region of the SiGe transistor. In a different example, the second MOSFET can be a PMOS and the first MOSFET can be an NMOS. In this case, the source region of the second MOSFET is electrically connected to the source region of the first MOSFET, and the drain region of the first MOSFET is electrically connected to the base region of the SiGe transistor.

[0132] It should be noted that, Figure 26 Taking the example where the first MOSFET and the second MOSFET are located on opposite sides of a SiGe transistor, the number of second active regions is two. In different embodiments, the first MOSFET and the second MOSFET can also be located on the same side of the SiGe transistor. In this case, due to the different types and doping types, shallow trench isolation is provided between each MOSFET, and the number of second active regions is also two.

[0133] In a preferred embodiment, when the second MOSFET and the first MOSFET are of the same type, their source and drain regions have the same doping type. For example, if both are NMOS transistors, they are both N-type doped; if both are PMOS transistors, they are both P-type doped. Since their source and drain regions have the same doping type, their electrical connections can be shared. That is, when both are NMOS transistors, the drain region of the second MOSFET shares the source region of the first MOSFET. Figure 28When the first MOS tube and the second MOS tube are both PMOS tubes, the source region of the second MOS tube and the drain region of the first MOS tube are shared. By sharing the electrodes, the occupied area can be reduced, and more components can be arranged on the same size substrate. In addition, after the electrodes are shared, the interconnection is realized, and the two electrodes do not need to be led out through the metal interconnection structure, which increases the setting density of the metal interconnection structure, and further increases the setting density of the metal interconnection line, reduces the risk of short circuit, and improves the stability of the circuit.

[0134] Figures 29 to 41 is a cross-sectional structure diagram of each step of the preparation method of the radio frequency power amplifier of another embodiment of the present application.

[0135] Another embodiment of the present application also provides a preparation method of a radio frequency power amplifier. Figures 1 to 13 The main difference between the embodiment and the embodiment shown in

[0136] Please continue to refer to Figure 3 on the basis of Figures 29 to 40 .

[0137] Please refer to Figure 29 , a patterned first photoresist layer 402 is formed on the first mask layer 401.

[0138] The forming method of the first photoresist layer 402 is similar to the forming method of the embodiment shown in Figure 4 , which will not be described here.

[0139] The difference between the embodiment and the embodiment shown in Figure 4 is that the lateral size of the photoetching pattern of the first photoresist layer 402 is smaller than the lateral size of the first region.

[0140] Please refer to Figure 30 , the first mask layer 401 and the top silicon layer 13 are etched with the first photoresist layer 402 as a mask to etch part of the top silicon layer 13 of the first active region 132, and an opening 1322 is formed.

[0141] The etching stops in the top silicon layer, so that there is a top silicon layer 13 with a preset thickness between the bottom of the opening and the buried oxygen layer 12, that is, the top silicon layer 13 in this region still has a certain thickness.

[0142] Since the lateral size of the photoetching pattern of the first photoresist layer 402 is smaller than the lateral size of the first region, the sidewall of the opening 1322 is separated from the sidewall of the shallow trench isolation structure by a preset distance, and a reserved region 134 is formed between the two. The side edge region in the first region which is not etched, that is, the reserved region 134, can be used for electrical lead-out of the collector region.

[0143] After the etching, the first photoresist layer 402 is removed.

[0144] Please refer to Figures 31 to 33 , an insulating layer is formed on the bottom and sidewall of the opening; the top silicon layer of the bottom of the opening is doped to form a first heavily doped region, which serves as the collector region of the SiGe transistor; the insulating layer of the bottom of the opening is removed, and the insulating layer of the sidewall of the opening is retained.

[0145] Specifically, the following implementation can be adopted: first, an insulating layer 51 is formed on the sidewall and bottom of the opening through an oxidation process, as shown in Figure 31 ; then a patterned second photoresist layer 4032 is formed on the first mask layer 401, and the top silicon layer of the bottom of the opening is doped to form a first heavily doped region 211 using the second photoresist layer 4032 as a mask, as shown in Figure 32 ; next, the insulating layer 51 above the first heavily doped region 211 is removed by dry etching, and only the insulating layer 51 of the sidewall of the opening is retained, as shown in Figure 33 .

[0146] Please refer to Figures 34 to 40 , the preparation methods are similar to those of the embodiment shown in Figures 7-13 , and will not be described here.

[0147] In this embodiment, after the SiGe transistor is formed, a metal interconnection structure is prepared, including a second base region electrode structure 36, a second emitter region electrode structure 35, and a second collector region electrode structure 37, for electrically leading out the base region, emitter region, and collector region of the SiGe transistor.

[0148] In this embodiment, the base region and the emitter region can be led out from the front surface of the substrate, and their electrical leading-out method is similar to that of the base region and the emitter region of the embodiment shown in Figure 14 ; in addition, the collector region can also be led out from the front surface of the substrate.

[0149] Specifically, the following implementation can be adopted:

[0150] Please refer to Figure 41 , the top layer of silicon of the reserved area 134 is heavily doped to form a third heavily doped region 333, which contacts the first heavily doped region 211.

[0151] When the preparation method further includes preparing a MOS tube, the doping of the third heavily doped region can be performed simultaneously with the formation of the source and drain of the MOS tube.

[0152] In this embodiment, step S3 specifically includes:

[0153] A third insulating layer 612 is formed on the substrate;

[0154] A plurality of second conductive structures are formed within the third insulating layer 612, the surfaces of which are exposed by the third insulating layer 612. These second conductive structures include a second emitter electrode structure 35, a second base electrode structure 36, and a second collector electrode structure 37 of a germanium-silicon transistor. The bottom surface of the second emitter electrode structure 35 contacts a second heavily doped region, the bottom surface of the second base electrode structure 36 contacts a silicon-germanium layer, and the bottom surface of the second collector electrode structure 37 contacts a third heavily doped region 333.

[0155] It should be noted that the number of second base region electrode structures can be two, such as... Figure 41 As shown, the two second base region electrode structures are located on both sides of the emitter region. Of course, the number of second base region electrode structures can also be one, arranged as follows: Figure 15 As shown, it is located on one side of the launch area.

[0156] The number of electrode structures in the second collector region can also be two, such as... Figure 41 As shown, the two second collector region electrode structures are located on both sides of the emitter region. Furthermore, the number of second collector region electrode structures can also be one, when led out from the front side of the substrate, and... Figure 14 The base region electrode structure is similar, and it can be located on one side of the emitter region; when led out from the back side of the substrate, the arrangement is as follows: Figure 15 As shown.

[0157] exist Figures 29 to 41 Based on the illustrated embodiment, the first MOS transistor and the second MOS transistor can also be fabricated, and their fabrication methods are the same as those shown. Figures 1 to 15 The fabrication methods for the first and second MOS transistors based on the illustrated embodiment are similar, i.e., they are the same as... Figures 16 to 21 The fabrication method for the MOS transistor shown is similar and will not be repeated here.

[0158] In the description of this specification, the references to terms such as "an embodiment," "an example," "a specific implementation process," and "an example" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0159] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of fabricating a radio frequency power amplifier, characterized by, The application relates to a method for manufacturing a substrate, and comprises the following steps: S0, providing a substrate, wherein the substrate comprises, from bottom to top, a bottom silicon layer, a buried oxygen layer and a top silicon layer; S1, forming a shallow trench isolation structure in the top silicon layer, wherein the shallow trench isolation structure is connected with the buried oxygen layer, and adjacent active regions of the top silicon layer are isolated by the shallow trench isolation structure; S2, preparing a silicon-germanium transistor in a first active region, comprising the following steps: etching part of the top silicon layer of the first active region to form an opening, wherein a top silicon layer with a preset thickness is reserved between the bottom of the opening and the buried oxygen layer; doping the top silicon layer at the bottom of the opening to form a first heavily doped region, wherein the first heavily doped region serves as a collector region of the silicon-germanium transistor; growing a silicon-germanium layer on the first heavily doped region, wherein the silicon-germanium layer serves as a base region of the silicon-germanium transistor; forming a second heavily doped region on the silicon-germanium layer, wherein the second heavily doped region serves as an emitter region of the silicon-germanium transistor; S3, forming a metal interconnection structure.

2. The production method according to claim 1, characterized by, The silicon-germanium layer is a doped silicon-germanium layer; the first heavily doped region and the second heavily doped region have the same doping type; the doping type of the silicon-germanium layer is different from the doping type of the first heavily doped region and the second heavily doped region.

3. The method of claim 1, wherein, Forming the second heavily doped region on the silicon-germanium layer specifically comprises the following steps: forming a cap silicon layer on the silicon-germanium layer, wherein the size of the cap silicon layer is smaller than the size of the silicon-germanium layer; doping the cap silicon layer to form the second heavily doped region, wherein the second heavily doped region covers part of the surface of the silicon-germanium layer.

4. The method of claim 1, wherein, Before step S2 is performed, it is also necessary to form a well region in a second active region.

5. The preparation method according to claim 4, characterized in that, After step S2 is completed, before step S3 is performed, it is also necessary to form a gate electrode on the second active region, and form source / drain regions in the well regions on both sides of the gate electrode to form a MOS transistor.

6. The production method according to claim 5, wherein Step S3 specifically comprises the following steps: forming a first insulating layer on the substrate; forming a plurality of first conductive structures in the first insulating layer, wherein the surfaces of the plurality of first conductive structures are exposed by the first insulating layer, the plurality of first conductive structures comprise a first emitter region electrode structure and a first base region electrode structure of a silicon-germanium transistor and a gate electrode structure, a source region electrode structure and / or a drain region electrode structure of a MOS transistor, the bottom surface of the first emitter region electrode structure is in contact with the second heavily doped region, and the bottom surface of the first base region electrode structure is in contact with the silicon-germanium layer; wherein the source region / drain region electrode structure of the MOS transistor is coupled with the first base region electrode structure of the silicon-germanium transistor; removing the bottom silicon layer to form a first collector region electrode structure on one side of the buried oxygen layer, wherein the first collector region electrode structure penetrates through the buried oxygen layer and is in contact with the first heavily doped region.

7. The production method according to claim 6, wherein The method for forming a collector region electrode structure on one side of the buried oxygen layer comprises the following steps: forming a second insulating layer on the bottom of the buried oxygen layer; forming a conductive via in the second insulating layer and the buried oxygen layer, wherein one end of the conductive via is in contact with the first heavily doped region; preparing a metal layer in the second insulating layer, wherein the bottom surface of the metal layer is exposed by the second insulating layer, and the top surface of the metal layer is electrically connected with the other end of the conductive via.

8. The preparation method according to claim 4, characterized in that, The sidewall of the opening is separated from the sidewall of the shallow trench isolation structure by a preset distance, and a reserved area is formed between the two; The step S2 specifically comprises: Etching a part of the top silicon layer of the first active region to form an opening, and a top silicon layer with a preset thickness is reserved between the bottom of the opening and the buried oxygen layer; An insulating layer is formed at the bottom and sidewall of the opening; The top silicon layer at the bottom of the opening is doped to form a first heavily doped region, which serves as a collector region of the silicon germanium triode; The insulating layer at the bottom of the opening is removed, and the insulating layer at the sidewall of the opening is reserved; A silicon germanium layer is grown on the first heavily doped region, which serves as a base region of the silicon germanium triode; A second heavily doped region is formed on the silicon germanium layer, which serves as an emitter region of the silicon germanium triode; A gate is formed on the second active region, the well region on both sides of the gate and the reserved area are heavily doped, a source / drain region is formed in the well region on both sides of the gate to form a MOS tube, and a third heavily doped region is formed in the reserved area.

9. The preparation method according to claim 8, characterized in that, The step S3 specifically comprises: A third insulating layer is formed on the substrate; A plurality of second conductive structures are formed in the third insulating layer, the surfaces of the plurality of second conductive structures are exposed by the third insulating layer, the plurality of second conductive structures include a second emitter electrode structure, a second base electrode structure and a second collector electrode structure of a silicon germanium triode, and a gate electrode structure, a source electrode structure and / or a drain electrode structure of a MOS tube, the bottom surface of the second emitter electrode structure contacts the second heavily doped region, the bottom surface of the second base electrode structure contacts the silicon germanium layer, and the bottom surface of the second collector electrode structure contacts the third heavily doped region; wherein the source / drain electrode structure of the MOS tube is coupled to the second base electrode structure of the silicon germanium triode.

10. The preparation method according to claim 7, characterized in that, The number of MOS tubes is multiple, and the plurality of MOS tubes are coupled by source / drain electrode structures to realize cascading, and the source / drain electrode structure of the last stage MOS tube is coupled to the first base electrode structure of the silicon germanium triode.

11. The preparation method according to claim 9, characterized in that, The number of MOS tubes is multiple, and the plurality of MOS tubes are coupled by source / drain electrode structures to realize cascading, and the source / drain electrode structure of the last stage MOS tube is coupled to the second base electrode structure of the silicon germanium triode. The number of MOS tubes is multiple, and the plurality of MOS tubes are coupled by source / drain electrode structures to realize cascading, and the source / drain electrode structure of the last stage MOS tube is coupled to the second base electrode structure of the silicon germanium triode.

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