An enhanced gallium nitride power transistor and an electronic device

Abstract

The present application relates to an enhanced gallium nitride power transistor in the field of semiconductors, which is characterized by including a buffer layer; a barrier layer located above the buffer layer; a source electrode and a drain electrode located above the barrier layer; at least one first gate located above the barrier layer, wherein the first gate includes P-type gallium nitride; a passivation layer located above the barrier layer and surrounding the first gate; at least one second gate located in the passivation layer and maintaining a preset distance from the first gate; wherein regardless of the state of the transistor, the first gate is always configured to receive a first preset voltage. The present application combines an enhanced P-GaN gate and a MIS gate to achieve a gallium nitride power transistor structure with a stable positive threshold voltage and a reliable gate. The present application also provides an electronic device including the above-mentioned enhanced gallium nitride power transistor.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to an enhanced gallium nitride power transistor and an electronic device. Background Art

[0002] At present, the main ways to realize enhancement-mode gallium nitride transistors such as HEMT include P-GaN gate structure and MIS gate structure. However, both structures have their own disadvantages. For the P-GaN gate structure, the gate needs to be biased to a forward voltage greater than 5.5V when the transistor is fully turned on, which will be subjected to higher electric field stress. This stress may cause ionization of the material or interface damage. Therefore, there are often various failure phenomena, including TDDB, hole trap capture, etc. For the enhancement-mode MIS gate structure, these problems are slightly less than those of the P-GaN gate structure, but the problem it faces is that it cannot obtain a stable positive threshold voltage. In the MIS GaN HEMT that is often seen with a positive threshold voltage, its threshold voltage will change with the GaN gate voltage bias history. Summary of the invention

[0003] In view of the technical problems existing in the prior art, the present application proposes an enhancement-mode gallium nitride power transistor, characterized in that it includes a buffer layer; a barrier layer located above the buffer layer; a source electrode and a drain electrode located above the barrier layer; at least one first gate located above the barrier layer, wherein the first gate includes P-type gallium nitride and is an enhancement-mode gate; a passivation layer located above the barrier layer and surrounding the first gate; at least one second gate located in the passivation layer and maintaining a preset distance from the first gate; wherein no matter what state the transistor is in, the first gate is always configured to receive a first preset voltage.

[0004] Particularly, when the dielectric constant of the passivation layer is greater than or equal to 3.5, the width of the first gate is less than or equal to 100 nm, and the preset distance is less than 100 nm.

[0005] Particularly, the preset distance is 10-50 nm.

[0006] Particularly, the second gate is located between the first gate and the source electrode and / or between the first gate and the drain electrode.

[0007] Particularly, the first gate is located between the second gate and the source electrode and / or between the first gate and the drain electrode.

[0008] In particular, in any of the transistors described above, the barrier layer includes at least one groove, and the second gate is located in the groove.

[0009] Specifically, the height difference between the bottom surface of the second gate and the bottom surface of the first gate is 20 - 30 nm.

[0010] Specifically, the width of the first gate is greater than or equal to 30 nm and less than or equal to 40 nm.

[0011] Specifically, the first preset voltage is the ground potential.

[0012] Specifically, when the voltage received by the second gate configuration is greater than or equal to the second preset voltage, the channels under the first gate and the second gate are turned on, otherwise the channel under the first gate is turned off.

[0013] Specifically, the second preset voltage is a voltage greater than or equal to 0.5 V and less than or equal to 30 V.

[0014] The present application also provides an electronic device, including the enhancement-mode gallium nitride transistor as described in any one of the foregoing.

[0015] By combining the enhancement-mode P-GaN gate and the MIS gate, the present application realizes a gallium nitride power transistor structure with a stable positive threshold voltage and a reliable gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Next, the preferred embodiments of the present application will be further described in detail with reference to the drawings, where:

[0017] Figure 1 Shown is a schematic side cross-sectional view of an enhancement-mode gallium nitride power transistor according to an embodiment of the present application.

[0018] Figure 2 Shown is a schematic side cross-sectional view of an enhancement-mode gallium nitride power transistor according to an embodiment of the present application.

[0019] Figure 3 Shown is a schematic side cross-sectional view of an enhancement-mode gallium nitride power transistor according to an embodiment of the present application.

[0020] Figure 4 Shown is a schematic side cross-sectional view of an enhancement-mode gallium nitride power transistor according to an embodiment of the present application.

[0021] Figure 5 Shown is a schematic side cross-sectional view of an enhancement-mode gallium nitride power transistor according to an embodiment of the present application.

[0022] Figure 6 Shown is a schematic side cross-sectional view of an enhancement-mode gallium nitride power transistor according to an embodiment of the present application.

[0023] Figure 7 and Figure 8Shown is a simulation diagram of the operating state of an enhanced gallium nitride power transistor according to an embodiment of the present application.

[0024] Figure 9 Shown is a threshold voltage characteristic curve graph of an enhanced gallium nitride power transistor with a P-GaN gate structure of different widths according to an embodiment of the present application.

[0025] Figure 10 and Figure 11 Shown is a transfer characteristic curve graph of an enhanced gallium nitride power transistor according to an embodiment of the present application.

[0026] Figure 12 Shown is a transfer characteristic curve graph in an enhanced gallium nitride power transistor with a P-GaN gate structure of different widths according to an embodiment of the present application. Detailed implementation manners

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0028] In the following detailed description, reference may be made to the accompanying drawings that form a part hereof and that show, by way of illustration, specific embodiments in which the present application may be practiced. In the drawings, like reference numerals describe substantially similar components in different views. The various specific embodiments of the present application have been described in sufficient detail below to enable those of ordinary skill in the art with relevant knowledge and technology to practice the technical solutions of the present application. It should be understood that other embodiments may be utilized or structural, logical, or electrical changes may be made to the embodiments of the present application.

[0029] Figure 1 Shown is a side cross-sectional schematic diagram of an enhanced gallium nitride power transistor according to an embodiment of the present application.

[0030] According to one embodiment, the gallium nitride power transistor may include, and the buffer layer 101 may include, for example, a combined layer of GaN or Al x Ga 1-x N.

[0031] According to one embodiment, the gallium nitride power transistor may further include a barrier layer 102 located above the buffer layer 101, which may include, for example, Al x Ga 1-x N.

[0032] According to one embodiment, the gallium nitride power transistor may further include a source electrode S and a drain electrode D located above the barrier layer 102. According to one embodiment, in order to contact the two-dimensional electron gas, etching or alloying reaction is carried out, and the source electrode S and the drain electrode D (contact interface) may be below the surface of the barrier layer 102.

[0033] According to one embodiment, the gallium nitride power transistor may further include a first gate G11 located above the barrier layer 102, which may include P-GaN, and G11 is in contact with the barrier layer 102. According to one embodiment, the first gate G11 is an enhancement-mode gate. An enhancement-mode gate is defined as a gate that makes the conduction threshold voltage of the channel below it greater than 0 volts.

[0034] According to one embodiment, the gallium nitride power transistor may further include a passivation layer 103 located above the barrier layer 102 and surrounding the top surface and side surfaces of the first gate G11.

[0035] According to one embodiment, the gallium nitride power transistor may further include a second gate G12 located in the passivation layer 103 and maintaining a preset distance from the first gate G11. G12 may include a metal such as TiN, Ti, Pt, W, Al, etc. A passivation layer may be provided between G12 and the barrier layer 102 to form a MIS gate. According to different embodiments, the second gate G12 may be a depletion-mode or enhancement-mode gate. A depletion-mode gate means that the threshold voltage for turning on the channel below it is less than 0 volts. According to one embodiment, G12 may be a depletion-mode Schottky contact (metal-semiconductor contact), and the characteristic of this type of contact is a stable threshold voltage.

[0036] According to one embodiment, the gallium nitride power transistor may further include an electrode lead-out layer 104-1 located above the first gate G11 and an electrode lead-out layer 104-2 located above the second gate G12. The electrode lead-out layers above G11 and G12 may be independent of each other. According to one embodiment, the contact between the electrode lead-out layer 104-1 above the first gate G11 and G11 may be an ohmic contact or a Schottky contact, and different materials or manufacturing processes may be adopted according to specific needs.

[0037] According to one embodiment, the thickness of the passivation layer 103 between the second gate G12 and the barrier layer 102 may be less than 100 nm.

[0038] According to one embodiment, when the relative permittivity of the passivation layer 103 is greater than or equal to 3.5, the horizontal preset distance between the first gate G11 and the second gate G12 in the source-drain direction can be less than 100 nm. In particular, it can be 10 - 50 nm. According to one embodiment, the width of the first gate G11 can be less than or equal to 100 nm; in particular, the width of G11 can be 40 nm or less. In this application, the so-called width refers to the distance extending in the source-drain direction parallel to the paper surface in the schematic cross-sectional view of the transistor.

[0039] Figure 2 Shown is a schematic cross-sectional view of an enhancement-mode gallium nitride power transistor according to an embodiment of the present application.

[0040] According to one embodiment, the gallium nitride power transistor may include a buffer layer 101, which may include, for example, a combined layer of GaN or Al x Ga 1-x N.

[0041] According to one embodiment, the gallium nitride power transistor may further include a barrier layer 102 located above the buffer layer 101, which may include, for example, Al x Ga 1-x N.

[0042] According to one embodiment, the gallium nitride power transistor may further include a source electrode S and a drain electrode D located above the barrier layer 102. According to one embodiment, in order to contact the two-dimensional electron gas, etching or alloying reaction is carried out, and the source electrode S and the drain electrode D (contact interface) may be below the surface of the barrier layer 102.

[0043] According to one embodiment, the gallium nitride power transistor may further include a passivation layer 103 located above the barrier layer 102 and surrounding the top surface and side surfaces of the first gate G11.

[0044] As shown in the figure, the transistor may include two second gates G12-1 and G12-2 in the passivation layer 103, respectively located between the first gate G11 and the source electrode S, and between the first gate G11 and the drain electrode D.

[0045] According to one embodiment, the widths of the two second gates G12-1 and G12-2 may be the same or different.

[0046] According to different embodiments, the width of the first gate G11 can be less than or equal to 100 nm; in particular, the width of G11 can be 40 nm or less. And when the relative permittivity of the passivation layer 103 is greater than or equal to 3.5, the preset horizontal distance between the two second gates G12-1 and G12-2 and the first gate G11 can be less than 100 nm. In particular, it can be 10 - 50 nm.

[0047] Figure 3 Shown is a side cross-sectional view of an enhanced gallium nitride power transistor according to an embodiment of the present application.

[0048] According to one embodiment, the gallium nitride power transistor may include a buffer layer 101, which may include, for example, a combined layer of GaN or Al x Ga 1-x N.

[0049] According to one embodiment, the gallium nitride power transistor may further include a barrier layer 102 located above the buffer layer 101, which may include, for example, Al x Ga 1-x N.

[0050] According to one embodiment, the gallium nitride power transistor may further include a source electrode S and a drain electrode D located above the barrier layer 102. According to one embodiment, in order to contact the two-dimensional electron gas, etching or alloying reaction is performed, and the source electrode S and the drain electrode D (contact interface) may be below the surface of the barrier layer 102.

[0051] According to one embodiment, the gallium nitride power transistor may further include a passivation layer 103 located above the barrier layer 102.

[0052] As shown in the figure, the transistor may include two first gates G11-1 and G11-2, respectively located between the second gate G12 and the source electrode S, and between the second gate G12 and the drain electrode D.

[0053] According to one embodiment, the widths of the two first gates G11-1 and G11-2 may be the same or different, and may be less than or equal to 100 nm. In particular, the widths of the first gates G11-1 and G11-2 may be 40 nm or less.

[0054] According to different embodiments, when the relative dielectric constant of the passivation layer 103 is greater than or equal to 3.5, the preset horizontal distance between the two first gates G11-1 and G11-2 and the second gate G12 may be less than 100 nm. In particular, it may be 10 - 50 nm.

[0055] According to one embodiment, the passivation layer 103 surrounds the top and side surfaces of the first gates G11-1 and G11-2 and the second gate G12.

[0056] Figure 4 Shown is a side cross-sectional view of an enhanced gallium nitride power transistor according to an embodiment of the present application.

[0057] According to one embodiment, the gallium nitride power transistor may include a buffer layer 101, which may include, for example, a combined layer of GaN or Alx Ga 1-x A combined layer of N.

[0058] According to one embodiment, the gallium nitride power transistor may further include a barrier layer 102 located above the buffer layer 101, which may include, for example, Al x Ga 1-x N.

[0059] According to one embodiment, the gallium nitride power transistor may further include a source electrode S and a drain electrode D located above the barrier layer 102. According to one embodiment, in order to contact the two-dimensional electron gas, etching or alloying reaction is performed, and the source electrode S and the drain electrode D (contact interface) may be below the surface of the barrier layer 102.

[0060] In this embodiment, the barrier layer 102 may include a groove, and a second gate G22 (such as a MIS gate) may be formed in the groove. According to one embodiment, the groove may further include a passivation layer 103, and the passivation layer 103 may be located between the side surface of the second gate G22 and the side wall of the groove, and / or between the bottom surface of the second gate G22 and the bottom surface of the groove.

[0061] According to one embodiment, the height difference between the bottom surface of the second gate G22 and the bottom surface of the first gate G21 may be 20 - 30 nm, and the second gate G22 may penetrate into the barrier layer 102, and even into the buffer layer 101, as long as it is ensured that the transistor can be normally turned on or off.

[0062] According to one embodiment, the width of the first gate G21 may be less than or equal to 100 nm; in particular, the width of G11 may be 40 nm or less.

[0063] According to one embodiment, when the relative dielectric constant of the passivation layer 103 is greater than or equal to 3.5, the preset horizontal distance between the first gate G21 and the second gate G22 may be less than 100 nm, and in particular, it may be 10 - 50 nm.

[0064] Figure 5 Shown is a schematic side cross-sectional view of an enhancement-mode gallium nitride power transistor according to an embodiment of the present application.

[0065] According to one embodiment, the gallium nitride power transistor may include, and the buffer layer 101 may include, for example, GaN or Al x Ga 1-x A combined layer of N.

[0066] According to one embodiment, the gallium nitride power transistor may further include a barrier layer 102 located above the buffer layer 101, which may include, for example, Al x Ga 1-x N.

[0067] According to one embodiment, the gallium nitride power transistor may further include a source electrode S and a drain electrode D located above the barrier layer 102. According to one embodiment, in order to contact the two-dimensional electron gas, etching or alloying reaction is performed, and the source electrode S and the drain electrode D (contact interface) may be below the surface of the barrier layer 102.

[0068] According to one embodiment, the gallium nitride power transistor may further include a passivation layer 103 located above the barrier layer 102 and surrounding the top surface and side surfaces of the first gate G21.

[0069] As shown in the figure, the transistor may include two second gates G22-1 and G22-2, which are respectively located between the first gate G21 and the source electrode S, and between G21 and the drain electrode D.

[0070] According to one embodiment, the widths of the two second gates G22-1 and G22-2 may be the same or different.

[0071] According to different embodiments, the width of the first gate G21 may be less than or equal to 100 nm. In particular, the width of G21 may be 40 nm or less. And when the relative dielectric constant of the passivation layer 103 is greater than or equal to 3.5, the preset horizontal distance between the two second gates G22-1 and G22-2 and the first gate G21 may be less than 100 nm. In particular, it may be 10 - 50 nm.

[0072] According to one embodiment, both of the two second gates G22-1 and G22-2 may be located in the grooves, or only one may be located in the grooves, or the groove depths where the two second gates are located may be different. According to one embodiment, the grooves may further include a passivation layer 103, and the passivation layer 103 may be located between the side surfaces of the second gates G22-1 and G22-2 and the side walls of the grooves, and / or between the bottom surfaces of the second gates G22-1 and G22-2 and the bottom surface of the grooves.

[0073] According to one embodiment, the height difference between the bottom surface of the second gate and the bottom surface of the first gate may be 20 - 30 nm. The second gate may penetrate into the barrier layer 102, and even into the buffer layer 101, as long as it ensures that the transistor can be normally turned on or off.

[0074] Figure 6 Shown is a schematic side cross-sectional view of an enhancement-mode gallium nitride power transistor according to an embodiment of the present application.

[0075] According to one embodiment, the gallium nitride power transistor may include a buffer layer 101, and the buffer layer 101 may include, for example, a combined layer of GaN or Al x Ga 1-x N.

[0076] According to one embodiment, the gallium nitride power transistor may further include a barrier layer 102 located above the buffer layer 101, which may include, for example, Al x Ga 1-x N.

[0077] According to one embodiment, the gallium nitride power transistor may further include a source electrode S and a drain electrode D located above the barrier layer 102. According to one embodiment, in order to contact the two-dimensional electron gas, etching or alloying reaction is performed, and the source electrode S and the drain electrode D (contact interface) may be below the surface of the barrier layer 102.

[0078] As shown in the figure, the transistor may include two first gates G21-1 and G21-2, which are respectively located between the second gate G22 and the source electrode S, and between G22 and the drain electrode D.

[0079] According to one embodiment, the gallium nitride power transistor may further include a passivation layer 103 located above the barrier layer 102 and surrounding the top and side surfaces of the first gates G21-1 and G21-2.

[0080] According to one embodiment, the widths of the two first gates G21-1 and G21-2 may be the same or different, and may be less than or equal to 100 nm. In particular, the widths of G21-1 and G21-2 may be 40 nm or less.

[0081] According to different embodiments, when the relative dielectric constant of the passivation layer 103 is greater than or equal to 3.5, the preset horizontal distance between the two first gates G21-1 and G21-2 and the second gate G22 may be less than 100 nm. In particular, it may be 10 - 50 nm. According to one embodiment, the second gate G22 may be located in a groove, and the depth of the groove may be 20 - 30 nm, and may penetrate into the barrier layer 102, or even into the buffer layer 101, as long as it ensures that the transistor can be normally turned on or off.

[0082] According to one embodiment, the groove may further include a passivation layer 103, and the passivation layer 103 may be located between the side surface of the second gate G22 and the side wall of the groove, and / or between the bottom surface of the second gate G22 and the bottom surface of the groove.

[0083] Figure 7 and Figure 8 Shown is a simulation diagram of the operating state of an enhancement-mode gallium nitride power transistor according to an embodiment of the present application.

[0084] When P-GaN is used as the gate in a gallium nitride power transistor, due to the PN junction included in the gate, various failure problems will occur when the gate voltage is switched; for a gallium nitride power transistor with an enhanced MIS gate, it is difficult to obtain an enhanced transistor with a stable positive threshold voltage because additional processing defects are usually introduced in the processing technology to achieve a relatively ideal threshold voltage (such as greater than 1.2V).

[0085] In the present application, the gallium nitride power transistor may include a first gate, such as a P-GaN gate, and a fixed voltage that keeps the channel below it cutoff, such as ground potential, may be always applied to the first gate, and the first gate is an enhanced gate. Since a voltage that satisfies the conduction of the P-GaN gate is not applied to the P-GaN gate, the failure problems caused by voltage switching of the P-GaN gate will not be triggered. This is very different from the existing gallium nitride power transistors. Although many existing gallium nitride power transistors include structures with multiple gates, the conduction or cutoff of the transistor is still determined by the P-GaN gate, or in other words, the power supply applied to the P-GaN gate needs to be switched when the transistor conducts and cuts off, which cannot avoid the failure problems caused by the P-GaN gate.

[0086] According to one embodiment, the gallium nitride power transistor disclosed in the present application may further include a second gate, such as an MIS gate. According to one embodiment, the MIS gate in this embodiment may be a depletion type or an enhanced type structure. The HEMT structure in this embodiment avoids the problem of unstable threshold voltage that needs to be faced when using only a traditional enhanced MIS gate structure to obtain an enhanced power transistor. In the present application, a stable positive threshold structure can be achieved by combining the second gate with the first gate. More importantly, the first gate (P-GaN gate) always receives a preset fixed voltage. When the second gate receives ground potential or other voltages less than the preset level (such as 0.5V), the channel under the second gate may be disconnected or may be conducting, but the transistor is still in the cutoff state, as Figure 7 shown, where VG1 is the first gate voltage and VG2 is the second gate voltage. This is because the barrier under the first gate is relatively high. Even if the barrier under the second gate is relatively high, and even if the channel under the second gate is conducting, since the channel under the first gate is cutoff, a continuous conducting channel between the source and the drain still cannot be formed.

[0087] According to one embodiment, when the second gate receives a voltage greater than or equal to a preset level voltage, such as a voltage in the range of 0.5 - 30 V, the channel under the second gate conducts. Since the width of the first gate is small enough and the distance between the first gate and the second gate is close enough, the second gate generates an electric field coupling effect on the first gate, reducing the barrier height under the first gate. As a result, the channel under the first gate also conducts, forming a continuously conducting channel between the source and the drain, and the transistor is turned on. As Figure 8 shown, where VG1 is the first gate voltage and VG2 is the second gate voltage.

[0088] That is to say, before the voltage on the second gate reaches, for example, 2 V, although the channel under the second gate may also conduct, due to the insufficient influence of the second gate on the barrier under the first gate, the channel under the first gate still does not conduct. Therefore, generally speaking, a continuously conducting channel cannot be formed between the source and the drain, and the gallium nitride power transistor remains in the off state.

[0089] According to one embodiment, when the first gate is grounded and a voltage not exceeding 30 V is applied to the second gate, the entire gallium nitride power transistor can also have a source-drain current density of > 1 mA / mm, that is, in the on state; when the second gate is also grounded, the first gate makes the source-drain current density of the overall gallium nitride power transistor < 1 μA / mm, that is, in the off state.

[0090] The above introduction is for the case where the first gate is always grounded. Of course, according to other embodiments, the preset fixed voltage can also be a positive voltage or a negative voltage. According to one embodiment, when the preset fixed voltage is a negative voltage, a greater voltage (relative to the range of 0.5 V to 30 V) needs to be applied to the second gate to turn on the power transistor; when the preset fixed voltage is a positive voltage and less than the threshold voltage corresponding to the first gate, a smaller voltage (relative to the range of 0.5 V to 30 V) only needs to be applied to the second gate to turn on the power transistor.

[0091] In the present application, the distance between the first gate and the second gate, as well as the material properties of the passivation layer between the first gate and the second gate, affect the coupling effect of the second gate on the first gate (P-GaN gate). As long as the second gate can generate a coupling effect on the first gate and the channel under it, the selection of the distance and the material between the two are within the protection scope of the present application.

[0092] Figure 9The figure shows the threshold voltage characteristic curve of an enhancement-mode gallium nitride power transistor with a P-GaN gate structure of different widths according to an embodiment of the present application. As shown in the figure, as the first gate width Lg continues to shorten, although the drain-source current when the transistor is turned on is large enough, there is also the disadvantage of a decrease in the transistor threshold voltage. Therefore, although the first gate width should be less than 100 nm, it should not be too low, for example, not less than 30 nm.

[0093] Figure 10 and Figure 11 The figure shows the transfer characteristic curve of an enhancement-mode gallium nitride power transistor according to an embodiment of the present application. Among them, the drain-source is 5V, and the test result graph of the source-drain current changing with the voltage difference between the second gate and the source, where Figure 10 the vertical axis of Figure 11 is a linear axis, Figure 10 and Figure 11 It can be seen from Figure 9 that the threshold voltage of the enhancement-mode gallium nitride power transistor of the present application can reach 2V, and can reach 4V by adjusting the structural parameters (such as the width of the P-GaN gate structure) (as shown in

[0094] ). Currently, the threshold voltage of common enhancement-mode P-GaN gate transistors is 1.5 - 1.7V. Therefore, the enhancement-mode gallium nitride power transistor of the present application has a higher threshold voltage, which is beneficial to preventing the transistor from being disturbed and mis-turning on in the off state. Figure 10 、 Figure 11 It can be seen from

[0095] Figure 12 that the current density of the enhancement-mode gallium nitride power transistor with a P-GaN gate of different widths according to an embodiment of the present application can reach the level of one to several hundred milliamperes per millimeter, and this level is also close to the current density of a normal GaN power transistor. It can be seen that the on-current ability of the enhancement-mode gallium nitride power transistor of the present application will not be affected by the gate structure optimization.

[0096] According to one embodiment, in order to achieve the high-voltage resistance effect, one or more of the electrodes in the present application may include field plates (such as the method adopted in conventional devices). However, since the design goal of the field plate is to withstand a relatively high voltage, such as in the range of 200V - 1200V, the design size, the horizontal and vertical distances from the channel under the P-GaN gate, the thickness or the type of the spacer dielectric have almost no impact on the critical channel under the P-GaN gate. Anyway, the field plate is not the gate electrode.

[0097] With the solution of the present application, since the first gate (P-GaN gate) does not perform switching operations, its adverse effects will not be introduced. At the same time, by adjusting the voltage on the second gate (such as a MIS gate), and using the coupling effect of the second gate on the first gate, the on or off state of the enhancement-mode gallium nitride power transistor of the present application is controlled.

[0098] The enhancement-mode gallium nitride power transistor provided by the present application adopts a unified gallium nitride process and is integrated. By combining the known MIS gate structure and P-GaN gate structure, and using the effect of horizontal electric field coupling, a novel combined gate is created. This novel gate structure achieves the comprehensive effect of the enhancement-mode transistor; during operation, it is not necessary to adjust the voltage of the P-GaN gate, thus avoiding the reliability problems of the P-GaN gate caused by repeated voltage increase and decrease.

[0099] The present application also provides an electronic device, including the enhancement-mode power transistor described in any one of the above.

[0100] The above embodiments are only for illustrating the present application and are not intended to limit the present application. Those of ordinary skill in the relevant technical fields can make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope of the disclosure of the present application.

Claims

1. An enhancement-mode gallium nitride power transistor, characterized in that include Buffer layer; a barrier layer located above the buffer layer; a source electrode and a drain electrode located above the barrier layer; at least one first gate located above the barrier layer, wherein the first gate comprises P-type gallium nitride and is an enhancement-mode gate; a passivation layer located above the barrier layer and surrounding the first gate; at least one second gate located in the passivation layer and maintaining a preset distance from the first gate; Wherein, no matter what state the transistor is in, the first gate is always configured to receive a first preset voltage, and the first preset voltage makes the lower channel non-conductive when the first gate acts on the lower channel alone; When the voltage received by the second gate configuration is greater than or equal to a second preset voltage, the channels under the first gate and under the second gate are turned on, otherwise the channel under the first gate is turned off.

2. The transistor according to claim 1, characterized in that When the dielectric constant of the passivation layer is greater than or equal to 3.5, the width of the first gate is less than or equal to 100 nm, and the preset distance is less than 100 nm.

3. The transistor according to claim 2, characterized in that The preset distance is 10-50 nm.

4. The transistor according to claim 1, characterized in that The second gate is located between the first gate and the source electrode and / or between the first gate and the drain electrode.

5. The transistor according to claim 1, characterized in that The first gate is located between the second gate and the source electrode and / or between the first gate and the drain electrode.

6. A transistor as claimed in any one of claims 1 to 5, characterized in that The barrier layer includes at least one groove, and the second gate is located in the groove.

7. The transistor according to claim 6, characterized in that The height difference between the bottom surface of the second gate and the bottom surface of the first gate is 20-30 nm.

8. The transistor according to claim 1, characterized in that The width of the first gate is greater than or equal to 30 nm and less than or equal to 40 nm.

9. The transistor according to claim 1, characterized in that The first preset voltage is a ground potential.

10. The transistor according to claim 1, characterized in that The second preset voltage is a voltage greater than or equal to 0.5V and less than or equal to 30V.

11. An electronic device, characterized in that The invention comprises an enhancement-mode gallium nitride power transistor as claimed in any one of claims 1 to 10.

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