Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof. Wherein the same hard mask layer is used during formation of some isolation structures (e.g., shallower shallow trench isolation structures) and during formation of additional isolation structures (e.g., shallow trench isolation structures), resulting in the isolation structures approximately flush with the level of the substrate in which the isolation structures are formed. That is, the step height of the isolation structure is reduced. Thus, the height of the portion of the gate extending over the isolation structure increases. The increase in the gate height results in an increase in the landing area of the contact, which helps to prevent leakage current, thereby improving the performance of an electronic device including the isolation structure.

Description

Technical Field

[0001] The invention relates to a semiconductor structure and a forming method thereof. Background Art

[0002] A power metal-oxide-semiconductor field-effect transistor (MOSFET) is a MOSFET designed to handle significant power levels (e.g., high voltage and / or high current). Power MOSFETs can be used in display drivers, power converters, motor controllers, and vehicle power devices, among other applications. One type of power MOSFET is the laterally diffused metal-oxide-semiconductor (LDMOS) transistor. LDMOS transistors exhibit high gain, high power output, and high efficiency at high frequencies, making LDMOS transistors often used with microwave and RF power amplifiers. Summary of the invention

[0003] As described in greater detail above, some embodiments described herein provide a semiconductor structure. The semiconductor structure includes a substrate. The semiconductor structure includes a shallow trench isolation structure formed in the substrate. The semiconductor structure includes a shallower shallow trench isolation structure formed in the substrate and producing an oxide definition region. The semiconductor structure includes a gate formed above the oxide definition region and partially overlapping the shallow trench isolation structure, the gate having a first height above the shallow trench isolation structure and a second height above the oxide definition region. The first height is approximately equal to the second height.

[0004] As described in greater detail above, some embodiments described herein provide a method. The method includes forming a hard mask layer over a substrate. The method includes forming one or more shallower shallow trench isolation structures in the substrate using the hard mask layer. The method includes forming shallow trench isolation structures in the substrate using the hard mask layer. The method includes performing chemical mechanical polishing on the shallow trench isolation structures. The method includes removing the hard mask layer. The method includes forming at least one gate over an oxide defined region formed by the shallower shallow trench isolation structures.

[0005] As described in greater detail above, some embodiments described herein provide a semiconductor structure. The semiconductor structure includes a substrate. The semiconductor structure includes a shallow trench isolation structure formed in the substrate, the shallow trench isolation structure having a step height in a range of 0.0 nanometers to approximately 2.0 nanometers relative to the substrate. The semiconductor structure includes a shallower shallow trench isolation structure formed in the substrate and producing an oxide definition region, the shallower shallow trench isolation structure having a step height in a range of 0.0 nanometers to approximately 2.0 nanometers relative to the substrate. The semiconductor structure includes a gate formed above the oxide definition region and partially overlapping the shallow trench isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with the attached Figure 1 When read together, the drawings or the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the size of various features can be increased or decreased arbitrarily for the clarity of discussion.

[0007] Figure 1 is a diagram of an example environment in which the systems and / or methods described herein may be implemented.

[0008] Figure 2 is a diagram of an example semiconductor structure described herein.

[0009] FIG. 3A to FIG. 3B is a diagram of an example semiconductor structure described herein.

[0010] Figure 4 is a diagram of an example semiconductor structure described herein.

[0011] FIG. 5A to FIG. 5I is a diagram of an exemplary embodiment described herein.

[0012] Figure 6 This article describes Figure 1 An example component diagram of one or more devices of FIG.

[0013] Figure 7 is a flow chart of an example process associated with forming the semiconductor structures described herein.

[0014] Description of Reference Numerals

[0015] 100: Environment

[0016] 102:Deposition tools

[0017] 104:Exposure Tools

[0018] 106: Developer Tools

[0019] 108: Etching tools

[0020] 110: Flattening tool

[0021] 112:Electroplating tools

[0022] 114: Photoresist removal tool

[0023] 116: Cleaning tools

[0024] 118: Wafer / die transfer tool

[0025] 200:Semiconductor components

[0026] 202, 404a, 404b: shallow trench isolation structure

[0027] 204a, 204b, 204c, 204d: shallower shallow trench isolation structure

[0028] 206, 206a, 206b, 206c, 206d, 206e, 206f, 206g, 206h: gate

[0029] 208, 208a, 208b: metal plug, gate contact

[0030] 210a, 210b: metal plug, source contact

[0031] 212a, 212b: metal plug, drain contact

[0032] 300, 350, 400: Cross-section

[0033] 302: substrate

[0034] 304: passivation layer

[0035] 306: Spacer

[0036] 352, 520: dielectric layer

[0037] 354:Metal plug

[0038] 402, 406, 406a, 406b: cushion layer

[0039] 408: pad layer

[0040] 500: Embodiment

[0041] 502: Hard mask layer

[0042] 504, 516: photoresist layer

[0043] 506a, 506b, 518: groove

[0044] 508: Additional pad layer

[0045] 510: Anti-reflection dielectric layer

[0046] 512: Intermediate anti-reflection layer

[0047] 514: Anti-reflective coating

[0048] 600: Device

[0049] 610: Bus

[0050] 620: Processor

[0051] 630: Memory

[0052] 640: Input component

[0053] 650: Output component

[0054] 660: Communication Components

[0055] 700: Craftsmanship

[0056] 710, 720, 730, 740, 750, 760: frame DETAILED DESCRIPTION

[0057] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0058] In addition, when a number or a range of numbers is described as "about," "approximate," etc., the term is intended to encompass numbers within a reasonable range taking into account variations that inherently occur during manufacturing as understood by those of ordinary skill in the art. For example, based on known manufacturing errors associated with manufacturing features having properties associated with the number, the number or range of numbers encompasses a reasonable range including the number, such as within + / - 10% of the number. For example, a material layer having a thickness of "about 5 nanometers" may encompass a range of sizes from 4.25 nanometers to 5.75 nanometers, where the manufacturing tolerance associated with the deposited material layer is known to those of ordinary skill in the art to be + / - 15%. Further, the present disclosure may repeat figure numerals and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0059] In some electronic devices, a laterally diffused metal oxide semiconductor (LDMOS) field effect transistor (FET) may be used. A shallow trench isolation (STI) structure may isolate different transistors in an LDMOS component. Additionally, in some LDMOS components, a dielectric (e.g., silicon oxide) may be inserted at a drift region of an oxide definition (OD) surface to maintain a higher breakdown voltage. This process forms a shallower shallow trench isolation (SSTI) structure. The gate of an LDMOS transistor may be formed to extend above an oxide definition region that is defined by an isolation structure.

[0060] The shallow trench isolation structure may extend beyond the horizontal plane of the substrate, which forms a shallow trench isolation structure. This extension may be referred to as a "step height". When a shallower shallow trench isolation structure is incorporated into the shallow trench isolation process, the step height of the shallow trench isolation structure is even greater. The step height of the shallow trench isolation structure reduces the gate height at the portion of the gate extending above the oxide definition region. The reduction in gate height results in a reduction in the landing area of ​​the contact, which may result in leakage current, thereby reducing the performance of the LDMOS device.

[0061] Some embodiments described herein provide techniques and devices for depositing additional hard mask material during the formation of an isolation structure (e.g., a shallower shallow trench isolation structure), which enables the same hard mask material to be reused during the formation of an additional isolation structure (e.g., a shallow trench isolation structure). As a result, the shallow trench isolation structure is substantially flush with the horizontal plane of the substrate on which the shallow trench isolation structure is formed. That is, the step height of the shallow trench isolation structure is reduced. Therefore, the height of the gate portion extending above the shallow trench isolation structure is increased. The increase in gate height results in an increase in the landing area of ​​the contact, which helps prevent leakage current, thereby improving the performance of an electronic device (e.g., an LDMOS component) including a shallow trench isolation structure.

[0062] Figure 1 1 is a diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown, environment 100 may include a plurality of semiconductor process tools 102 to 116 and a wafer / die transport tool 116. The plurality of semiconductor process tools 102 to 116 may include a deposition tool 102, an exposure tool 104, a developer tool 106, an etch tool 108, a planarization tool 110, a plating tool 112, a photoresist removal tool 114, a cleaning tool 116, and / or another type of semiconductor process tool. Among other examples, the tools included in example environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility, and / or a semiconductor manufacturing facility.

[0063] Deposition tool 102 is a semiconductor process tool that includes a semiconductor process chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma enhanced CVD (PECVD) tool, a low-pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of chemical vapor deposition. In some embodiments, deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or other types of PVD tools. In some embodiments, example environment 100 includes multiple different types of deposition tools 102. As used herein, "deposition tool 102" may refer to one or more deposition tools 102, one or more deposition tools 102 of the same type, and / or one or more deposition tools 102 of different types, among other examples.

[0064] The exposure tool 104 is a semiconductor process tool capable of exposing the photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep ultraviolet light source, an extreme ultraviolet light (EUV) source, and / or the like), an X-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. This pattern may include one or more semiconductor component layer patterns for forming one or more semiconductor components, may include patterns for forming one or more structures of a semiconductor component, may include patterns for etching various portions of a semiconductor component, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0065] The developer tool 106 is a semiconductor process tool capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developer tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by dissolving exposed or unexposed portions of the photoresist layer using a chemical developer.

[0066] The etching tool 108 is a semiconductor process tool of various types capable of etching a material of a substrate, wafer, or semiconductor component. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, etc. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove one or more specific amounts of the substrate. In some embodiments, the etching tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may include using an ionized gas to etch the one or more portions isotropically or directionally.

[0067] The planarization tool 110 is a semiconductor process tool capable of grinding or flattening the layers of a wafer or semiconductor component. For example, the planarization tool 110 may include a chemical mechanical polishing (CMP) tool and / or another type of planarization tool that grinds or flattens a layer or surface of a deposited or plated material. The planarization tool 110 may use a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing) to grind or flatten the surface of a semiconductor component. The planarization tool 110 may use abrasive and corrosive chemical slurry in combination with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor component). The polishing pad and the semiconductor component may be pressed together by a dynamic polishing head and fixed by a retaining ring. The dynamic polishing head may rotate with different rotation axes to remove material and flatten any irregular topography of the semiconductor component, thereby making the semiconductor component flat or planar.

[0068] The electroplating tool 112 is a semiconductor process tool capable of electroplating a substrate (e.g., a wafer, a semiconductor component, and / or the like) or a portion thereof with one or more metals. For example, the electroplating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound or alloy (e.g., a wafer, a semiconductor component, and / or the like) electroplating device, and / or other one or more electroplating devices of conductive materials, metals, and / or similar material types.

[0069] The photoresist removal tool 114 is a semiconductor processing tool capable of removing the remaining portion of the photoresist layer from the substrate after the etching tool 108 removes a portion of the substrate. For example, the photoresist removal tool 114 may use a chemical stripper and / or other techniques to remove the photoresist layer from the substrate.

[0070] Cleaning tool 116 is a semiconductor process tool capable of cleaning a substrate, wafer, or semiconductor component. For example, etching tool 108 may include a wet cleaning tool (e.g., using water), a dry cleaning tool (e.g., using plasma), etc. In some embodiments, cleaning tool 116 includes a chamber filled with a cleaning material, and the substrate is placed in the chamber for a specific period of time to clean the substrate (e.g., to remove organic materials and / or remove oxidized molecules, among other examples). In some embodiments, cleaning tool 116 may use plasma to clean the substrate isotropically or directionally.

[0071] The wafer / die transfer tool 118 may be included in a cluster tool or another type of tool including multiple process chambers, and may be configured to transfer substrates and / or semiconductor components between multiple process chambers, between a process chamber and a buffer, between a process chamber and an interface tool such as an equipment front end module (EFEM), and / or between a process chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), among other examples. In some embodiments, the wafer / die transfer tool 118 may be included in a multi-chamber (or cluster) deposition tool 102, which may include pre-clean process chambers (e.g., for cleaning or removing oxides, oxidation and / or other types of contamination or byproducts from substrates and / or semiconductor components) and types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations).

[0072] In some embodiments, one or more of the one or more semiconductor process tools 102 to 116 and / or the wafer / die transfer tool 118 may perform one or more semiconductor process operations described herein. For example, one or more of the one or more semiconductor process tools 102 to 116 and / or the wafer / die transfer tool 118 may form a hard mask layer over a substrate; form one or more shallower shallow trench isolation (SSTI) structures in the substrate using the hard mask layer; form shallow trench (STI) isolation structures in the substrate using the hard mask layer; perform chemical mechanical polishing on the shallow trench (STI) isolation structures; remove the hard mask layer; and form at least one gate over an oxide definition (OD) region through a plurality of shallower shallow trench (SSTI) isolation structures.

[0073] Figure 1The number and arrangement of devices shown are provided as one or more examples. In practice, there may be more than Figure 1 The devices shown may include additional devices, fewer devices, different devices, or devices in a different arrangement. Figure 1 Two or more of the components shown may be implemented in a single component, or Figure 1 A single component shown in the example environment 100 may be implemented as multiple distributed components. Additionally or alternatively, one set of components (eg, one or more components) of the example environment 100 may perform one or more functions described as being performed by another set of components of the example environment 100.

[0074] Figure 2 is a top view of a cross-section of an example semiconductor component 200 described herein. Semiconductor component 200 comprises an example of a semiconductor component such as a display driver, a power converter, a motor controller, a vehicle power component, or another type of semiconductor component including LDMOS.

[0075] like Figure 2 As shown, the exemplary semiconductor device 200 may include an isolation structure, such as a shallow trench isolation structure 202. The shallow trench isolation structure 202 may electrically isolate different transistors within the exemplary semiconductor device 200. Figure 4 As shown, the shallow trench isolation structure 202 may include a liner layer (e.g., an antireflective coating (ARC), such as a nitrogen-containing material, and / or a passivation layer, etc.) and a dielectric filler (e.g., an oxide material). In addition, the example semiconductor component 200 may include additional isolation structures, such as shallower shallow trench isolation structures 204a, 204b, 204c, and 204d that form oxide definition regions. The shallower shallow trench isolation structures 204a, 204b, 204c, and 204d may also include a liner layer and a dielectric filler, such as a combination of Figure 4 The shallower shallow trench isolation structures 204a, 204b, 204c and 204d have a smaller depth than the shallow trench isolation structure 202. That is, the shallow trench isolation structure 202 extends further into the substrate ( Figure 2 not shown).

[0076] The exemplary semiconductor device 200 also includes a plurality of gates 206. The exemplary semiconductor device 200 includes four gates (shown as gates 206a, 206d, 206e, and 206h) formed adjacent to the shallower shallow trench isolation structure and four gates (shown as gates 206b, 206c, 206f, and 206g) formed above the shallower shallow trench isolation structure. FIG. 3A to FIG. 3BAs shown, each gate 206 may include a crystalline layer and a spacer surrounding the periphery of the gate. In addition, each gate 206 may be connected to a metal plug 208 (eg, Figure 2 The gate 206 may be physically in contact with the plugs 208a and 208b in the example semiconductor device 200. Thus, the gate 206 may control the flow of current between the source region and the drain region of the example semiconductor device 200. For example, the gate 206c may be energized (e.g., by applying a voltage or current to the metal plug 208b) to cause a conductive channel to be formed between the source region and the drain region connected by the gate 206c. The conductive channel may be removed or closed by de-energizing the gate 206c, which may block and / or prevent the flow of photocurrent between the source region and the drain region connected by the gate 206c.

[0077] like Figure 2 As further shown, the source region of the exemplary semiconductor device 200 may be connected to a source contact 210 (eg, Figure 2 Similarly, the drain region of the exemplary semiconductor device 200 may be physically contacted with the drain contact 212 (eg, Figure 2 The metal plugs 212a and 212b) in the embodiment of the present invention are in physical contact with each other.

[0078] As mentioned above, providing Figure 2 As an example. Other examples can be found in Figure 2 Other examples may include Figure 2 The example semiconductor device 200 shown may have additional gates or fewer gates. Similarly, other examples may include Figure 2 The exemplary semiconductor device 200 shown may include additional source contacts or fewer source contacts, and / or may include additional source contacts or fewer source contacts than the exemplary semiconductor device 200 shown. Figure 2 The exemplary semiconductor device 200 shown has additional drain contacts or fewer drain contacts than the exemplary semiconductor device 200 .

[0079] Figure 3A is an example semiconductor component along the Figure 2 The cross-section 300 is shown along the Y-section line. Figure 3A In the present invention, the gate of the LDMOS component has not been subjected to chemical mechanical polishing. In addition, the gate contact of the LDMOS component has not yet been formed.

[0080] like Figure 3AAs shown, the shallow trench isolation structure 202 is formed in a substrate 302. The substrate 302 may include a semiconductor die substrate, a semiconductor wafer, a stacked semiconductor wafer, or another type of substrate in which a semiconductor pixel may be formed. For example, the substrate 302 may be made of silicon (Si) (e.g., a silicon substrate), a material including silicon, a III-V compound semiconductor material (e.g., gallium arsenide (GaAs)), silicon on insulator (SOI), or another type of semiconductor material. In some embodiments, the substrate 302 is formed of a doped material such as doped silicon (e.g., a p-type (p-doped) material or an n-type (n-doped) material).

[0081] like Figure 3A As further shown, the gate 206 may be at least partially formed above the shallow trench isolation structure 202. The gate 206 may include a metal and / or a crystalline material. Because the shallow trench isolation structure 202 has a step height of less than 2 nanometers (nm), as shown in FIG. Figure 4 As described above, the gate 206 has a relatively uniform height above the shallow trench isolation structure 202 and the substrate 302, as described in more detail in conjunction with Figure 3B .

[0082] like Figure 3A As further shown, a passivation layer 304 can be formed over the gate 206. For example, the passivation layer 304 can protect portions of the gate 206 during the formation of the gate contact, such as in conjunction with Figure 3B In addition, spacers 306 (e.g., sidewall spacers) may be formed around gate 206. Spacers 306 may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxycarbide (SiOC), and / or silicon oxycarbonitride (SiOCN), etc. Spacers 306 may also protect portions of gate 206 during formation of a gate contact, such as in combination with Figure 3B described.

[0083] Figure 3B is an example semiconductor component along the Figure 3A A cross-sectional view 350 is shown along the Y-section line. Figure 3B In the embodiment, the gate of the LDMOS component has been subjected to chemical mechanical polishing, and a gate contact of the LDMOS component has been formed.

[0084] like Figure 3B As shown, dielectric layer 352 has been formed over passivation layer 304, gate 206, and substrate 302 (and shallow trench isolation structure 202). In addition, gate contact 208 has been formed in dielectric layer 352. Gate contact 208 may be an interconnect line and / or a metal plug (e.g., as combined with Figure 2 The gate contact 208 may be in physical contact with the gate 206 (e.g., through the passivation layer 304), which allows the gate contact 208 to conduct voltage to the gate 206 and energize the gate 206. The gate contact 208 may also be in physical contact with the metal plug 354, further connecting the gate 206 to an interconnect region (e.g., connecting the semiconductor component to a package).

[0085] like Figure 3B As further shown, the gate 206 has a first height (e.g., represented by h1) above the shallow trench isolation structure and a second height (e.g., represented by h2) above the substrate 302. The gate 206 also has a shallower shallow trench isolation structure ( Figure 3B The first height h1 and the second height h2 are approximately equal. As used herein, "approximately equal" means equal within an error range (e.g., an error range of 5% or less). Therefore, the difference between the first height h1 and the second height h2 satisfies a threshold value having a value corresponding to the error range.

[0086] Since the step height of the shallow trench isolation structure 202 is less than 2 nanometers, the gate 206 presents an increased height above the shallow trench isolation structure 202. Therefore, the first height h1 and the second height h2 are approximately equal, which results in an increased landing area of ​​the gate contact 208. The increased landing area helps prevent leakage current and thus improves the performance of the exemplary semiconductor device.

[0087] As mentioned above, providing FIG. 3A to FIG. 3B As an example. Other examples can be found in FIG. 3A to FIG. 3B For example, the spacer 306 may be omitted from the exemplary semiconductor device.

[0088] Figure 4 is an example semiconductor component along the Figure 2 The cross-section 400 is shown in FIG. Figure 4 In the embodiment, the isolation structure of the LDMOS component has been formed, but the gate of the LDMOS component has not yet been formed.

[0089] like Figure 4As shown, the substrate 302 of the exemplary semiconductor device includes a shallow trench isolation structure 202 and shallower shallow trench isolation structures 404a and 404b. The shallower shallow trench isolation structures 404a and 404b are similar to the shallow trench isolation structure 202, but do not extend as deep into the substrate 302 as the shallow trench isolation structure 202. Therefore, in some embodiments, the shallow trench isolation structure 202 can have a higher aspect ratio than the shallower shallow trench isolation structures 404a and 404b, such as Figure 4 shown.

[0090] like Figure 4 As further shown, the shallow trench isolation structure 202 includes a liner layer 402. In addition, the shallower shallow trench isolation structures 404a and 404b include liner layers 406a and 406b, respectively. Figure 4 , the pad layer 408 has not been removed; therefore, the step height (e.g., represented by h3) of the shallow trench isolation structure 202 and the shallower shallow trench isolation structures 404a and 404b is measured through the pad layer 408 (i.e., from the top surface of the substrate 302). Therefore, the step height represents how far the shallow trench isolation structure 202 and the shallower shallow trench isolation structures 404a and 404b extend (or extend out) above the substrate 302. The step height h3 ranges from 0.0 nanometers to approximately 2.0 nanometers. The shallow trench isolation structure 202 and the shallower shallow trench isolation structures 404a and 404b are formed to have a step height of no greater than 2.0 nanometers to prevent the step height from reducing the height of the gate above the shallow trench isolation structure 202 and / or the shallower shallow trench isolation structures 404a and 404b (e.g., as combined Fig.5I A larger step height will reduce the height of the gate, which in turn will result in a reduced landing area for the gate contact and reduced leakage current and performance of the exemplary semiconductor device.

[0091] In addition, the step height of the shallow trench isolation structure 202 is approximately equal to the step height of the shallower shallow trench isolation structures 404a and 404b (ie, both are composed of Figure 4 denoted by h3 in FIG. 1 ). A shallow trench isolation structure 202 and shallower shallow trench isolation structures 404a and 404b having the same hard mask layer are formed (for example, as combined with Figures 5A to 5F Different hard mask layers will result in different step heights, and will generally result in a step height of the shallow trench isolation structure 202 greater than 2.0 nanometers.

[0092] As mentioned above, providing Figure 4 As an example. Other examples can be found in Figure 4 Different from the above. Figure 4Other examples may include additional shallower shallow trench isolation structures compared to the illustrated example semiconductor structure. Additionally or alternatively, other examples may omit the liner layer 402 and / or the liner layers 406a and 406b.

[0093] FIG. 5A to FIG. 5I is a diagram of an example embodiment 500 described herein. Example embodiment 500 may be an example process for forming example semiconductor component 200 described herein. Example semiconductor component 200 may include a display driver, a power converter, a motor controller, a vehicle power component, or another type of semiconductor component including LDMOS.

[0094] like Figure 5A As shown, an exemplary process for forming a semiconductor component can be performed in conjunction with a substrate 302. The substrate 302 can include a semiconductor die substrate, a semiconductor wafer, a stacked semiconductor wafer, or other substrate types that can form a semiconductor pixel. In some embodiments, the substrate 302 is formed of a doped material (e.g., a p-type material or an n-type material) such as doped silicon.

[0095] like Figure 5A As further shown, example processes may be performed in conjunction with a pad layer 408. For example, deposition tool 102 may form pad layer 408 over and / or on the front side surface of substrate 302. In some embodiments, deposition tool 102 uses a spin-coating technique, a chemical vapor deposition technique, a physical vapor deposition technique, an atomic layer deposition technique, and / or other deposition techniques to form pad layer 408. Pad layer 408 may include an oxide material and / or other material types that protect substrate 302 during subsequent processes.

[0096] like Figure 5A As further shown, the example process can be performed in conjunction with a hard mask layer 502. For example, the deposition tool 102 can form the hard mask layer 502 above and / or on the front side surface of the substrate 302 and the pad layer 408. In some embodiments, the deposition tool 102 uses a spin coating technique, a chemical vapor deposition technique, a physical vapor deposition technique, an atomic layer deposition technique, and / or other deposition techniques to form the hard mask layer 502. The hard mask layer 502 can include silicon nitride (SiN) and / or another type of mask layer. The hard mask layer 502 can have a thickness ranging from approximately To approximate The height selection of not more than 1000 angstroms ensures that the hard mask layer 502 can be removed without a prolonged etching process (e.g., as combined with Figure 5HThe extended etching process will damage the isolation structure formed using the hard mask layer 502. The height selection of at least 500 angstroms ensures that the hard mask layer 502 will remain until the isolation structure is formed. If the hard mask layer 502 is inadvertently etched before the isolation structure is completed, the isolation structure will be damaged.

[0097] like Figure 5A As further shown, the exemplary process can be performed in conjunction with a photoresist (PR) layer 504. For example, the deposition tool 102 can form the photoresist layer 504 above and / or on the front side surfaces of the substrate 302, the pad layer 408, and the hard mask layer 502. In some embodiments, the deposition tool 102 uses a spin coating technique, a chemical vapor deposition technique, a physical vapor deposition technique, an atomic layer deposition technique, and / or other deposition techniques to form the photoresist layer 504. The photoresist layer 504 may include tetraethyl orthosilicate (TEOS) oxide and / or another type of photoresist material. The photoresist layer 504 may have a height in a range from approximately 400 angstroms to approximately 800 angstroms. The height is selected to be no more than 800 angstroms to ensure that the photoresist layer 504 can be removed without a prolonged etching process (for example, as combined with Figure 5B The extended etching process will damage the substrate 302. The height selection of at least 400 angstroms ensures that the photoresist layer 504 is large enough to be patterned during the etching of the recesses into the substrate 302 (e.g., as combined with Figure 5B If the photoresist layer 504 is patterned incorrectly, the substrate 302 will be damaged.

[0098] like Figure 5B As shown, recesses 506a and 506b may be formed in substrate 302. In an embodiment, photoresist layer 504 may be patterned (e.g., by exposing photoresist layer 504 to a radiation source via exposure tool 104 to form a pattern on photoresist layer 504), a portion of photoresist layer 504 may be etched to expose the pattern (e.g., by developing and removing a portion of photoresist layer 504 via developer tool 106), and recesses 506a and 506b may be formed (e.g., by etching tool 108 using a wet etching technique, a dry etching technique, a plasma enhanced etching technique, and / or another type of etching technique). In addition, as shown in FIG. Figure 5B As shown, the photoresist layer 504 can be removed. For example, after forming the recesses 506a and 506b, the photoresist removal tool 114 can remove the remaining portions of the photoresist layer 504 (eg, using a chemical stripper, a plasma asher, and / or other techniques).

[0099] like Figure 5CAs shown, liner layers 406a and 406b may be formed in recesses 506a and 506b, respectively. For example, deposition tool 102 may form liner layers 406a and 406b using a conformal technique such that liner layers 406a and 406b are formed only on exposed surfaces of substrate 302 (and not on exposed surfaces of pad layer 408 or hard mask layer 502). In some embodiments, before forming liner layers 406a and 406b, cleaning tool 116 may clean recesses 506a and 506b (e.g., using a combination of acid, hydrogen peroxide, and deionized water, etc.).

[0100] like Figure 5C As further shown, dielectric material may be formed in recesses 506a and 506b to form shallower shallow trench isolation structures 404a and 404b, respectively. In some embodiments, deposition tool 102 uses a spin coating technique, a chemical vapor deposition technique, a physical vapor deposition technique, an atomic layer deposition technique, and / or another deposition technique to form shallower shallow trench isolation structures 404a and 404b. Because dielectric material may overflow recesses 506a and 506b, planarization tool 110 may perform chemical mechanical polishing on shallower shallow trench isolation structures 404a and 404b to remove excess dielectric material. Chemical mechanical polishing may also cause "dishing" of shallower shallow trench isolation structures 404a and 404b, such as Figure 5C Specifically, the top surfaces of the shallower shallow trench isolation structures 404a and 404b may be uneven because the edges of the shallower shallow trench isolation structures 404a and 404b are higher than the middles of the shallower shallow trench isolation structures 404a and 404b.

[0101] like Figure 5D As shown, multiple layers may be formed over the hard mask layer 502 and the shallower shallow trench isolation structures 404a and 404b. An additional pad layer 508 may be formed. For example, the deposition tool 102 may form the additional pad layer 508 over and / or on the front surface of the substrate 302, the pad layer 408, the hard mask layer 502, and the shallower shallow trench isolation structures 404a and 404b.

[0102] An anti-reflection dielectric (ARD) layer 510 may also be formed. For example, deposition tool 102 may form ARD layer 510 above and / or on the front surface of substrate 302, pad layer 408, hard mask layer 502, shallower shallow trench isolation structures 404a and 404b, and additional pad layer 508. ARD layer 510 may have a height ranging from approximately 500 angstroms to approximately 1400 angstroms. The height is selected to be no greater than 1400 angstroms to ensure that ARD layer 510 can be removed (e.g., as in combination with Figure 5E The extended etching process may damage the shallower shallow trench isolation structures 404a and 404b. The height selection of at least 500 angstroms ensures that the anti-reflective dielectric layer 510 is large enough to prevent light self-interference during patterning of the photoresist layer 516 (e.g., as combined with Figure 5E The interference of light may cause shallow trench isolation structures to be formed at the wrong locations in the substrate 302 (e.g., as shown in FIG. Fig. 5F described above).

[0103] An intermediate anti-reflective layer 512 may also be formed. For example, the deposition tool 102 may form the intermediate anti-reflective layer 512 above and / or on the front surface of the substrate 302, the pad layer 408, the hard mask layer 502, the shallower shallow trench isolation structures 404a and 404b, the additional pad layer 508, and the anti-reflective dielectric layer 510. The intermediate anti-reflective layer 512 may be formed of silicon oxynitride (SiON) and / or another similar material. The intermediate anti-reflective layer 512 may have a height in a range from approximately 200 angstroms to approximately 300 angstroms. The height selection of not more than 300 angstroms ensures that the intermediate anti-reflective layer 512 can be removed without a prolonged etching process (e.g., as in combination with Figure 5E The extended etching process may damage the shallower STI structures 404a and 404b. The height selection of at least 200 angstroms ensures that the intermediate anti-reflective layer 512 is large enough to prevent interference of light during patterning of the photoresist layer 516 (e.g., as combined with Figure 5E The interference of light may cause shallow trench isolation structures to be formed at the wrong locations in the substrate 302 (e.g., as shown in FIG. Fig. 5F described above).

[0104] An anti-reflective coating (ARC) 514 may also be formed. For example, deposition tool 102 may form ARC 514 over and / or on the front side surfaces of substrate 302, pad layer 408, hard mask layer 502, shallower shallow trench isolation structures 404a and 404b, additional pad layer 508, anti-reflective dielectric layer 510, and intermediate anti-reflective layer 512. Anti-reflective coating 514 may have a height in a range from approximately 300 angstroms to approximately 600 angstroms. The height selection of no more than 600 angstroms ensures that anti-reflective coating 514 may be removed without a prolonged etching process (e.g., as in combination with Figure 5E The extended etching process may damage the shallower STI structures 404a and 404b. The height selection of at least 300 angstroms ensures that the anti-reflective coating 514 is large enough to prevent interference of light during patterning of the photoresist layer 516 (e.g., as combined with Figure 5E The interference of light may cause shallow trench isolation structures to be formed at the wrong locations in the substrate 302 (e.g., as shown in FIG. Fig. 5F described above).

[0105] A photoresist layer 516 may also be formed. For example, the deposition tool 102 may form the photoresist layer 516 over and / or on the front side surfaces of the substrate 302, the pad layer 408, the hard mask layer 502, the shallower shallow trench isolation structures 404a and 404b, the additional pad layer 508, the anti-reflective dielectric layer 510, the intermediate anti-reflective layer 512, and the anti-reflective coating layer 514. In some embodiments, the deposition tool 102 forms the photoresist layer 516 using a spin coating technique, a chemical vapor deposition technique, a physical vapor deposition technique, an atomic layer deposition technique, and / or other deposition techniques. The photoresist layer 516 may have a height in the range of about 500 angstroms to about 1000 angstroms. The height is selected to be no more than 1000 angstroms to ensure that the photoresist layer 516 can be removed without a prolonged etching process (e.g., as combined with Figure 5E The extended etching process may damage the shallower STI structures 404a and 404b. The height selection of at least 500 angstroms ensures that the photoresist layer 516 is large enough to be patterned during the etching of the recesses into the substrate 302 (e.g., as combined with Figure 5E If the photoresist layer 516 is incorrectly patterned, the substrate 302 will be damaged.

[0106] like Figure 5EAs shown, recess 518 may be formed in substrate 302. In an embodiment, photoresist layer 516 may be patterned (e.g., by exposing photoresist layer 516 to a radiation source via exposure tool 104 to form a pattern on photoresist layer 516), portions of photoresist layer 516 may be etched to expose the pattern (e.g., by developing and removing portions of photoresist layer 516 via developer tool 106), and recess 518 may be formed (e.g., by etching tool 108 using a wet etching technique, a dry etching technique, a plasma enhanced etching technique, and / or another type of etching technique). Recess 518 may surround shallower shallow trench isolation structures 404a and 404b in substrate 302, thereby forming a recess 518 in substrate 302. Figure 5E In addition, as shown in the cross-sectional view of Figure 5E As shown, the photoresist layer 516 can be removed. For example, after forming the recess 518, the photoresist removal tool 114 can remove the remaining portion of the photoresist layer 516 (e.g., using a chemical stripper, a plasma asher, and / or other techniques). Figure 5E As shown, the anti-reflective dielectric layer 510, the intermediate anti-reflective layer 512, and the anti-reflective coating layer 514 may be removed. The additional pad layer 508 may also be removed, and the hard mask layer 502 may be pulled back. Figure 5E As shown, “pulling back” the hard mask layer 502 causes the recess 518 to be wider at the hard mask layer 502 than at the pad layer 408 .

[0107] like Fig. 5F As shown, the liner layer 402 may be formed in the recess 518. For example, the deposition tool 102 may form the liner layer 402 using a conformal technique such that the liner layer 402 is formed only on the exposed surface of the substrate 302 (and not on the exposed surfaces of the pad layer 408, the hard mask layer 502, or the shallower shallow trench isolation structures 404a and 404b). In some embodiments, the cleaning tool 116 may clean the recess 518 (e.g., using a combination of acid, hydrogen peroxide, and deionized water, etc.) before forming the liner layer 402.

[0108] like Fig. 5F As further shown, a dielectric material may be formed in the recess 518 to form the shallow trench isolation structure 202. In some embodiments, the deposition tool 102 uses a spin coating technique, a chemical vapor deposition technique, a physical vapor deposition technique, an atomic layer deposition technique, and / or other deposition techniques. Fig. 5F As shown, the dielectric material may overflow the groove 518. Figure 5GAs shown, the planarization tool 110 can perform chemical mechanical polishing on the shallow trench isolation structure 202 to remove excess dielectric material. Chemical mechanical polishing may also cause "dishing" of the shallow trench isolation structure 202, such as Figure 5G Specifically, the top surface of the shallow trench isolation structure 202 may be uneven because the edge of the shallow trench isolation structure 202 is higher than the middle of the shallow trench isolation structure 202 .

[0109] like Figure 5H As shown, the hard mask layer 502 may be removed (e.g., using hydrofluoric acid (HF) etching and / or another type of wet etching). In addition, an oxide definition region may be formed over the shallower shallow trench isolation structures 404a and 404b (e.g., using ion deposition). Figure 5H As further shown, pad layer 408 may be removed.

[0110] like Fig.5I As shown, gates 206a and 206b may be formed on shallower shallow trench isolation structures 404a and 404b, respectively. Fig.5I , but an additional gate may be formed partially on the shallow trench isolation structure (eg, as combined with Figure 2 , Figure 3A and Figure 3B The gates 206a and 206b may be formed with spacers 306a and 306b, respectively. A dielectric layer 520 may be formed to cover the gates 206a and 206b (as well as the substrate 302, the shallower shallow trench isolation structures 404a and 404b, and the exposed surfaces of the shallow trench isolation structures 202). In some embodiments, the deposition tool 102 forms the dielectric layer 520 using a spin coating technique, a chemical vapor deposition technique, a physical vapor deposition technique, an atomic layer deposition technique, and / or another deposition technique.

[0111] As mentioned above, providing FIG. 5A to FIG. 5I As an example. Other examples can be found in FIG. 5A to FIG. 5I Other examples may include a bottom layer (BL) and a middle layer (ML) used in combination with the photoresist layer 504 and the hard mask layer 502. Additionally or alternatively, other examples may omit the spacers 306a and 306b.

[0112] Figure 6 is a diagram of example components of the device 600 described herein. In some embodiments, one or more of the plurality of semiconductor process tools 102 to 116 and / or the wafer / die transport tool 118 may include one or more devices 600 and / or one or more components of the device 600. Figure 6As shown, device 600 may include a bus 610 , a processor 620 , a memory 630 , an input component 640 , an output component 650 , and a communication component 660 .

[0113] The bus 610 may include one or more components that enable wired and / or wireless communications between the various components of the device 600. ... Figure 6 Two or more components of a computer programmable logic device are coupled together, for example, via operational coupling, communication coupling, electronic coupling, and / or electrical coupling. Processor 620 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and / or another type of processing component. Processor 620 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 620 may include one or more processors that can be programmed to perform one or more operations or processes described elsewhere herein.

[0114] The memory 630 may include volatile and / or non-volatile memory. For example, the memory 630 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 630 may include internal memory (e.g., RAM, ROM, or hard disk) and / or removable memory (e.g., removable via a universal serial bus connection). The memory 630 may be a non-transitory computer-readable medium. The memory 630 may store information related to the operation of the device 600, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, the memory 630 may include, for example, one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 620) via the bus 610.

[0115] Input components 640 can enable device 600 to receive inputs such as user input and / or sense inputs, for example, input components 640 can include touch screens, keyboards, keypads, mice, buttons, microphones, switches, sensors, GPS sensors, GNSS sensors, accelerometers, gyroscopes, and / or actuators; output components 650 can enable device 600 to provide outputs, for example, via displays, speakers, and / or light-emitting diodes; communication components 660 can enable device 600 to communicate with other devices via wired connections and / or wireless connections. For example, communication components 660 can include receivers, transmitters, transceivers, modems, network interface cards, and / or antennas.

[0116] Device 600 can perform one or more operations or processes described herein. For example, a non-temporary computer-readable medium (e.g., memory 630) can store a set of instructions (e.g., one or more instructions or program codes) for execution by processor 620. Processor 620 can execute a set of instructions to perform one or more operations or processes described herein. In some embodiments, execution of the group of instructions by one or more processors 620 causes one or more processors 620 and / or device 600 to perform one or more operations or processes described herein. In some embodiments, hard-wired circuits can be used to replace instructions or to perform one or more operations or processes described herein in combination with instructions. Additionally or alternatively, processor 620 can be set to perform one or more operations or processes described herein. Therefore, the implementation described herein is not limited to any particular combination of hardware circuits and software.

[0117] Figure 6 The number and arrangement of the various components shown are provided as examples. Device 600 may include Figure 6 Additional components, fewer components, different components, or differently arranged components than those shown. Additionally or alternatively, one set of components (e.g., one or more components) of device 600 can perform one or more functions described as being performed by another set of components of device 600.

[0118] Figure 7 FIG. 7 is a flow chart of an example process 700 associated with forming the isolation structures described herein. In some embodiments, one or more semiconductor process tools (eg, one or more of semiconductor process tools 102 to 114) are used to perform Figure 7 Additionally or alternatively, Figure 7 One or more process blocks of may be performed using one or more components of the device 600 , such as the processor 620 , the memory 630 , the input component 640 , the output component 650 , and / or the communication component 660 .

[0119] like Figure 7 As shown, process 700 may include forming a hard mask layer over a substrate (block 710). For example, one or more of semiconductor process tools 102-116 may form hard mask layer 502 over substrate 302, as described herein.

[0120] like Figure 7 As further shown, the process 700 may include forming one or more shallower shallow trench isolation structures in the substrate using the hard mask layer (block 720). For example, one or more of the semiconductor process tools 102 to 116 may be used to form one or more shallower shallow trench isolation structures 404 in the substrate 302 using the hard mask layer 502, as described herein.

[0121] like Figure 7 As further shown, process 700 may include forming a shallow trench isolation structure in the substrate using the hard mask layer (block 730). For example, one or more of semiconductor process tools 102 to 116 may be used to form shallow trench isolation structure 202 in substrate 302 using hard mask layer 502, as described herein.

[0122] like Figure 7 As further shown, process 700 may include performing chemical mechanical polishing on the shallow trench isolation structure (block 740). For example, one or more of the plurality of semiconductor process tools 102-116 may be used to perform chemical mechanical polishing on the shallow trench isolation structure 202, as described herein.

[0123] like Figure 7 As further shown, the process 700 may include removing the hard mask layer (block 750). For example, one or more of the semiconductor process tools 102-116 may be used to remove the hard mask layer 502, as described herein.

[0124] like Figure 7 As further shown, the process 700 may include forming at least one gate 206 above the oxide defined region formed by the shallower shallow trench isolation structure (block 760). For example, one or more of the semiconductor process tools 102 to 116 may be used to form at least one gate 206 above the oxide defined region formed by the shallower shallow trench isolation structure 404, as described herein.

[0125] Process 700 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or other processes described elsewhere herein.

[0126] In a first embodiment, forming the hard mask layer 502 includes forming the hard mask layer 502 to a height in a range of approximately 500 angstroms to approximately 1000 angstroms.

[0127] In the second embodiment, alone or in combination with the first embodiment, the process 700 includes forming a pad layer 408 between the substrate 302 and the hard mask layer 502. The process 700 may also include removing the pad layer 408 after removing the hard mask layer.

[0128] In the third embodiment, alone or in combination with one or more of the first and second embodiments, forming one or more shallower shallow trench isolation structures 404 includes forming one or more recesses 506 in the substrate 302, and filling the one or more recesses 506 with a dielectric material to form the one or more shallower shallow trench isolation structures 404. Forming the one or more shallower shallow trench isolation structures 404 may further include forming one or more liner layers 406 in the one or more recesses 506 before filling the one or more recesses 506.

[0129] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, forming the shallow trench isolation structure 202 includes forming a recess 518 in the substrate 302 and filling the recess 518 with a dielectric material to form the shallow trench isolation structure 202. Forming the shallow trench isolation structure 202 may also include forming a liner layer 402 in the recess 518 before filling the recess 518.

[0130] Although Figure 7 An example block diagram of process 700 is shown, but in some embodiments, process 700 includes Figure 7 Additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in the process 700. Additionally or alternatively, blocks of two or more of the processes 700 may be performed in parallel.

[0131] In this way, during the formation of some isolation structures (e.g., shallower shallow trench isolation structures) and during the formation of additional isolation structures (e.g., shallow trench isolation structures), the same hard mask layer is used, resulting in the isolation structure being approximately flush with the horizontal plane of the substrate in which the isolation structure is formed. That is, the step height of the isolation structure is reduced. As a result, the height of the portion of the gate extending above the isolation structure is increased. The increase in the gate height results in an increase in the landing area of ​​the contact, which helps prevent leakage current, thereby improving the performance of the electronic device including the isolation structure.

[0132] As described in greater detail above, some embodiments described herein provide a semiconductor structure. The semiconductor structure includes a substrate. The semiconductor structure includes a shallow trench isolation structure formed in the substrate. The semiconductor structure includes a shallower shallow trench isolation structure formed in the substrate and producing an oxide definition region. The semiconductor structure includes a gate formed above the oxide definition region and partially overlapping the shallow trench isolation structure, the gate having a first height above the shallow trench isolation structure and a second height above the oxide definition region. The first height is approximately equal to the second height.

[0133] As described in greater detail above, some embodiments described herein provide a method. The method includes forming a hard mask layer over a substrate. The method includes forming one or more shallower shallow trench isolation structures in the substrate using the hard mask layer. The method includes forming shallow trench isolation structures in the substrate using the hard mask layer. The method includes performing chemical mechanical polishing on the shallow trench isolation structures. The method includes removing the hard mask layer. The method includes forming at least one gate over an oxide defined region formed by the shallower shallow trench isolation structures.

[0134] As described in greater detail above, some embodiments described herein provide a semiconductor structure. The semiconductor structure includes a substrate. The semiconductor structure includes a shallow trench isolation structure formed in the substrate, the shallow trench isolation structure having a step height in a range of 0.0 nanometers to approximately 2.0 nanometers relative to the substrate. The semiconductor structure includes a shallower shallow trench isolation structure formed in the substrate and producing an oxide definition region, the shallower shallow trench isolation structure having a step height in a range of 0.0 nanometers to approximately 2.0 nanometers relative to the substrate. The semiconductor structure includes a gate formed above the oxide definition region and partially overlapping the shallow trench isolation structure.

[0135] As used herein, “satisfying a threshold” may mean greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, etc., depending on the context.

[0136] The above overview of features and embodiments is intended to enable those of ordinary skill in the art to better understand aspects of the present invention. Those of ordinary skill in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. Those of ordinary skill in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A shallow trench isolation structure is formed in the substrate; A shallower shallow trench isolation structure is formed in the substrate and creates an oxide defined region; as well as A gate is formed above the oxide definition region and partially overlaps the shallow trench isolation structure, wherein the gate has a first height above the shallow trench isolation structure and a second height above the oxide definition region, and the first height is equal to the second height.

2. The semiconductor structure according to claim 1, characterized in that: Also includes: A source contact physically contacts a source region adjacent to the shallow trench isolation structure.

3. The semiconductor structure according to claim 1, characterized in that: Also includes: The drain contact physically contacts the drain region adjacent to the shallower shallow trench isolation structure.

4. The semiconductor structure according to claim 1, characterized in that: The shallow trench structure includes a liner layer.

5. A method for forming a semiconductor, characterized in that: include: forming a hard mask layer over the substrate; forming one or more shallower shallow trench isolation structures in the substrate using the hard mask layer; forming a shallow trench isolation structure in the substrate using the hard mask layer; performing chemical mechanical polishing on the shallow trench isolation structure; removing the hard mask layer; as well as At least one gate is formed over an oxide defined region formed by a shallower shallow trench isolation structure.

6. The method according to claim 5, characterized in that The forming of the hard mask layer comprises: The hard mask layer is formed to have a height in a range of 500 angstroms to 1000 angstroms.

7. The method according to claim 5, characterized in that Also includes: A pad layer is formed between the substrate and the hard mask layer.

8. The method according to claim 7, characterized in that Also includes: The pad layer is removed after the hard mask layer is removed.

9. A semiconductor structure, characterized in that: include: substrate; A shallow trench isolation structure is formed in the substrate, wherein the shallow trench isolation structure has a step height in the range of 0.0 nanometers to 2.0 nanometers relative to the substrate; A shallower shallow trench isolation structure is formed in the substrate and creates an oxide defined region, wherein the shallower shallow trench isolation structure has a step height in the range of 0.0 nanometers to 2.0 nanometers relative to the substrate; as well as A gate is formed above the oxide definition region and partially overlaps the shallow trench isolation structure.

10. The semiconductor structure according to claim 9, characterized in that: The shallower shallow trench isolation structure includes a liner layer.

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