An oxide semiconductor thin film transistor and a method for manufacturing the same

Abstract

The application discloses an oxide semiconductor thin film transistor and a preparation method thereof. The oxide semiconductor thin film transistor comprises a substrate, a gate electrode on the substrate, a gate dielectric layer on the gate electrode, an effective induction layer, the effective induction layer comprising a channel layer a, a channel layer b and a channel particle layer arranged from bottom to top, the channel layer a being on the gate dielectric layer, an induction layer on the channel particle layer, and a source electrode and a drain electrode arranged on the gate dielectric layer and the effective induction layer. The oxide semiconductor thin film transistor has high mobility and stability.

Description

Technical Field

[0001] This invention belongs to the field of display driving, specifically relating to an oxide semiconductor thin-film transistor and its fabrication method. Background Technology

[0002] Thin-film transistors (TFTs), as the cornerstone of modern electronics, are increasingly widely used in various high-tech fields. The introduction of amorphous oxide semiconductors (AOS) has injected new vitality into the development of TFT technology. AOS materials, especially InGaZnO (IGZO), have wide applications in the TFT field due to their unique performance advantages. IGZO-TFTs not only have extremely low off-state current, ensuring stable operation of circuits under low power consumption, but also exhibit high mobility, which is crucial for improving the processing speed and response sensitivity of circuits. In addition, the visible light transparency of IGZO materials makes them promising for applications in transparent electronic devices, such as transparent displays and solar cells.

[0003] In recent years, with continuous advancements in fabrication technology, the performance of IGZO-TFTs has been significantly improved, and their application areas have continued to expand. In display driving, IGZO-TFTs have been widely used in high-resolution, high-refresh-rate displays, bringing users a clearer and smoother visual experience. Simultaneously, IGZO-TFTs have also demonstrated enormous application potential in fields such as radio frequency circuits, providing strong support for the development of wireless communication technology. However, as display devices increasingly demand higher resolutions and refresh rates, existing IGZO TFTs are finding it increasingly difficult to meet the higher mobility requirements.

[0004] High-mobility thin-film transistors (TFTs) can respond to control signals more quickly, improve refresh rates, and optimize pixel brightness and color control, thereby enhancing display resolution and image quality. This is especially important for high-speed image or video playback, effectively preventing screen tearing or ghosting. Therefore, improving mobility has become one of the key technologies in manufacturing high-performance displays.

[0005] The electrical stability of a thin-film transistor (TFT) describes whether its performance parameters, such as leakage current, threshold voltage, and switching speed, can be maintained during long-term use. A TFT with good stability exhibits more consistent performance, ensuring consistent and reliable operation under various stress conditions or after repeated switching. Although compensation circuits are used in screen displays to correct threshold voltage deviations, excessively significant threshold voltage deviations are difficult for these circuits to repair, severely affecting the switching state of the TFT.

[0006] A common method to improve mobility is to increase the indium content (above 60%) in the oxide channel. However, for high-performance AOS TFTs, while increasing the indium (In) content helps improve carrier mobility, the In content is limited. 3+ Oxygen vacancy defects are easily generated in the surrounding environment, leading to poor stability of the device under negative bias illumination. Stability can be improved by doping with additional elements (such as Si, Hf, Pr, etc.), but this introduces a new scattering mechanism, which leads to a decrease in mobility. Therefore, the trade-off between mobility and stability is unavoidable in single-layer channel AOS TFTs.

[0007] Therefore, designing TFTs with low In content, high mobility, and high stability is a challenging problem. Summary of the Invention

[0008] The present invention provides an oxide semiconductor thin film transistor, which has high mobility and stability.

[0009] This invention provides an oxide semiconductor thin-film transistor, comprising:

[0010] Substrate;

[0011] The gate electrode is located on the substrate;

[0012] A gate dielectric layer is located on the gate electrode;

[0013] An effective induction layer, comprising a channel layer a, a channel layer b, a channel particle layer and an induction layer arranged from bottom to top, wherein the channel layer a is located on the gate dielectric layer;

[0014] The source electrode and the drain electrode are disposed on the gate dielectric layer and the effective induction layer, which are spaced apart.

[0015] This invention utilizes channel layer a as an electron transport layer and channel layer b as an electron relaxation layer. The channel layer b is used to assist photoelectron relaxation to achieve the stability of the device under light stress. At the same time, the channel layer a, which has fewer deep level defects, is used as an electron transport layer to ensure the stability of the device under normal stress.

[0016] This invention utilizes an induction layer to induce the formation of a channel particle layer. The ordered structure of the channel particle layer improves the orderliness of the effective induction layer. At the same time, due to the oxygen capture by the induction layer, the oxygen vacancy concentration of the channel layer is increased, thereby increasing the carrier concentration of the effective induction layer. Under the above two effects, the effective induction layer provided by this invention has a high mobility.

[0017] Preferably, in the channel layer a, the indium (In) content is 0-30%. Since the channel particle layer induced by the induction layer provided by the present invention improves the mobility, the indium content can be controlled at a low level.

[0018] Preferably, the material of the channel layer a is InSnZnO, SnZnO, InZnO, etc., and the channel layer a serves as an electron transport layer;

[0019] The channel layer b is made of materials such as InGaZnO and PrInSnZnO, and serves as an electronic relaxation layer.

[0020] Preferably, the thickness of the channel layer a is 15-25 nm, and the thickness of the channel layer b is 15-25 nm.

[0021] Preferably, the channel particle layer is an ordered nanoparticle layer.

[0022] Preferably, the material of the channel particle layer is one or more of indium oxide, zinc oxide, gallium oxide, and tin oxide.

[0023] Preferably, the inducing layer is located between the source electrode and the drain electrode, and does not overlap with the source electrode and the drain electrode. Mobility calculation formula: Where, μ sat Where L is the saturation mobility, W is the channel length, and C is the channel width. OX For the capacitance per unit area of ​​the gate dielectric layer, I D Leakage current, V GS The gate voltage is given, and the channel length is the distance between the two electrodes. The overlap between the source / drain electrodes and the induction layer reduces the channel length (L). The channel length used in the calculation is the original L, which leads to an overestimation of the calculated mobility, which does not match the actual value.

[0024] Preferably, the material of the inducing layer is a low electronegativity material.

[0025] More preferably, the low electronegativity material is Al or Ta. The Al or Ta used in this invention has very low electronegativity. When used as an induction layer, combined with an annealing process, it can induce the formation of an ordered channel particle layer between the channel layer b and the induction layer, improving channel order and increasing the mobility of the thin-film transistor.

[0026] Preferably, the substrate is any one of a silicon wafer, a thermally oxidized silicon wafer, a glass slide, or an alumina sheet;

[0027] The source electrode and drain electrode are made of ITO, Au, or Pt, respectively.

[0028] The present invention also provides a method for fabricating an oxide semiconductor thin-film transistor, comprising:

[0029] A gate electrode and a gate dielectric layer are sequentially formed on the substrate;

[0030] Radio frequency telemetry and control sputtering deposition, plasma treatment, and first annealing are performed on the gate dielectric layer to form the channel layer a;

[0031] Radio frequency magnetron sputtering deposition, mask etching, and a second annealing were performed on channel layer a to obtain channel layer b;

[0032] Spaced source and drain electrodes are formed on the channel layer b and the gate dielectric layer;

[0033] An induced layer is deposited on the channel layer b, followed by a third annealing process to form a channel particle layer between the channel layer b and the induced layer, thereby obtaining an oxide semiconductor thin film transistor.

[0034] Preferably, the substrate is a dual-layer rigid substrate consisting of an insulating layer and a conductive layer.

[0035] Preferably, the temperature of the first annealing is 300-400℃ and the time is 1-2 hours.

[0036] Preferably, the second annealing temperature is 300-400℃ and the time is 1-2 hours.

[0037] Preferably, before the gate electrode and the gate dielectric layer are sequentially formed on the substrate, the substrate is cleaned by ultrasonic cleaning with acetone, alcohol and deionized water respectively.

[0038] Preferably, the photomask lithography process uses hydroiodic acid etching, wherein the mass fraction of the hydroiodic acid is 55.0-58.0%, and the etching time is 5-10s.

[0039] Preferably, the temperature of the third annealing is 300-400℃, and the time is 1-2 hours. By controlling the temperature and time of the post-annealing, an ordered nanocrystalline channel particle layer can be induced to form.

[0040] Preferably, the source and drain electrode materials are materials such as ITO, Au, and Pt that can withstand high-temperature post-annealing.

[0041] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0042] This invention combines metal-induced layering technology with multilayer stacking technology, employing a target material with low indium content (below 30%). This not only fully leverages the advantages of low indium content in reducing defect density, minimizing indium resource consumption, and lowering production costs, but also significantly improves device stability while maintaining high mobility. Simultaneously, the oxidized induced layer provides passivation to the thin-film transistor channel, isolating it from the influence of air and other factors. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the structure of a thin-film transistor provided in Embodiment 1 of the present invention;

[0044] Figure 2 The transfer curve of the thin-film transistor obtained in Embodiment 1 of the present invention;

[0045] Figure 3 This is a graph showing the negative bias light irradiation stability of the thin-film transistor obtained in Example 1 of the present invention.

[0046] Figure 4 This is a positive bias voltage stability curve of the thin-film transistor obtained in Example 1 of the present invention;

[0047] Figure 5 This is a transmission electron microscope (TEM) image of the thin-film transistor obtained in Example 1 of the present invention.

[0048] Figure 6 The image shows the negative bias light irradiation stability (NBIS) results of the thin film transistors prepared in Example 1 and Comparative Example 1 of this invention.

[0049] Figure 7 This is a cross-sectional topographic view of the thin-film transistor obtained in Embodiment 1 of the present invention.

[0050] Among them, substrate-1, gate electrode layer-2, gate dielectric layer-3, effective induction layer (channel layer a-4, channel layer b-5, channel particle layer-6, induction layer-7), source electrode-8, and drain electrode-9. Detailed Implementation

[0051] To further describe the technical solutions of this invention in detail, the following will be explained in conjunction with the accompanying drawings and specific implementation examples.

[0052] A specific embodiment of the present invention provides a thin-film transistor of an oxide semiconductor, such as... Figure 1 As shown, it includes a substrate-1, a gate electrode layer-2, a gate dielectric layer-3, an effective induction layer (channel layer a-4, channel layer b-5, channel particle layer-6, induction layer-7), a source electrode-8, and a drain electrode-9.

[0053] In a specific embodiment of the present invention, the gate electrode 2 is located on the substrate 1, the gate dielectric layer 3 is located on the gate electrode 2, and the channel layer 4 forms a channel particle layer 5 at the contact interface with the source electrode 6 and the drain electrode 7. The channel layer 4, the source electrode 6 and the drain electrode 7 are all located on the gate dielectric layer 3.

[0054] The explanation will be elaborated with specific implementation cases.

[0055] Example 1

[0056] This embodiment illustrates a method for fabricating an oxide semiconductor thin-film transistor, including:

[0057] (1) Obtain p + A Si / SiO2 thermally oxidized silicon wafer was used as substrate 1, and a clean silicon wafer was used as a co-wafer. The wafers were ultrasonically cleaned with acetone, alcohol, and deionized water for 5 min, 5 min, and 8 min respectively, followed by drying with N2. The purpose of this process was to provide a contamination-free growth substrate for the subsequent channel layer. Furthermore, p + -Si / SiO2 thermally oxidized silicon wafers have an oxide layer of about 100nm on their surface, so they can be used simultaneously as substrate-1, gate electrode-2 and gate dielectric layer-3, simplifying the process.

[0058] (2) Take a 2cm*2cm p + Amorphous indium tin zinc oxide (ITI) thin films, approximately 25 nm thick, were grown on thermally oxidized silicon wafers (Si / SiO2) using RF magnetron sputtering technology with an argon-oxygen flow rate ratio of 6.5:6 sccm and a sputtering power of 100 W. The target material was ITZO (In:Sn:Zn = 1:1:3, i.e., the atomic ratio of In, Sn, and Zn was 1:1:3). Plasma treatment was then performed at 75 W for 10 min, followed by a first annealing process at 400 °C for 1 h to obtain the channel layer a-4.

[0059] (3) Using ITZO:Pr (In:Sn:Zn = 1:1:3, 5%wt, i.e., the atomic ratio of In, Sn and Zn is 1:1:3, and the mass fraction of Pr is 5%) as the target material, in a gas environment with an argon-oxygen flow ratio of 12.5:8sccm, the sputtering power is 100W, and an amorphous praseodymium-doped indium tin zinc oxide film is deposited on the film in step (2) using radio frequency magnetron sputtering technology. The film thickness is about 25nm.

[0060] (4) A channel photoresist array is formed on the channel surface using a mask photolithography process. Pre-baking is performed at 95°C for 3 minutes, followed by an exposure time of 9 seconds and a development time of 40 seconds. The etching solution used is 55.0-58.0% HI acid, and the etching time is 5-10 seconds. A second annealing process is then performed at 400°C for 1 hour to obtain the patterned channel layer, resulting in channel layer b-5.

[0061] (5) The patterned channel layer b-5 is bonded to the metal electrode mask. Using ITO as the target material, an ITO electrode of about 100 nm thickness is deposited by DC sputtering at 65W for 27 min in a gas environment with an argon-oxygen flow ratio of 30:1.5 sccm to obtain the source electrode-8 and the drain electrode-9.

[0062] (6) The sample obtained in step (5) is bonded to the induction layer mask, and an Al strip of about 15 nm thickness is deposited by DC sputtering at 50 W for 7 min in an argon atmosphere of 30 sccm to obtain the induction layer-7.

[0063] (7) The obtained device is subjected to post-annealing treatment to form a channel particle layer-6 between the channel layer b-5 and the induction layer-7. The annealing conditions are annealing at 400℃ for 1h.

[0064] Comparative Example 1

[0065] Compared with the embodiment, the comparative example does not perform step (6), and the remaining steps are the same as those in the embodiment.

[0066] Performance Analysis:

[0067] The electrical performance of the thin-film transistors in the embodiment was characterized and analyzed using a semiconductor parameter analyzer, and their threshold offset and mobility were calculated.

[0068] The morphology of the thin-film transistors in the embodiments was characterized and analyzed using transmission electron microscopy.

[0069] like Figure 2 This demonstrates the source-drain voltage V of Example 1 and Comparative Example 1. DS The transfer characteristic curve at 10.1V. From Figure 2 It can be seen that the on-state current high mobility (μ) of the embodiment is large from Figure 2 It can be seen that the on-state current of the embodiment is higher than that of the comparative example, according to the mobility calculation formula. μ sat Where L is the saturation mobility, W is the channel length, and C is the channel width. OX For the capacitance per unit area of ​​the gate dielectric layer, I D Leakage current, V GS Given the gate voltage, the mobility is greater than that of the comparative example. Threshold (V) th The point is where the source-drain current is 10. -8 The corresponding gate voltage value, near 0V, has a steep subthreshold slope (SS).

[0070] Figure 3 a and b and Figure 5 Figures a and b illustrate the negative bias illumination stability (NBIS) results for Example 1 and Comparative Example 1. Example 1, with a gate bias V... GS = -20V, light intensity is 0.14mw / cm 2 Under the given conditions, the maximum deviation of the threshold voltage during irradiation for 600-3600s was -0.4V, while the maximum deviation of the threshold voltage in Comparative Example 1 was -0.68V.

[0071] Figure 4a and b and Figure 6 Figures a and b illustrate the positive bias stability (PBS) results for Example 1 and Comparative Example 1. Example 1, at a gate bias V... GS Under 20V conditions, the threshold voltage offset is 0V after irradiation for 600-3600s, while the maximum threshold voltage offset in Comparative Example 1 is 1.9V.

[0072] Electrical performance parameter table provided in Example 1

[0073]

[0074] Figure 7 The image shows a cross-sectional morphology of the embodiment under a transmission electron microscope. It is clearly observed that a granular layer exists at the interface between the induced layer and the channel in the embodiment. Some of these particles have crystallized, and after calculating the crystal intercepts, their composition is Zn4In2O7 and Zn7In2O7. 10 .

[0075] The above embodiments, in conjunction with the accompanying drawings, have illustrated and explained the present invention. It should be noted that the above description represents only specific embodiments of the present invention and is therefore merely illustrative and should not be considered limiting. Modifications, improvements, and substitutions made by those skilled in the art based on this invention should all be within the protection scope of the present invention.

Claims

1. An oxide semiconductor thin-film transistor, characterized in that, include: Substrate; The gate electrode is located on the substrate; A gate dielectric layer is located on the gate electrode; An effective induction layer, comprising a channel layer a, a channel layer b, a channel particle layer and an induction layer arranged from bottom to top, wherein the channel layer a is located on the gate dielectric layer; The source electrode and the drain electrode are disposed on the gate dielectric layer and the effective induction layer, respectively, with the source electrode and the drain electrode spaced apart. In channel layer a, the indium content is 0-30%; The material of the channel particle layer is one or more of indium oxide, zinc oxide, gallium oxide, and tin oxide; The material of the induction layer is a low electronegativity material; The low electronegativity material is Al or Ta.

2. The oxide semiconductor thin-film transistor according to claim 1, characterized in that, The material of the channel layer a is InSnZnO, SnZnO or InZnO; The material of the channel layer b is InGaZnO or PrInSnZnO.

3. The oxide semiconductor thin-film transistor according to claim 1, characterized in that, The channel particle layer is an ordered nanoparticle layer.

4. The oxide semiconductor thin-film transistor according to claim 1, characterized in that, The induction layer is located between the source electrode and the drain electrode, and does not overlap with the source electrode and the drain electrode.

5. The oxide semiconductor thin-film transistor according to claim 1, characterized in that, The source electrode and drain electrode are made of ITO, Au, or Pt, respectively.

6. A method for fabricating an oxide semiconductor thin-film transistor according to any one of claims 1-5, characterized in that, include: A gate electrode and a gate dielectric layer are sequentially formed on the substrate; Radio frequency telemetry and control sputtering deposition, plasma treatment, and first annealing are performed on the gate dielectric layer to form the channel layer a; Radio frequency magnetron sputtering deposition, mask lithography, and a second annealing are performed on channel layer a to obtain channel layer b; Spaced source and drain electrodes are formed on the channel layer b and the gate dielectric layer; An induced layer is deposited on the channel layer b, followed by a third annealing process to form a channel particle layer between the channel layer b and the induced layer, thereby obtaining an oxide semiconductor thin film transistor.

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