Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The method comprises the following steps: providing a substrate comprising an NMOS region and a PMOS region, the substrate being provided with a gate structure, a hard mask layer, a first side wall and a first protective layer or a second side wall, the thickness of the hard mask layer in the NMOS region being greater than that in the PMOS region; forming a filling layer covering the substrate; exposing the hard mask layer in the NMOS region; removing the remaining filling layer in the NMOS region; removing the hard mask layer with a partial thickness in the NMOS region; removing the filling layer in the PMOS region to form an oxide layer on the surface of the epitaxial layer; and removing the hard mask layer, the second side wall and the first protective layer. The application can avoid causing damage to the epitaxial layer and the substrate in the NMOS region, and can reduce the damage caused by over-etching to the first side wall in the PMOS region, so that the height of the last remaining first side wall in the NMOS region and the PMOS region is similar, thereby ensuring the appearance of the subsequently formed side wall.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuits, and in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] With the rapid development of semiconductor manufacturing technology, in order to achieve higher operating speed, greater data storage capacity and more functions, semiconductor devices are developing towards higher element density and higher integration. Therefore, the gate of a complementary metal oxide semiconductor (CMOS) transistor becomes thinner and shorter than ever. However, the size change of the gate will affect the electrical performance of the semiconductor device, and at present, the electrical performance of the semiconductor device is mainly improved by controlling the carrier mobility. One key element of this technology is to control the stress in the transistor channel. For example, by properly controlling the stress, the carrier (electrons in n-channel transistors and holes in p-channel transistors) mobility is improved, thereby improving the drive current. Among them, in the CMOS device channel direction (longitudinal), the tensile stress is beneficial to the NMOS electron mobility, and the compressive stress is beneficial to the PMOS hole mobility; the tensile stress in the channel width direction (transverse) is beneficial to the carrier mobility of NMOS and PMOS devices, and the compressive stress in the vertical channel plane direction (out-of-plane) is beneficial to the electron mobility of NMOS devices, and the tensile stress is beneficial to the mobility of PMOS devices.

[0003] At present, the conventional manufacturing process of a CMOS device applying a stress proximity technique includes: setting a shallow trench isolation (STI) structure on a semiconductor substrate, and isolating an NMOS region and a PMOS region by using the shallow trench isolation structure; then setting a gate structure on the NMOS region and the PMOS region, and setting a hard mask layer on the surface of the gate structure; then setting a side wall on the side wall of the gate structure; then forming a silicon germanium epitaxial layer in the substrate on both sides of the gate structure in the PMOS region; and then removing the residual hard mask layer in the NMOS region and the PMOS region.

[0004] However, in the process of removing the hard mask layer, the substrate in the NMOS region will be lost, and since the height of the hard mask layer in the NMOS region is greater than the height of the hard mask layer in the PMOS region, over-etching is needed when removing the hard mask layer in the NMOS region, so that the remaining height of the side wall in the PMOS region is much lower than the remaining height of the side wall in the NMOS region, thereby affecting the morphology of the subsequently formed side wall. At the same time, in the process of removing the hard mask layer, over-etching will also cause damage to the epitaxial layer in the PMOS region, resulting in a decrease in device performance. SUMMARY

[0005] The present application aims to provide a semiconductor device and a manufacturing method thereof, which can reduce the loss of the substrate in the NMOS region, reduce the loss of the side wall in the PMOS region caused by over-etching, reduce the influence of over-etching on the epitaxial layer, and improve the performance of the device.

[0006] To solve the above technical problems, according to a first aspect of the present application, a manufacturing method of a semiconductor device is provided, comprising the following steps:

[0007] providing a substrate, wherein the substrate comprises an NMOS region and a PMOS region; in the NMOS region, a gate structure, a hard mask layer, a first side wall and a first protective layer are formed on the substrate, the hard mask layer is located on the gate structure, the first side wall is located on the side wall of the gate structure and the hard mask layer, and the first protective layer conformally covers the first hard mask layer, the first side wall and the substrate; in the PMOS region, a gate structure, a hard mask layer, a first side wall and a second side wall are formed on the substrate, the hard mask layer is located on the gate structure, the first side wall is located on the side wall of the gate structure and the hard mask layer, the second side wall is located on the side wall of the first side wall, and an epitaxial layer is further formed in the substrate on both sides of the gate structure; and the thickness of the hard mask layer in the NMOS region is greater than the thickness of the hard mask layer in the PMOS region;

[0008] forming a filling layer, wherein the filling layer covers the substrate;

[0009] removing part of the filling layer and part of the first protective layer in the NMOS region to expose the hard mask layer;

[0010] removing the remaining filling layer in the NMOS region;

[0011] removing part of the thickness of the hard mask layer in the NMOS region, and retaining at least part of the thickness of the first protective layer on the substrate;

[0012] removing the filling layer in the PMOS region, and performing an oxidation process to form an oxidation layer on the surface of the epitaxial layer; and

[0013] removing the hard mask layer, the second side wall and the first protective layer in the NMOS region and the PMOS region, and retaining the first side wall of the gate structure.

[0014] Optionally, a second protective layer is further formed in the NMOS region, wherein the second protective layer conformally covers the first protective layer; and a third side wall is further formed in the PMOS region, wherein the third side wall is located on the side wall of the second side wall.

[0015] Optionally, the method for removing part of the filling layer and part of the first protective layer in the NMOS region to expose the hard mask layer comprises:

[0016] forming an anti-reflection coating layer covering the filling layer;

[0017] forming a patterned photoresist layer covering the anti-reflection coating layer in the PMOS region; and

[0018] etching the anti-reflection coating layer and part of the filling layer, part of the second protective layer and part of the first protective layer in the NMOS region to expose the hard mask layer, with the patterned photoresist layer as a mask.

[0019] Optionally, the thickness of the hard mask layer in the NMOS region is removed to make the thickness of the hard mask layer in the NMOS region substantially equal to the thickness of the hard mask layer in the PMOS region.

[0020] Optionally, the hard mask layer and the second protective layer, the third sidewall and the first sidewall are made of the same material, and the first protective layer and the second sidewall are made of the same material.

[0021] Optionally, the hard mask layer and the second protective layer, the third sidewall and the first sidewall are made of silicon nitride, and the first protective layer and the second sidewall are made of silicon oxide.

[0022] Optionally, part of the filling layer, part of the second protective layer and part of the first protective layer in the NMOS region are removed to expose the hard mask layer by using a dry etching process or a wet etching process, and the filling layer and the second protective layer and the first protective layer have a low etching selectivity.

[0023] Optionally, the remaining filling layer in the NMOS region is removed by using a dry etching process or a wet etching process, and the filling layer has a high etching selectivity with respect to the first protective layer and the second protective layer.

[0024] Optionally, part of the thickness of the hard mask layer and part of the second protective layer in the NMOS region are removed by using a dry etching process or a wet etching process, and at least part of the thickness of the first protective layer is reserved on the substrate, the hard mask layer has a high etching selectivity with respect to the first protective layer, and the second protective layer has a high etching selectivity with respect to the first protective layer.

[0025] To solve the above technical problems, according to the second aspect of the present application, a semiconductor device is also provided, which is manufactured by using the manufacturing method of the semiconductor device as described above.

[0026] In summary, in the semiconductor device and the manufacturing method thereof, the hard mask layer in the NMOS region is removed by a certain thickness, and the first protective layer on the substrate in the NMOS region is reserved by a certain thickness. Then, the oxidation process is performed to form an oxide layer on the surface of the epitaxial layer. Since the first protective layer on the substrate in the NMOS region is reserved by a certain thickness, the substrate will not be oxidized during the oxidation process, thereby avoiding the loss of the substrate in the NMOS region caused by the oxidation process. Meanwhile, after the hard mask layer in the NMOS region is removed by a certain thickness and the height difference of the hard mask layer in the two regions is reduced, the hard mask layer in the NMOS region and the PMOS region is removed at the same time, which can reduce the over-etching caused by the need to completely remove the hard mask layer, thereby reducing the loss of the first side wall in the PMOS region caused by the over-etching, making the height of the last reserved first side wall in the NMOS region and the PMOS region similar, thereby ensuring the morphology of the subsequently formed side wall. In addition, the over-etching is reduced, which can reduce the damage to the epitaxial layer caused by the over-etching, thereby improving the performance of the device.

[0027] Further, the part of the filling layer and the part of the first protective layer in the NMOS region are removed first to expose the hard mask layer, and then the remaining filling layer in the NMOS region is removed. In the process of removing the first protective layer on the top of the hard mask layer, the filling layer will not cause etching to the isolation structure due to the protection of the filling layer, thereby avoiding the loss of the isolation structure. BRIEF DESCRIPTION OF DRAWINGS

[0028] Those skilled in the art will understand that the provided drawings are for the purpose of better illustrating the present application and do not constitute any limitation on the scope of the present application. Among them:

[0029] Figures 1 to 7 is a schematic structural diagram of each step of the manufacturing method of the semiconductor device.

[0030] Figure 8 is a flow chart of the manufacturing method of the semiconductor device provided by an embodiment of the present application.

[0031] Figures 9 to 16 is a schematic structural diagram of each step of the manufacturing method of the semiconductor device provided by an embodiment of the present application.

[0032] Explanation of reference signs:

[0033] Figures 1 to 7In the middle: 10-substrate; 11-isolation structure; 12-gate structure; 13-hard mask layer; 14-first sidewall; 14′-final first sidewall; 15-first protective layer; 16-second protective layer; 17-second sidewall; 18-third sidewall; 19-epitaxy layer; 20-antireflective coating; 21-patterned mask layer; 22-oxide layer.

[0034] Figures 9 to 16 In the middle: 100-substrate; 110-isolation structure; 120-gate structure; 130-hard mask layer; 140-first sidewall; 150-first protective layer; 160-second protective layer; 170-second sidewall; 180-third sidewall; 190-epitaxy layer; 200-fill layer; 210-antireflective coating; 220-patterned photoresist layer; 230-oxide layer. Detailed Implementation

[0035] Figures 1 to 7 This is a schematic diagram of the steps involved in the fabrication of a semiconductor device. Figure 1 This is a schematic diagram of the structure after a silicon-germanium epitaxial layer is formed within the PMOS substrate, as shown below. Figure 1 As shown, substrate 10 includes an NMOS region I and a PMOS region II, which are isolated from each other by an isolation structure 11. A gate structure 12 is formed in the NMOS region, and a hard mask layer 13 is formed on the gate structure 12. A first sidewall 14 is formed on the sidewalls of the gate structure 12 and the hard mask layer 13. A first protective layer 15 and a second protective layer 16 are also formed in the NMOS region. The first protective layer 15 conformally covers the hard mask layer 13, the first sidewall 14, and the substrate 10, and the second protective layer 16 conformally covers the first protective layer 15. Within the PMOS region, a gate structure 12 is formed on the substrate 10, and a hard mask layer 13 is formed on the gate structure 12. A first sidewall 14, a second sidewall 17, and a third sidewall 18 are sequentially formed on the sidewalls of the gate structure 12 and the hard mask layer 13. The material of the second sidewall 17 is the same as that of the first protective layer 15, and the material of the third sidewall 18 is the same as that of the second protective layer 16. Silicon-germanium epitaxial layers 19 are formed in the substrate 10 on both sides of the gate structure 12 within the PMOS region. The thickness of the hard mask layer 13 within the NMOS region is greater than the thickness of the hard mask layer 13 within the PMOS region.

[0036] The material of the hard mask layer 13 is preferably silicon nitride, the materials of the first sidewall 14, the third sidewall 18, and the second protective layer 16 are all preferably silicon nitride, and the materials of the second sidewall 17 and the first protective layer 15 are preferably silicon oxide.

[0037] Please refer to Figure 2 As shown, an anti-reflective coating (Barc) 20 is formed, which covers the substrate 10, and then a patterned photoresist layer 21 is formed, which covers the anti-reflective coating 20 in the PMOS region and exposes the anti-reflective coating 20 in the NMOS region.

[0038] Please refer to Figure 3 As shown, using the patterned photoresist layer 21 as a mask, the anti-reflective coating 20 in the NMOS region is etched away, and part of the second protective layer 16 is removed. The remaining second protective layer 16 is located on the sidewall of the gate structure 12 to form a third sidewall 18.

[0039] Please refer to Figure 4 As shown, the patterned photoresist layer 21 and the anti-reflective coating 20 are removed.

[0040] Please refer to Figure 5 As shown, the first protective layer 15 on top of the hard mask layer 13 in the NMOS region is removed by wet cleaning, and the remaining first protective layer 15 serves as the second sidewall 17.

[0041] Please refer to Figure 6 As shown, an oxidation process is performed to form an oxide layer 22 on the epitaxial layer 19 to prevent damage to the epitaxial layer 19 in subsequent steps.

[0042] Please refer to Figure 7 As shown, wet etching removes the hard mask layer 13, the third sidewall 18, and the second sidewall 17, leaving the first sidewall 14 as the final sidewall of the gate structure 12.

[0043] However, during wet cleaning, the first protective layer 15 on the substrate 10 within the NMOS region is also removed. During subsequent oxidation processes, the substrate 10 will also be oxidized, resulting in the loss of the substrate 10. Furthermore, wet cleaning also leads to the loss of the isolation structure 11. Additionally, during wet etching, because the thickness of the hard mask layer 13 within the NMOS region is greater than that within the PMOS region, over-etching is required to ensure complete removal of the hard mask layer 13 within the NMOS region. This results in the final height of the first sidewall 14' within the PMOS region being significantly lower than that within the NMOS region, thus affecting the morphology of the subsequently formed sidewalls. Moreover, during wet etching, due to over-etching, prolonged immersion of the PMOS region in hot phosphoric acid may damage the epitaxial layer 19, thereby affecting device performance.

[0044] In order to solve the above problems, the present application provides a semiconductor device and a manufacturing method thereof, which can not cause loss of the NMOS region substrate, can reduce the loss of the first side wall in the PMOS region caused by over-etching, and can reduce the influence of over-etching on the epitaxial layer, thereby improving the device performance.

[0045] To make the objects, advantages and features of the present application more comprehensible, the following further describes the present application in conjunction with the drawings and specific embodiments. It should be noted that the drawings are very simplified and not drawn according to scale, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application. In addition, the structures shown in the drawings are often a part of the actual structures. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0046] As used in the present application, the singular forms "a", "an" and "the" include plural referents unless the content clearly dictates otherwise. As used in the present application, the term "or" is generally used in the sense of "and / or" unless the content clearly dictates otherwise. As used in the present application, the term "several" is generally used in the sense of "at least one" unless the content clearly dictates otherwise. As used in the present application, the term "at least two" is generally used in the sense of "two or more" unless the content clearly dictates otherwise. In addition, the terms "first", "second", "third" are only used for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second", "third" can explicitly or implicitly include one or at least two features.

[0047] Figure 8 FIG. 1 is a flowchart of a manufacturing method of a semiconductor device according to an embodiment of the present application. As shown in FIG. 1, the manufacturing method of the semiconductor device according to the embodiment of the present application includes the following steps: Figure 8

[0048] ​Step S1: providing a substrate, the substrate comprising an NMOS region and a PMOS region; in the NMOS region, a gate structure, a hard mask layer, a first sidewall and a first protective layer are formed on the substrate, the hard mask layer is on the gate structure, the first sidewall is on the sidewall of the gate structure and the hard mask layer, and the first protective layer conformally covers the first hard mask layer, the first sidewall and the substrate; in the PMOS region, a gate structure, a hard mask layer, a first sidewall and a second sidewall are formed on the substrate, the hard mask layer is on the gate structure, the first sidewall is on the sidewall of the gate structure and the hard mask layer, the second sidewall is on the sidewall of the first sidewall, and an epitaxial layer is further formed in the substrate on both sides of the gate structure; and the thickness of the hard mask layer in the NMOS region is greater than the thickness of the hard mask layer in the PMOS region;

[0049] Step S2: forming a filling layer, the filling layer covering the substrate;

[0050] Step S3: removing part of the filling layer and part of the first protective layer in the NMOS region to expose the hard mask layer;

[0051] Step S4: removing the remaining filling layer in the NMOS region;

[0052] Step S5: removing part of the thickness of the hard mask layer in the NMOS region, and at least retaining part of the thickness of the first protective layer on the substrate;

[0053] Step S6: removing the filling layer in the PMOS region, and performing an oxidation process to form an oxide layer on the surface of the epitaxial layer; and

[0054] Step S7: removing the hard mask layer, the second sidewall and the first protective layer in the NMOS region and the PMOS region, and retaining the first sidewall of the sidewall of the gate structure.

[0055] Figures 9 to 16 is a schematic structural diagram of each step of the manufacturing method of the semiconductor device provided by an embodiment of the present application. Next, the manufacturing method of the semiconductor device provided by the embodiment of the present application will be described in combination with Figure 8 and Figures 9 to 16 The manufacturing method of the semiconductor device provided by the embodiment of the present application will be described in detail.

[0056] In step S1, please refer to Figure 9As shown, a substrate 100 is provided, which comprises an NMOS region I and a PMOS region II; in the NMOS region, a gate structure 120, a hard mask layer 130, a first sidewall 140 and a first protective layer 150 are formed on the substrate 100, the hard mask layer 130 is located on the gate structure 120, the first sidewall 140 is located on the sidewall of the gate structure 120 and the hard mask layer 130, and the first protective layer 150 conformally covers the first hard mask layer 130, the first sidewall 140 and the substrate 100; in the PMOS region, a gate structure 120, a hard mask layer 130, a first sidewall 140 and a second sidewall 170 are formed on the substrate 100, the hard mask layer 130 is located on the gate structure 120, the first sidewall 140 is located on the sidewall of the gate structure 120 and the hard mask layer 130, the second sidewall 170 is located on the sidewall of the first sidewall 140, and an epitaxial layer 190 is also formed in the substrate 100 on both sides of the gate structure 120; and the thickness of the hard mask layer 130 in the NMOS region is greater than the thickness of the hard mask layer 130 in the PMOS region.

[0057] In this embodiment, Figure 9 is a structural schematic diagram after forming an epitaxial layer in the substrate of the PMOS region. Please refer to Figure 9 As shown, a second protective layer 160 is also formed in the NMOS region, which conformally covers the first protective layer 150; and a third sidewall 180 is also formed in the PMOS region, which is located on the sidewall of the second sidewall 170. The second sidewall 170 in the PMOS region is formed after etching the first protective layer formed in the PMOS region, and the third sidewall 180 is formed after etching the second protective layer formed in the PMOS region, so the material of the second sidewall 170 is the same as that of the first protective layer 150, and the material of the third sidewall 180 is the same as that of the second protective layer 160, but not limited thereto.

[0058] In an embodiment of the present application, the material of the hard mask layer 130 and the second protective layer 160 can be the same, and the material of the first sidewall 140 and the second protective layer 160 can also be the same, that is, the material of the hard mask layer 130, the second protective layer 160, the first sidewall 140 and the third sidewall 180 can all be the same, but not limited thereto. For example, the material of the hard mask layer 130, the second protective layer 160, the first sidewall 140 and the third sidewall 180 is nitride, such as silicon nitride, and the material of the first protective layer 150 and the second sidewall 170 is oxide, such as silicon oxide.

[0059] The substrate 100 further has an isolation structure 110 formed therein, which is used to isolate the NMOS region from the PMOS region, and the isolation structure 110 is, for example, a shallow trench isolation structure. In the PMOS region, the substrate 100 on both sides of the gate structure 120 has an epitaxial layer 190 formed therein, and the material of the epitaxial layer 190 is, for example, silicon germanium. In addition, since the hard mask layer 130 in the PMOS region is used as a mask when the epitaxial layer 190 is formed, a groove is formed in the substrate 100. Therefore, the thickness of the hard mask layer 130 in the NMOS region is greater than the thickness of the hard mask layer 130 in the PMOS region, for example, the thickness of the hard mask layer 130 in the NMOS region is The thickness of the hard mask layer 130 in the PMOS region is

[0060] In step S2, as shown in Figure 10 , a filling layer 200 is formed, which covers the substrate 100.

[0061] In this embodiment, the filling layer 200 needs to have good filling capacity to fill the groove between adjacent gate structures 120 and cover the hard mask layer 130 and the second protective layer 160, and the upper surface of the filling layer 200 is a relatively flat surface. For example, the filling layer 200 contains a water-soluble organic carbon (SOC), but is not limited thereto.

[0062] In step S3, as shown in Figure 11 , part of the filling layer 200 and part of the first protective layer 150 in the NMOS region are removed to expose the hard mask layer 130.

[0063] For example, as shown in Figure 10 , an anti-reflective coating 210 is first formed, which covers the filling layer 200, then a photoresist layer is formed on the anti-reflective coating 210, which covers the anti-reflective coating 210, and then the photoresist layer is patterned to form a patterned photoresist layer 220.

[0064] As shown in Figure 11 , the anti-reflective coating 210 in the NMOS region and part of the filling layer 200, part of the second protective layer 160 and part of the first protective layer 150 are etched with the patterned photoresist layer 220 as a mask to expose the hard mask layer 130.

[0065] In this embodiment, part of the filling layer 200, part of the second protective layer 160 and part of the first protective layer 150 are removed by using a dry etching process or a wet etching process, wherein the filling layer 200 has a low etching selectivity ratio with the second protective layer 160 and the first protective layer 150. That is, the etching rate of the filling layer 200, the second protective layer 160 and the first protective layer 150 is close in this etching process, which means that the etching rate of the filling layer and the silicon nitride and the silicon oxide is close. For example, the dry etching process is used for etching, and the etching gas can include CF4 or NF3, but is not limited thereto.

[0066] When the first protective layer 150 on the hard mask layer 130 in the NMOS region is removed by etching, the isolation structure 110 is protected by the filling layer 200, so that the isolation structure 110 is not etched in the process of removing the first protective layer 150, thereby avoiding the loss of the isolation structure 110.

[0067] In step S4, as shown in Figure 12 , the remaining filling layer 200 in the NMOS region is removed.

[0068] In this embodiment, the remaining filling layer 200 in the NMOS region is removed by using a dry etching process or a wet etching process, and the filling layer 200 has a high etching selectivity ratio with the first protective layer 150 and the second protective layer 160. That is, the etching rate of the filling layer 200 is high in this etching process, and the etching rate of the second protective layer 160 and the first protective layer 150 (i.e., the etching rate of the silicon nitride and the silicon oxide) is low, so that the remaining filling layer 200 in the NMOS region is removed. For example, the dry etching process is used to remove the filling layer 200, and the etching gas can include O2 or SO2 and other gases used for etching organic matter, but is not limited thereto.

[0069] In step S5, as shown in Figure 13 , part of the hard mask layer 130 in the NMOS region is removed, and at least part of the first protective layer 150 on the substrate 100 is reserved.

[0070] In an embodiment of the present application, part of the hard mask layer 130 in the NMOS region is removed, so that the thickness of the hard mask layer 130 in the NMOS region is substantially equal to the thickness of the hard mask layer 130 in the PMOS region, wherein substantially equal means that the difference between the thicknesses of the two is less than 20%. For example, the thickness of the remaining hard mask layer 130 in the NMOS region is 1000A, and the thickness of the hard mask layer 130 in the PMOS region is 1000A.

[0071] In this embodiment, the hard mask layer 130 and the second protective layer 160 in the NMOS region are removed by dry etching or wet etching process, and at least part of the first protective layer 150 on the substrate 100 is reserved, wherein the hard mask layer 130 has a high etching selectivity with respect to the first protective layer 150, and the second protective layer 160 has a high etching selectivity with respect to the first protective layer 150. That is, in this etching process, the etching rate of the hard mask layer 130 and the second protective layer 160 (i.e. silicon nitride) is high, and the etching rate of the first protective layer 150 (i.e. silicon oxide) is low. For example, the dry etching process is used to remove part of the hard mask layer 130 and part of the second protective layer 160, and the etching gas can include CH3F or SO2, but is not limited thereto.

[0072] In the process of etching and removing the hard mask layer 130, part of the second protective layer 160 is also etched and removed. In an embodiment of the present application, as shown in Figure 13 , the second protective layer 160 on the horizontal surface of the substrate 100 is completely removed, and part of the second protective layer 160 on the sidewall of the gate structure 120 remains as a sidewall. In another embodiment of the present application, part of the second protective layer 160 can remain on the sidewall of the gate structure 120 and on the horizontal surface of the substrate 100. In another embodiment of the present application, the second protective layer 160 on the horizontal surface of the substrate 100 can be completely removed, and part of the first protective layer 150 exposed is etched. In the above embodiments, at least part of the first protective layer 150 on the substrate 100 is reserved.

[0073] In the process of etching the hard mask layer 130, part of the patterned photoresist layer 220 is removed, or the patterned photoresist layer 220 is completely removed.

[0074] In step S6, please refer to Figure 14 and Figure 15 , the filling layer in the PMOS region is removed, and an oxidation process is performed to form an oxide layer 230 on the surface of the epitaxial layer 190.

[0075] In this embodiment, the remaining patterned photoresist layer 220 is removed first, and then the anti-reflective coating layer 210 and the filling layer 200 in the PMOS region are removed, to form a structure as shown in Figure 14 . Then, an oxidation process is performed to form an oxide layer on the surface of the epitaxial layer 190, to form a structure as shown in Figure 15 .

[0076] For example, the surface of the epitaxial layer 190 can be oxidized by ozone to form the oxidation layer 230, which is used to protect the epitaxial layer 190 in subsequent etching. Since the first protection layer 150 with a partial thickness is reserved on the substrate 100 in the NMOS region, the substrate 100 in the NMOS region is not oxidized, so that the loss of the substrate in the NMOS region due to the oxidation process can be avoided.

[0077] In step S7, as shown in Figure 16 The hard mask layer 130, the second sidewall 170 and the first protection layer 150 in the NMOS region and the PMOS region are removed, and the first sidewall 140 of the gate structure 120 is reserved.

[0078] In this embodiment, the hard mask layer 130, the second protection layer 160 and the third sidewall 180 are etched and removed first, for example, etching can be performed by using phosphoric acid, and then the first protection layer 150 and the second sidewall 170 are etched and removed, for example, etching can be performed by using hydrofluoric acid.

[0079] Although the thickness of the hard mask layer 130 in the NMOS region is greater than that in the PMOS region in step S1, the hard mask layer 130 in the NMOS region has been partially etched in step S5, and the height difference between the hard mask layers 130 in the two regions has been reduced. Therefore, although over-etching is needed to ensure that the hard mask layer 130 in the NMOS region is completely removed, the over-etching can be reduced due to the reduced height difference, so that the loss of the first sidewall 140 in the PMOS region caused by over-etching can be reduced, and the height of the first sidewall 140 reserved in the NMOS region and the PMOS region is similar, so that the morphology of the sidewall formed subsequently can be ensured. In addition, the over-etching is reduced, and the influence of over-etching on the epitaxial layer 190 can be reduced, so that the performance of the device can be improved.

[0080] Correspondingly, the application also provides a semiconductor device, which is manufactured by using the manufacturing method of the semiconductor device.

[0081] In the semiconductor device and the manufacturing method thereof, the hard mask layer in the NMOS region is removed partially, the first protective layer on the substrate in the NMOS region is reserved partially, then the oxidation process is performed to form an oxide layer on the surface of the epitaxial layer. Since the first protective layer on the substrate in the NMOS region is reserved partially, the substrate will not be oxidized during the oxidation process, so that the loss of the substrate in the NMOS region caused by the oxidation process can be avoided. Meanwhile, after the hard mask layer in the NMOS region is removed partially and the height difference of the hard mask layer in the two regions is reduced, the hard mask layer in the NMOS region and the PMOS region is removed simultaneously, so that the over-etching caused by the need to remove the hard mask layer completely can be reduced, the loss of the first side wall in the PMOS region caused by the over-etching can be reduced, the height of the first side wall reserved finally in the NMOS region and the PMOS region is similar, so that the morphology of the side wall formed subsequently can be ensured. In addition, the over-etching is reduced, the damage of the epitaxial layer caused by the over-etching can be reduced, so that the performance of the device can be improved.

[0082] Further, the part of the filling layer, the part of the second protective layer and the part of the first protective layer in the NMOS region are removed first to expose the hard mask layer, then the remaining filling layer in the NMOS region is removed. In the process of removing the first protective layer on the top of the hard mask layer, the filling layer will not cause etching to the isolation structure due to the protection of the filling layer, so that the loss of the isolation structure can be avoided.

[0083] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way. Any modification or change made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: providing a substrate, the substrate comprising an NMOS region and a PMOS region; forming a gate structure, a hard mask layer, a first sidewall and a first protective layer on the substrate in the NMOS region, the hard mask layer being on the gate structure, the first sidewall being on the sidewall of the gate structure and the hard mask layer, and the first protective layer conformally covering the first hard mask layer, the first sidewall and the substrate; forming a gate structure, a hard mask layer, a first sidewall and a second sidewall on the substrate in the PMOS region, the hard mask layer being on the gate structure, the first sidewall being on the sidewall of the gate structure and the hard mask layer, and the second sidewall being on the sidewall of the first sidewall, and an epitaxial layer being further formed in the substrate on both sides of the gate structure; and the thickness of the hard mask layer in the NMOS region being greater than the thickness of the hard mask layer in the PMOS region; forming a filling layer, the filling layer covering the substrate; removing part of the filling layer and part of the first protective layer in the NMOS region to expose the hard mask layer; removing the remaining filling layer in the NMOS region; removing part of the thickness of the hard mask layer in the NMOS region, and at least retaining part of the thickness of the first protective layer on the substrate; removing the filling layer in the PMOS region, and performing an oxidation process to form an oxide layer on the surface of the epitaxial layer; and removing the hard mask layer, the second sidewall and the first protective layer in the NMOS region and the PMOS region, and retaining the first sidewall of the sidewall of the gate structure.

2. The method of manufacturing a semiconductor device according to claim 1, wherein A second protective layer is further formed in the NMOS region, the second protective layer conformally covering the first protective layer; and a third sidewall is further formed in the PMOS region, the third sidewall being on the sidewall of the second sidewall.

3. The method of manufacturing a semiconductor device according to claim 2, wherein The method for removing part of the filling layer and part of the first protective layer in the NMOS region to expose the hard mask layer comprises: forming an anti-reflective coating layer, the anti-reflective coating layer covering the filling layer; forming a patterned photoresist layer, the patterned photoresist layer covering the anti-reflective coating layer in the PMOS region; and using the patterned photoresist layer as a mask, etching the anti-reflective coating layer in the NMOS region and part of the filling layer, part of the second protective layer and part of the first protective layer to expose the hard mask layer.

4. The method of manufacturing a semiconductor device according to Claim 2, wherein The thickness of the hard mask layer in the NMOS region is substantially equal to the thickness of the hard mask layer in the PMOS region.

5. The method according to any one of claims 2 to 4, wherein The materials of the hard mask layer, the second protective layer, the third sidewall and the first sidewall are the same, and the materials of the first protective layer and the second sidewall are the same.

6. The method of manufacturing a semiconductor device according to claim 5, wherein The materials of the hard mask layer, the second protective layer, the third sidewall and the first sidewall are silicon nitride, and the materials of the first protective layer and the second sidewall are silicon oxide.

7. The method of manufacturing a semiconductor device according to claim 6, wherein The dry etching process or the wet etching process is used to remove part of the filling layer, part of the second protective layer and part of the first protective layer in the NMOS region to expose the hard mask layer, and the filling layer and the second protective layer and the first protective layer have low etching selectivity.

8. The method of fabricating a semiconductor device according to Claim 6, wherein The dry etching process or the wet etching process is used to remove the remaining filling layer in the NMOS region, and the filling layer has high etching selectivity with respect to the first protective layer and the second protective layer.

9. The method of fabricating a semiconductor device according to Claim 6, wherein The dry etching process or the wet etching process is used to remove part of the thickness of the hard mask layer and part of the second protective layer in the NMOS region, and at least part of the thickness of the first protective layer is reserved on the substrate, the hard mask layer has high etching selectivity with respect to the first protective layer, and the second protective layer has high etching selectivity with respect to the first protective layer.

10. A semiconductor device, characterized by comprising: The semiconductor device is manufactured by using the manufacturing method of the semiconductor device according to any one of claims 1 to 9.

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