Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure comprises the steps of providing a substrate; at least one first transistor and at least one second transistor which are distributed along a first direction parallel to the substrate are formed on one side of the substrate; the first transistor comprises a first gate, and the second transistor comprises a second gate; forming a photoresist layer on one side of the substrate, wherein the photoresist layer covers the substrate, the first transistor and the second transistor; wherein the photoresist layer has a first target thickness on the first grid electrode and has a second target thickness on the second grid electrode; the first target thickness is smaller than the second target thickness; and forming an ion doped region on the top of the photoresist layer and the top of the first grid electrode. According to the invention, the electrical parameters of different types of transistors in the integrated circuit can be independently regulated and controlled on the premise of not additionally introducing a mask, thereby facilitating the simplification of the working steps and the improvement of the electrical performance of the integrated circuit.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] As the integration of integrated circuits becomes higher and higher, semiconductor devices also tend to develop towards high density and miniaturization. Among them, metal-oxide-semiconductor (MOS) transistors are an important semiconductor device in integrated circuit chips. Threshold voltage (Vt) and gate resistance (RS_poly) are important electrical parameters of MOS transistors. There are different electrical parameter requirements between low-voltage metal-oxide semiconductor (LV MOS) transistors in the core circuit (Core) of integrated circuits and medium-voltage metal-oxide semiconductor (MV MOS) transistors in the input / output circuit (IO). In related technologies, the electrical parameters of MOS transistors are usually controlled by controlling the thickness of the gate dielectric layer and gate pre-injection.

[0003] However, in these conventional methods, multiple mask definitions are required for different device areas in the integrated circuit, and different gate structures are formed separately or separate ion implantation processes are performed on different gate structures, which easily increases the complexity of the integrated circuit manufacturing process and increases the cost. Summary of the invention

[0004] Based on this, the embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, so as to individually adjust the electrical parameters of different types of transistors in an integrated circuit without the need for additional mask plates, thereby helping to simplify the process steps and improve the electrical performance of the integrated circuit.

[0005] In order to achieve the above-mentioned purpose, on the one hand, some embodiments of the present application provide a method for manufacturing a semiconductor structure. The manufacturing method includes: providing a substrate; forming at least one first transistor and at least one second transistor distributed along a first direction parallel to the substrate on one side of the substrate; the first transistor includes a first gate, and the second transistor includes a second gate; forming a photoresist layer on one side of the substrate, the photoresist layer covering the substrate, the first transistor and the second transistor; wherein the photoresist layer has a first target thickness on the first gate and a second target thickness on the second gate; the first target thickness is less than the second target thickness; forming an ion doping region on the top of the photoresist layer and the top of the first gate.

[0006] In some embodiments, the implantation depth of the ion doped region is equal at all locations within the photoresist layer.

[0007] In some embodiments, the ion doped region has a target implantation depth; the target implantation depth is greater than the first target thickness and less than the second target thickness.

[0008] In some embodiments, a gap exists between the ion doped region and the second gate in a direction perpendicular to the substrate.

[0009] In some embodiments, a longitudinal cross-sectional area of ​​the first gate in a direction parallel to the substrate is smaller than a longitudinal cross-sectional area of ​​the second gate in a direction parallel to the substrate.

[0010] In some embodiments, an operating voltage of the first transistor is less than an operating voltage of the second transistor.

[0011] In some embodiments, after forming the ion-doped region on the top of the photoresist layer and the top of the first gate, the manufacturing method further includes: removing the photoresist layer and the ion-doped region in the photoresist layer.

[0012] On the other hand, the present application also provides a semiconductor structure according to some embodiments; the semiconductor structure can be prepared by the manufacturing method of the semiconductor structure in some of the above embodiments. The semiconductor structure includes a substrate, a photoresist layer and an ion doping region. One side of the substrate has at least one first transistor and at least one second transistor distributed along a first direction; the first transistor includes a first gate, and the second transistor includes a second gate; the photoresist layer is located on one side of the substrate, and the photoresist layer covers the substrate, the first transistor and the second transistor; wherein the photoresist layer has a first target thickness on the first gate and a second target thickness on the second gate; the first target thickness is less than the second target thickness; the ion doping region is located on the top of the photoresist layer and the top of the first gate.

[0013] In some embodiments, the ion doped region has a target implantation depth; the target implantation depth is greater than the first target thickness and less than the second target thickness.

[0014] In some embodiments, the photoresist layer and the ion-doped region in the photoresist layer are configured to be removed after the ion-doped region is formed.

[0015] The embodiments of the present application may or at least have the following advantages:

[0016] In the embodiment of the present application, a photoresist layer is formed, and a first target thickness is formed on the first gate of the first transistor, and a second target thickness is formed on the second gate of the second transistor, and the first target thickness is less than the second target thickness. In this way, the implantation depth of the ion-doped region can be controlled according to the first target thickness and the second target thickness, so that the ion-doped region can be formed only on the top of the first gate without ion-doping the second gate, thereby realizing the individual regulation of the electrical parameters (including threshold voltage and / or gate resistance, etc.) of the first transistor in the integrated circuit without affecting the electrical properties of the second transistor, and there is no need to define separate masks for different device regions where different transistors in the integrated circuit are located, which effectively simplifies the process steps and reduces the process difficulty. On this basis, it is also beneficial to accurately regulate the electrical parameters of different transistors in the integrated circuit, thereby facilitating the improvement of the electrical performance of the integrated circuit.

[0017] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor structure provided in some embodiments;

[0020] Figure 2 A schematic flow chart of another method for manufacturing a semiconductor structure provided in some embodiments;

[0021] Figure 3 is a schematic structural diagram of a substrate provided in some embodiments;

[0022] Figure 4 A schematic diagram of a structure obtained after forming a photoresist layer provided in some embodiments;

[0023] Figure 5 A schematic diagram of a structure obtained after forming an ion-doped region provided in some embodiments;

[0024] Figure 6 A schematic diagram of a structure obtained after removing a photoresist layer and an ion-doped region in the photoresist layer provided in some embodiments.

[0025] Description of reference numerals:

[0026] 1-substrate, A1-first device area, A2-second device area, T1-first transistor, G1-first gate, T2-second transistor, G2-second gate, AA-active area, 2-photoresist layer, 3-ion doping area, H1-first target thickness, H2-second target thickness, d-target implantation depth. DETAILED DESCRIPTION

[0027] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0029] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0030] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0031] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0032] The embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, so as to individually adjust the electrical parameters of different types of transistors in an integrated circuit without the need for additional mask plates, thereby helping to simplify the process steps and improve the electrical performance of the integrated circuit.

[0033] In some embodiments, see Figure 1 , the manufacturing method of the semiconductor structure includes the following steps S100~S300.

[0034] S100, providing a substrate; at least one first transistor and at least one second transistor distributed along a first direction parallel to the substrate are formed on one side of the substrate; the first transistor includes a first gate, and the second transistor includes a second gate.

[0035] S200, forming a photoresist layer on one side of the substrate, the photoresist layer covering the substrate, the first transistor and the second transistor; wherein the photoresist layer has a first target thickness on the first gate and a second target thickness on the second gate; the first target thickness is less than the second target thickness.

[0036] S300, forming an ion doping region on the top of the photoresist layer and the top of the first gate.

[0037] In the embodiment of the present application, a photoresist layer is formed, and a first target thickness is formed on the first gate of the first transistor, and a second target thickness is formed on the second gate of the second transistor, and the first target thickness is less than the second target thickness. In this way, the implantation depth of the ion-doped region can be controlled according to the first target thickness and the second target thickness, so that the ion-doped region can be formed only on the top of the first gate without ion-doping the second gate, thereby realizing the individual regulation of the electrical parameters (including threshold voltage and / or gate resistance, etc.) of the first transistor in the integrated circuit without affecting the electrical properties of the second transistor, and there is no need to define separate masks for different device regions where different transistors in the integrated circuit are located, which effectively simplifies the process steps and reduces the process difficulty. On this basis, it is also beneficial to accurately regulate the electrical parameters of different transistors in the integrated circuit, thereby facilitating the improvement of the electrical performance of the integrated circuit.

[0038] In some embodiments, see Figure 2 After step S300, the method for manufacturing the semiconductor structure further includes the following step S400.

[0039] S400, removing the photoresist layer and the ion-doped region in the photoresist layer.

[0040] It should be noted that after removing the photoresist layer and the ion-doped region in the photoresist layer, in the resulting structure, only the top of the first gate is formed with an ion-doped region, while the top of the second gate is not ion-doped. In this way, the embodiment of the present application can achieve separate regulation of the electrical parameters (including threshold voltage and / or gate resistance, etc.) of the first transistor in the integrated circuit without affecting the electrical properties of the second transistor, which is conducive to precise regulation of the electrical parameters of different transistors in the integrated circuit, thereby facilitating the improvement of the electrical performance of the integrated circuit.

[0041] It should be understood that although Figure 1~Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1~Figure 2 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0042] In order to more clearly illustrate the manufacturing method of the semiconductor structure in some of the above embodiments, the following embodiments are combined with Figure 3~Figure 6 Understand.

[0043] In some embodiments, the method for manufacturing a semiconductor structure includes the following steps S100 - S300 .

[0044] In step S100, refer to Figure 3 , providing a substrate 1; at least one first transistor T1 and at least one second transistor T2 distributed along a first direction (for example, X direction) parallel to the substrate 1 are formed on one side of the substrate 1; the first transistor T1 includes a first gate G1, and the second transistor T2 includes a second gate G2.

[0045] In some embodiments, base 1 includes a substrate.

[0046] For example, the substrate can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate should not limit the scope of protection of this application.

[0047] In some embodiments, the substrate 1 includes a first device region A1 and a second device region A2, wherein at least one first transistor T1 is formed in the first device region A1, and at least one second transistor T2 is formed in the second device region A2.

[0048] It should be noted that Figure 3 Although the example is given with three first transistors T1 and one second transistor T2, it can be understood that the number of the first transistor T1 and / or the second transistor T2 can be set to other numbers, and the present application does not limit this.

[0049] By way of example, the first transistor T1 and / or the second transistor T2 both include but are not limited to Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET for short).

[0050] For some examples, see Figure 3 The first transistor T1 and the second transistor T2 each include a plurality of active areas AA spaced apart along a first direction (e.g., X direction). The plurality of active areas AA are distributed on both sides of each first gate G1 in the substrate 1 in the first direction (e.g., X direction) and on both sides of each second gate G2 in the first direction (e.g., X direction).

[0051] In some embodiments, the size of each first gate G1 in the second direction (eg, Y direction) perpendicular to the substrate 1 is the same as the size of each second gate G2 in the second direction (eg, Y direction) perpendicular to the substrate 1 .

[0052] Illustratively, the second direction (eg, the Y direction) intersects the first direction (eg, the X direction).

[0053] By way of example, the material of the first gate G1 includes but is not limited to polysilicon (Poly).

[0054] By way of example, the material of the second gate G2 includes but is not limited to polysilicon (Poly).

[0055] In step S200, refer to Figure 4 A photoresist layer 2 is formed on one side of the substrate 1, and the photoresist layer 2 covers the substrate 1, the first transistor T1 and the second transistor T2; wherein the photoresist layer 2 has a first target thickness H1 on the first gate G1 and a second target thickness H2 on the second gate G2; the first target thickness H1 is less than the second target thickness H2.

[0056] It should be noted that the “thickness” here and below refers to the dimension in the second direction (eg, Y direction) perpendicular to the substrate 1 .

[0057] For example, the thickness of the photoresist layer 2 on the first gate G1 refers to the distance between the top of the photoresist layer 2 and the top of the first gate G1 in the second direction (for example, the Y direction) perpendicular to the substrate 1; the thickness of the photoresist layer 2 on the second gate G2 refers to the distance between the top of the photoresist layer 2 and the top of the second gate G2 in the second direction (for example, the Y direction) perpendicular to the substrate 1.

[0058] By way of example, the process of forming the photoresist layer 2 includes but is not limited to a coating process.

[0059] In some embodiments, an operating voltage of the first transistor T1 is less than an operating voltage of the second transistor T2 .

[0060] By way of example, the first transistor T1 includes but is not limited to a low voltage transistor, for example, a low voltage metal oxide semiconductor field effect transistor (abbreviated as LV MOS).

[0061] By way of example, the second transistor T2 includes but is not limited to a medium voltage transistor, for example, a medium voltage metal oxide semiconductor field effect transistor (MV MOS for short).

[0062] Illustratively, the number of the first transistors T1 is greater than the number of the second transistors T2.

[0063] In some embodiments, see Figure 3 or Figure 4 , a longitudinal cross-sectional area of ​​the first gate G1 in a direction parallel to the substrate 1 is smaller than a longitudinal cross-sectional area of ​​the second gate G2 in a direction parallel to the substrate 1 .

[0064] It should be noted that the photoresist layer 2 in the embodiment of the present application uses a photoresist material with good fluidity, and because the longitudinal cross-sectional area of ​​the first gate G1 of the first transistor T1 (for example, a low-voltage transistor) in a direction parallel to the substrate 1 is smaller than the longitudinal cross-sectional area of ​​the second gate G2 of the second transistor T2 (for example, a medium-voltage transistor) in a direction parallel to the substrate 1, it is easier to form a photoresist layer 2 with a smaller thickness on the first gate G1 and a photoresist layer 2 with a larger thickness on the second gate G2; in this way, it is beneficial to make the first target thickness H1 smaller than the second target thickness H2, thereby facilitating the individual regulation of the electrical parameters (including threshold voltage and / or gate resistance, etc.) of the first transistor T1 in the integrated circuit without affecting the electrical properties of the second transistor T2, and there is no need to define separate masks for different device regions where different transistors in the integrated circuit are located, which effectively simplifies the process steps and reduces the process difficulty. On this basis, it is also beneficial to accurately regulate the electrical parameters of different transistors in the integrated circuit, thereby facilitating the improvement of the electrical performance of the integrated circuit.

[0065] In step S300, refer to Figure 5 An ion doping region 3 is formed on the top of the photoresist layer 2 and the top of the first gate G1.

[0066] In some embodiments, please refer to Figure 5 , the implantation depth of the ion doping region 3 is equal everywhere in the photoresist layer 2 .

[0067] For example, the implantation depth of the ion-doped region 3 refers to the distance between the bottom of the ion-doped region 3 and the surface of the photoresist layer 2 in the second direction (eg, Y direction) perpendicular to the substrate 1 .

[0068] It should be noted that, in the embodiment of the present application, an ion doping region 3 is formed on the top of the first gate G1, and the implantation dose and doping type of the ion doping region 3 are controlled, so as to control the electrical parameters of the first transistor T1. For example, the threshold voltage (Vt) and the gate resistance (RS_poly) of the first transistor T1 can be changed, thereby improving the control accuracy of the electrical parameters of the transistor in the integrated circuit.

[0069] In some embodiments, please refer to Figure 5 , the ion-doped region 3 has a target implantation depth d; the target implantation depth d is greater than the first target thickness H1 and less than the second target thickness H2.

[0070] In some embodiments, there is a gap between the ion-doped region 3 and the second gate G2 in a direction perpendicular to the substrate 1 .

[0071] It should be explained that, by controlling the injection depth of the ion-doped region 3 according to the first target thickness H1 and the second target thickness H2, the target injection depth d is greater than the first target thickness H1 and less than the second target thickness H2, so that the ion-doped region 3 is only in contact with the top of the first gate G1 and is spaced from the second gate G2 in a second direction (e.g., Y direction) perpendicular to the substrate 1, thereby achieving separate regulation of the electrical parameters (including threshold voltage and / or gate resistance, etc.) of the first transistor T1 in the integrated circuit without affecting the electrical properties of the second transistor T2, and there is no need to define separate masks for different device regions where different transistors in the integrated circuit are located, which effectively simplifies the process steps and reduces the process difficulty. On this basis, it is also beneficial to accurately regulate the electrical parameters of different transistors in the integrated circuit, thereby facilitating improving the electrical performance of the integrated circuit.

[0072] In some embodiments, after step S300 , the method for manufacturing a semiconductor structure further includes the following step S400 .

[0073] In step S400, refer to Figure 6 , remove the photoresist layer 2 and the ion-doped region 3 in the photoresist layer 2.

[0074] Illustratively, the removal process of the photoresist layer 2 includes, but is not limited to, a debonding process.

[0075] Please refer to Figure 6 After removing the photoresist layer 2 and the ion-doped region 3 in the photoresist layer 2, in the semiconductor structure, only the top of the first gate G1 of the first transistor T1 is formed with the ion-doped region 3, while the second gate G2 of the second transistor T2 is not ion-doped. In this way, the electrical parameters (including threshold voltage and / or gate resistance, etc.) of the first transistor T1 in the integrated circuit can be separately regulated without affecting the electrical properties of the second transistor T2, which is beneficial to accurately regulate the electrical parameters of different transistors in the integrated circuit, thereby facilitating the improvement of the electrical performance of the integrated circuit.

[0076] For example, the size of the ion-doped region 3 formed on the top of the first gate G1 in the second direction (eg, Y direction) perpendicular to the substrate 1 may be the difference between the target implantation depth d and the first target thickness H1.

[0077] The present application also provides a semiconductor structure according to some embodiments, which can be prepared by the manufacturing method of the semiconductor structure in some of the above embodiments. The semiconductor structure also has the technical advantages of the manufacturing method of the above semiconductor structure. It should be noted that the parts that are the same or corresponding to the above embodiments can refer to the corresponding description of the above embodiments, and will not be described in detail below.

[0078] In some embodiments, see Figure 5 , the semiconductor structure includes a substrate 1, a photoresist layer 2 and an ion doping region 3. One side of the substrate 1 has at least one first transistor T1 and at least one second transistor T2 distributed along a first direction; the first transistor T1 includes a first gate G1, and the second transistor T2 includes a second gate G2; the photoresist layer 2 is located on one side of the substrate 1, and the photoresist layer 2 covers the substrate 1, the first transistor T1 and the second transistor T2; wherein the photoresist layer 2 has a first target thickness H1 on the first gate G1 and a second target thickness H2 on the second gate G2; the first target thickness H1 is less than the second target thickness H2; the ion doping region 3 is located on the top of the photoresist layer 2 and the top of the first gate G1.

[0079] In some embodiments, base 1 includes a substrate.

[0080] For example, the substrate can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate should not limit the scope of protection of this application.

[0081] In some embodiments, the substrate 1 includes a first device region A1 and a second device region A2, wherein at least one first transistor T1 is formed in the first device region A1, and at least one second transistor T2 is formed in the second device region A2.

[0082] It should be noted that Figure 5 Although the example is given with three first transistors T1 and one second transistor T2, it can be understood that the number of the first transistor T1 and / or the second transistor T2 can be set to other numbers, and the present application does not limit this.

[0083] For some examples, see Figure 5 The first transistor T1 and the second transistor T2 each include a plurality of active areas AA spaced apart along a first direction (e.g., X direction). The plurality of active areas AA are distributed on both sides of each first gate G1 in the substrate 1 in the first direction (e.g., X direction) and on both sides of each second gate G2 in the first direction (e.g., X direction).

[0084] In some examples, the operating voltage of the first transistor T1 is less than the operating voltage of the second transistor T2 .

[0085] By way of example, the first transistor T1 includes but is not limited to a low voltage transistor, for example, a low voltage metal oxide semiconductor field effect transistor (abbreviated as LV MOS).

[0086] By way of example, the second transistor T2 includes but is not limited to a medium voltage transistor, for example, a medium voltage metal oxide semiconductor field effect transistor (MV MOS for short).

[0087] For some examples, see Figure 5 , a longitudinal cross-sectional area of ​​the first gate G1 in a direction parallel to the substrate 1 is smaller than a longitudinal cross-sectional area of ​​the second gate G2 in a direction parallel to the substrate 1 .

[0088] In some embodiments, the ion-doped region 3 has a target implantation depth d; the target implantation depth d is greater than the first target thickness H1 and less than the second target thickness H2.

[0089] It should be noted that there is a gap between the ion-doped region 3 and the second gate G2 in the second direction (eg, Y direction) perpendicular to the substrate 1 .

[0090] In some embodiments, the photoresist layer 2 and the ion-doped region 3 in the photoresist layer 2 are intended to be removed after the ion-doped region 3 is formed.

[0091] In some examples, after the photoresist layer 2 and the ion doped region 3 in the photoresist layer 2 are removed, the following can be obtained: Figure 6 The structure shown in FIG. 1 is a semiconductor structure in which only the top of the first gate G1 of the first transistor T1 is formed with an ion doping region 3, while the second gate G2 of the second transistor T2 is not ion doped, and the size of the ion doping region 3 formed on the top of the first gate G1 in a second direction (for example, Y direction) perpendicular to the substrate 1 can be the difference between the target implantation depth d and the first target thickness H1.

[0092] In the description of this specification, the description with reference to the terms "some embodiments", "some examples", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0093] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; At least one first transistor and at least one second transistor distributed along a first direction parallel to the substrate are formed on one side of the substrate; the first transistor includes a first gate, and the second transistor includes a second gate; forming a photoresist layer on one side of the substrate, the photoresist layer covering the substrate, the first transistor and the second transistor; wherein the photoresist layer has a first target thickness on the first gate and a second target thickness on the second gate; and the first target thickness is less than the second target thickness; An ion doping region is formed on the top of the photoresist layer and the top of the first gate.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The implantation depth of the ion doping region is equal at all locations in the photoresist layer.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The ion doping region has a target implantation depth; the target implantation depth is greater than the first target thickness and less than the second target thickness.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The ion doping region is spaced apart from the second gate in a direction perpendicular to the substrate.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: A longitudinal cross-sectional area of ​​the first gate in a direction parallel to the substrate is smaller than a longitudinal cross-sectional area of ​​the second gate in a direction parallel to the substrate.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: An operating voltage of the first transistor is lower than an operating voltage of the second transistor.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: After forming an ion doping region on the top of the photoresist layer and the top of the first gate, the manufacturing method further includes: The photoresist layer and the ion-doped region in the photoresist layer are removed.

8. A semiconductor structure, characterized in that: include: substrate; One side of the substrate has at least one first transistor and at least one second transistor distributed along a first direction; the first transistor includes a first gate, and the second transistor includes a second gate; a photoresist layer, located on one side of the substrate, the photoresist layer covering the substrate, the first transistor and the second transistor; wherein the photoresist layer has a first target thickness on the first gate and a second target thickness on the second gate; the first target thickness is less than the second target thickness; The ion doping region is located on the top of the photoresist layer and the top of the first gate.

9. The semiconductor structure according to claim 8, characterized in that: The ion doping region has a target implantation depth; the target implantation depth is greater than the first target thickness and less than the second target thickness.

10. The semiconductor structure according to claim 8, characterized in that The photoresist layer and the ion-doped region in the photoresist layer are used to be removed after the ion-doped region is formed.

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