Zero-crossing detection circuit, method and power management chip applied to BUCK

Abstract

The present invention relates to the field of power management technology, and discloses a zero-crossing detection circuit, method, and power management chip for a buck (BUCK) circuit. In the zero-crossing detection circuit, a first end of a current mirror circuit is connected to a current source, and a second end of the current mirror circuit is connected to a first end of a trimming circuit. A first end of a sampling amplifier circuit is connected to a switch node of the buck circuit, a second end of the sampling amplifier circuit is connected to a second end of the trimming circuit, a third end of the sampling amplifier circuit is connected to a third end of the trimming circuit, and a fourth end of the sampling amplifier circuit is connected to a ground terminal. A first end of a comparison circuit is connected to a fifth end of the sampling amplifier circuit, a second end of the comparison circuit is connected to a sixth end of the sampling amplifier circuit, a third end of the comparison circuit is connected to a ground terminal, and a fourth end of the comparison circuit outputs a zero-crossing detection result. By implementing the present invention, the sensitivity of circuit detection and the trimming accuracy are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of power management, and in particular to a zero-crossing detection circuit and method applied to a BUCK, and a power management chip. Background Art

[0002] Zero-crossing detection circuits are crucial for controlling the energy consumption of power management chips. To conserve energy within the power management chip (BUCK), the chip typically enters power-saving mode when the inductor current reaches zero under light load conditions. However, the signal near zero is very weak, making accurate detection and precise adjustment of this weak zero-crossing signal a key challenge for zero-crossing detection circuits. Summary of the Invention

[0003] In view of this, the present invention provides a zero-crossing detection circuit, method and power management chip applied to BUCK to solve the problem that the zero-crossing detection circuit cannot accurately detect the zero-crossing signal and cannot accurately adjust the zero-crossing signal.

[0004] In a first aspect, the present invention provides a zero-crossing detection circuit for a BUCK, wherein the zero-crossing detection circuit comprises: a current mirror circuit, a trimming circuit, a sampling and amplifying circuit, a comparison circuit, and a controller, wherein:

[0005] A first end of the current mirror circuit is connected to a current source, a second end of the current mirror circuit is connected to a first end of the trimming circuit, and the current mirror circuit is used to copy the current to other internal power branches according to a preset proportional relationship;

[0006] A first end of the sampling and amplifying circuit is connected to a switch node of the buck circuit, a second end of the sampling and amplifying circuit is connected to a second end of the trimming circuit, a third end of the sampling and amplifying circuit is connected to a third end of the trimming circuit, and a fourth end of the sampling and amplifying circuit is connected to a ground end. The sampling and amplifying circuit is configured to perform voltage-to-current conversion and amplify a voltage signal at the switch node, and output an amplified current signal.

[0007] The first terminal of the comparison circuit is connected to the fifth terminal of the sampling and amplifying circuit, the second terminal of the comparison circuit is connected to the sixth terminal of the sampling and amplifying circuit, the third terminal of the comparison circuit is connected to the ground terminal, and the fourth terminal of the comparison circuit outputs the zero-crossing detection result to the controller. The comparison circuit is used to compare the amplified current signal with the ground terminal voltage and output the zero-crossing detection result;

[0008] The controller is also connected to the control end of the current mirror circuit and the control end of the adjustment circuit respectively. The controller selects the working mode of the current mirror circuit and the adjustment circuit according to the zero-crossing point detection result and adjusts the zero-crossing point.

[0009] The present invention provides a zero-crossing detection circuit for a buck (BUCK) circuit. Because the sampling and amplifier circuit has a large transconductance when operating in the saturation region, it can convert minute voltage changes in the switch into significant current changes for detection, thereby improving the circuit's detection sensitivity. Furthermore, the sampling and amplifier circuit operating in the saturation region can also convert minute voltage changes in the trimming circuit output into significant current changes, thereby improving the trimming accuracy of the zero-crossing detection circuit.

[0010] In an optional embodiment, the current mirror circuit includes a first transistor and a second transistor, wherein:

[0011] The first end of the first transistor is connected to the first end of the second transistor and an external power supply, respectively. The second end of the first transistor is connected to the current source. The control end of the first transistor is connected to the control end of the second transistor and the second end of the first transistor, respectively. The second end of the second transistor is connected to the first end of the trimming circuit.

[0012] In an optional embodiment, the current mirror circuit further includes a plurality of third transistors and a plurality of fourth transistors, wherein:

[0013] The first end of each of the third transistors is connected to an external power supply, the control end of each of the third transistors is connected to the control end of the first transistor and the control end of the second transistor respectively, the second end of each of the third transistors is connected to the first end of one of the fourth transistors, the second end of each of the fourth transistors is connected to the first end of the trimming circuit, and the control end of each of the fourth transistors is connected to the controller.

[0014] In an optional embodiment, the trimming circuit includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first resistor and a second resistor, wherein:

[0015] The first end of the fifth transistor is respectively connected to the second end of the current mirror circuit, the first end of the first resistor, the first end of the second resistor, and the first end of the eighth transistor. The second end of the fifth transistor is respectively connected to the second end of the sixth transistor and the second end of the sampling and amplifying circuit. The second end of the first resistor is connected to the first end of the sixth transistor, the second end of the second resistor is connected to the first end of the seventh transistor, and the second end of the seventh transistor is respectively connected to the second end of the eighth transistor and the third end of the sampling and amplifying circuit. The control end of the fifth transistor, the control end of the sixth transistor, the control end of the seventh transistor, and the control end of the eighth transistor are all connected to the controller.

[0016] In an optional embodiment, the trimming circuit further includes: a plurality of ninth transistors and a plurality of third resistors, wherein:

[0017] The first end of each of the third resistors is respectively connected to the first end of the fifth transistor, the first end of the first resistor, the first end of the second resistor, and the first end of the eighth transistor. The second end of each of the third resistors is connected to the first end of the ninth transistor. The second end of the ninth transistor is connected to the second end and / or the third end of the sampling and amplifier circuit.

[0018] In an optional implementation, the sampling and amplifying circuit includes: a tenth transistor and an eleventh transistor, wherein:

[0019] The first end of the tenth transistor is connected to the second end of the trimming circuit, the second end of the tenth transistor is connected to the first end of the comparison circuit, and the control end of the tenth transistor is connected to the switch node of the buck circuit;

[0020] The first end of the eleventh transistor is connected to the third end of the trimming circuit, the second end of the eleventh transistor is connected to the second end of the comparison circuit, and the control end of the eleventh transistor is connected to the ground end.

[0021] In an optional implementation, the sampling and amplifying circuit further includes: a twelfth transistor and a thirteenth transistor, wherein:

[0022] A first end of the twelfth transistor is connected to the control end of the tenth transistor, a second end of the twelfth transistor is connected to a switch node of the BUCK circuit, and a control end of the twelfth transistor is connected to an external power supply;

[0023] The first end of the thirteenth transistor is connected to the control end of the eleventh transistor, the second end of the thirteenth transistor is connected to the ground end, and the control end of the twelfth transistor is connected to an external power supply.

[0024] In an optional implementation, the comparison circuit includes: a comparator, a fourth resistor, and a fifth resistor, wherein:

[0025] The non-inverting input terminal of the comparator is connected to the second terminal of the eleventh transistor and the first terminal of the fifth resistor respectively, and the inverting input terminal of the comparator is connected to the second terminal of the tenth transistor and the first terminal of the fourth resistor;

[0026] The second end of the fourth resistor and the second end of the fifth resistor are both grounded.

[0027] In a second aspect, the present invention provides a power management chip, comprising the zero-crossing detection circuit applied to a BUCK according to the first aspect or any corresponding embodiment thereof.

[0028] The present invention provides a power management chip that can accurately detect the zero-crossing point by adopting the above-mentioned zero-crossing detection circuit applied to BUCK, and enters a power saving mode when the inductor current is zero, thereby improving the energy consumption of the power management chip.

[0029] In a third aspect, the present invention provides a zero-crossing detection method applied to a buck converter (BUCK), based on the zero-crossing detection circuit applied to a buck converter (BUCK) according to the first aspect or any corresponding embodiment thereof, the zero-crossing detection method comprising:

[0030] Obtaining an actual zero-crossing point of the inductor current, and selecting an operating mode of the current mirror circuit and the trimming circuit according to the actual zero-crossing point of the inductor current to obtain a trimmed current;

[0031] Collect the voltage signal at the switch node, perform voltage-current conversion and amplification processing, and output the amplified current signal;

[0032] The amplified current signal is compared with the ground terminal voltage to obtain a zero-crossing point, and the zero-crossing point is adjusted according to the adjustment current.

[0033] The present invention provides a zero-crossing detection method for a buck (BUCK) circuit. Because the sampling and amplifier circuit has a large transconductance when operating in the saturation region, it can convert small voltage changes in the switch into significant current changes for detection, thereby improving the circuit's detection sensitivity. Furthermore, the sampling and amplifier circuit operating in the saturation region can also convert small voltage changes in the trimming circuit output into significant current changes, thereby improving the trimming accuracy of the zero-crossing detection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 1 is a schematic diagram of a BUCK circuit according to an embodiment of the present invention;

[0036] Figure 2 1 is a principle block diagram of a zero-crossing detection circuit applied to a BUCK according to an embodiment of the present invention;

[0037] Figure 31 is a schematic diagram of a zero-crossing detection circuit applied to a BUCK according to an embodiment of the present invention;

[0038] Figure 4 1 is a schematic diagram of another zero-crossing detection circuit applied to a BUCK according to an embodiment of the present invention;

[0039] Figure 5 FIG. 4 is a flow chart of a zero-crossing detection method applied to a BUCK according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0041] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0042] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components; wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0043] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0044] BUCK circuit framework Figure 1 As shown, the BUCK circuit can usually include a power tube Q 上 And the power tube Q 下, and connected with other external devices (such as inductors, capacitors and resistors, etc.) to achieve functions such as boost or buck. 上 and down tube Q 下 The connection point is the switch node SW. 下 On, upper tube Q 上 When turned off, the current flowing through the lower tube Q of the power tube 下 The current flowing through the inductor L is equal to the current flowing through the inductor L, that is, I bottom =I L Therefore, the potential of SW is -I L R bottom , I L is the current flowing through the inductor, R bottom Q for the down tube 下 If R is known, bottom The value of SW and I L Since the potential of SW corresponds to the current flowing through the inductor, the inductor current I can be known by detecting the voltage value of SW. L Therefore, the inductor current I can be detected during zero-crossing detection. L The zero point from positive to negative is converted into the zero point where the potential of the detection SW changes from negative to positive.

[0045] Based on the above analysis, the present invention provides a zero-crossing detection circuit applied to BUCK, such as Figure 2 As shown, the system includes: a current mirror circuit, a trimming circuit, a sampling amplifier circuit, a comparison circuit, and a controller. The first end of the current mirror circuit is connected to a current source, and the second end of the current mirror circuit is connected to the first end of the trimming circuit. The first end of the sampling amplifier circuit is connected to the switch node of the buck circuit, the second end of the sampling amplifier circuit is connected to the second end of the trimming circuit, the third end of the sampling amplifier circuit is connected to the third end of the trimming circuit, and the fourth end of the sampling amplifier circuit is connected to ground. The first end of the comparison circuit is connected to the fifth end of the sampling amplifier circuit, the second end of the comparison circuit is connected to the sixth end of the sampling amplifier circuit, the third end of the comparison circuit is connected to ground, and the fourth end of the comparison circuit outputs a zero-crossing detection result, ZCD_OUT, to the controller. The controller is also connected to the control end of the current mirror circuit and the control end of the trimming circuit, respectively.

[0046] Specifically, the current source is used to provide a reference current. The current mirror circuit is used to copy the reference current to other internal power branches according to a preset proportional relationship. The sampling and amplifier circuit is used to convert and amplify the voltage signal at the switch node, and output the amplified current signal. The comparison circuit is used to compare the amplified current signal with the ground voltage and output the zero-crossing detection result. The controller selects the operating mode of the current mirror circuit and the adjustment circuit based on the zero-crossing detection result and adjusts the zero-crossing point. The zero-crossing detection result output by the comparison circuit is the actual zero-crossing point of the inductor current.

[0047] On the power tube Q 上 Cut-off, power tube lower tube Q 下 When conducting, the voltage signal at SW reflects the current flowing through inductor L. Therefore, the inductor current can usually be indirectly detected by monitoring the voltage change at SW. Because the sampling amplifier circuit has a large transconductance when operating in the saturation region, it can convert small voltage changes at SW into significant current changes for detection, thereby improving the circuit's detection sensitivity. Furthermore, the sampling amplifier circuit operating in the saturation region can also convert small voltage changes at the trimming circuit output into significant current changes, thereby improving the trimming accuracy of the zero-crossing detection circuit.

[0048] In an optional embodiment, as Figure 3 As shown, the current mirror circuit includes a first transistor PM0 and a second transistor PM1. A first terminal of the first transistor PM0 is connected to a first terminal of the second transistor PM1 and an external power supply VDD, respectively. A second terminal of the first transistor PM0 is connected to a current source. A control terminal of the first transistor PM0 is connected to a control terminal of the second transistor PM1 and a second terminal of the first transistor PM0, respectively. A second terminal of the second transistor PM1 is connected to a first terminal of the trimming circuit.

[0049] Specifically, the current source is a reference current source, and its current is I0. The first transistor PM0 and the second transistor PM1 form a current mirror circuit, and the currents flowing through them are I1 and I2 respectively, and the size parameters satisfy the relationship Then i1=I2=I0, wherein the first transistor PM0 and the second transistor PM1 are both MOS transistors, W is the channel width of the MOS transistor, and L is the channel length of the MOS transistor.

[0050] In an optional implementation, the current mirror circuit may be expanded, such as Figure 4As shown, the current mirror circuit may further include a plurality of third transistors PM2 and a plurality of fourth transistors PM3. A first terminal of each third transistor PM2 is connected to an external power supply VDD, a control terminal of each third transistor PM2 is connected to the control terminal of the first transistor PM0 and the control terminal of the second transistor PM1, respectively, a second terminal of each third transistor PM2 is connected to a first terminal of a fourth transistor PM3, a second terminal of each fourth transistor PM3 is connected to a first terminal of the trimming circuit, and a control terminal of each fourth transistor PM3 is connected to a controller, wherein Trim1 is a control signal sent by the controller.

[0051] Specifically, after the current mirror circuit is expanded, the first transistor PM0, the second transistor PM1 and the third transistor PM2 constitute a current mirror circuit, and the currents flowing through the circuit are I1, I2 and I3 respectively, and the size parameters satisfy the relationship Then, I1 = I2 = i3 = i0. Both the third transistor PM2 and the fourth transistor PM3 are MOS transistors. The fourth transistor PM3 switches the third transistor PM2. When the fourth transistor PM3 is on, the third transistor PM2 is input into the current mirror circuit; when the fourth transistor PM3 is off, the third transistor PM2 is removed from the current mirror circuit. By expanding the current mirror circuit, the zero-crossing detection circuit can achieve multi-level adjustment.

[0052] In an optional embodiment, as Figure 3 As shown, the trimming circuit includes: a fifth transistor PM4, a sixth transistor PM5, a seventh transistor PM6, an eighth transistor PM7, a first resistor R1, and a second resistor R2. The first end of the fifth transistor PM4 is respectively connected to the second end of the current mirror circuit, the first end of the first resistor R1, the first end of the second resistor R2, and the first end of the eighth transistor PM7. The second end of the fifth transistor PM4 is respectively connected to the second end of the sixth transistor PM5 and the second end of the sampling and amplifying circuit. The second end of the first resistor R1 is connected to the first end of the sixth transistor PM5, the second end of the second resistor R2 is connected to the first end of the seventh transistor PM6, and the second end of the seventh transistor PM6 is respectively connected to the second end of the eighth transistor PM7 and the third end of the sampling and amplifying circuit. The control ends of the fifth transistor PM4, the sixth transistor PM5, the seventh transistor PM6, and the eighth transistor PM7 are all connected to the controller.

[0053] Specifically, the fifth transistor PM4, the sixth transistor PM5, the seventh transistor PM6, the eighth transistor PM7, the first resistor R1, and the second resistor R2 constitute a trimming circuit. The resistance of the first resistor R1 is R1, the resistance of the second resistor R2 is R2, and R1 = R2 = R0. Trim2, Trim3, Trim4, and Trim5 are control signals sent by the controller.

[0054] In this embodiment of the present invention, the fifth transistor PM4, the sixth transistor PM5, the seventh transistor PM6, and the eighth transistor PM7 are all MOS transistors. Trim2, Trim3, Trim4, and Trim5 are connected to the gates of PM4, PM5, PM6, and PM7, respectively, to control the on and off of the corresponding MOS transistors. When the control signal is high, the controlled MOS transistor is turned off, and the corresponding branch is closed. When the control signal is low, the controlled MOS transistor is turned on, and the corresponding branch is conductive.

[0055] In an optional implementation, the trimming circuit can be expanded to further include: a plurality of ninth transistors and a plurality of third resistors. Figure 4 As shown, the plurality of ninth transistors include a plurality of transistors PM8 and / or a plurality of transistors PM9, and the third resistor includes a plurality of resistors R3 and / or a plurality of resistors R4. The branch formed by the resistor R3 and the transistor PM8 is connected in parallel to both ends of the branch formed by the first resistor R1 and the sixth transistor PM5. The branch formed by the resistor R4 and the transistor PM9 is connected in parallel to both ends of the branch formed by the second resistor R2 and the seventh transistor PM6. The first end of each resistor R3 is respectively connected to the first end of the fifth transistor PM4, the first end of the first resistor R1, the first end of the second resistor R2, one end of each resistor R4, and the first end of the eighth transistor PM7. The second end of each resistor R3 is connected to the first end of the transistor PM8, and the second end of the transistor PM8 is connected to the second end of the sampling and amplifying circuit. The first end of each resistor R4 is respectively connected to the first end of the fifth transistor PM4, the first end of the first resistor R1, the first end of the second resistor R2, one end of each resistor R3, and the first end of the eighth transistor PM7. The second end of each resistor R4 is connected to the first end of the transistor PM9, and the second end of the transistor PM9 is connected to the third end of the sampling and amplifying circuit.

[0056] Specifically, transistor PM8 and resistor R3 can be added only to the left half of the trimming circuit, resistor R4 and transistor PM9 can be added only to the right half, or transistor PM8 and resistor R3 can be added to the left half while resistor R4 and transistor PM9 are added to the right half. The resistance values ​​of resistors R3 and R4 in each branch can be equal or unequal. Transistors PM8 and PM9 are MOS transistors. By expanding the trimming circuit, the zero-crossing detection circuit can achieve multi-level trimming.

[0057] In an optional embodiment, as Figure 3 and Figure 4 As shown, the sampling and amplifying circuit includes a tenth transistor PM10 and an eleventh transistor PM11. A first terminal of the tenth transistor PM10 is connected to the second terminal of the trimming circuit, a second terminal of the tenth transistor PM10 is connected to the first terminal of the comparison circuit, and a control terminal of the tenth transistor PM10 is connected to the switch node SW of the buck circuit. A first terminal of the eleventh transistor PM11 is connected to the third terminal of the trimming circuit, a second terminal of the eleventh transistor PM11 is connected to the second terminal of the comparison circuit, and a control terminal of the eleventh transistor PM11 is connected to ground.

[0058] Specifically, such as Figure 3 and Figure 4 As shown, the sampling and amplifying circuit further includes: a twelfth transistor NMd1 and a thirteenth transistor NMd2. A first end of the twelfth transistor NMd1 is connected to the control end of the tenth transistor PM10, a second end of the twelfth transistor NMd1 is connected to the switch node SW of the buck circuit, and a control end of the twelfth transistor NMd1 is connected to an external power supply VDD. A first end of the thirteenth transistor NMd2 is connected to the control end of the eleventh transistor PM11, a second end of the thirteenth transistor NMd2 is connected to ground, and a control end of the twelfth transistor NMd1 is connected to the external power supply VDD.

[0059] In the embodiment of the present invention, the tenth transistor PM10 and the eleventh transistor PM11 are both MOS transistors. The gates of PM10 and PM11 are comparative voltage input terminals that receive voltage signals. SW is connected to the gate of PM10 via NMd1, and GND is connected to the gate of PM11 via NMd2. According to the characteristics of MOS transistors, when PM10 and PM11 operate in the saturation region, PM10 and PM11 have large transconductances, which can convert small gate voltage changes into significant current changes. After conversion by the sampling and amplifier circuit, the voltage signal that was originally difficult to measure is converted into a current signal that is easy to measure, so the sampling and amplifier circuit has high sensitivity. As long as the voltage difference across R5 and R6 is less than the threshold voltage of PM10 and PM11, PM10 and PM11 can operate in the saturation region. For example, the currents flowing through PM10, R5 and R6, PM11 are I4 and I5, respectively, and R5 = R6 = R t , the voltages across resistors R5 and R6 are R t *I4, R t *I5, guaranteed R t *I4 <Vth、R t*I5 < Vth (where Vth is the threshold voltage of PM10 and PM11), which can make PM10 and PM11 operate in the saturation region. At the same time, it can be known that the potential at point A is R t *I4, then the potential at point B is R t *I5.

[0060] Furthermore, the twelfth transistor NMd1 and the thirteenth transistor NMd2 are DMOS. NMd1 can prevent the high voltage that appears at SW from being input to the gate of PM10. NMd2 is a matching circuit, which can reduce the mismatch of the circuit and improve the accuracy of the circuit.

[0061] In an optional implementation, as Figure 3 and Figure 4 shown, the comparison circuit includes: a comparator U1, a fourth resistor R5, and a fifth resistor R6. Among them, the non-inverting input terminal of the comparator U1 is respectively connected to the second terminal of the eleventh transistor PM11 and the first terminal of the fifth resistor R6, and the inverting input terminal of the comparator U1 is connected to the second terminal of the tenth transistor PM10 and the first terminal of the fourth resistor R5. The second terminals of the fourth resistor R5 and the fifth resistor R6 are both grounded.

[0062] Specifically, the comparator U1 is used to compare the potentials of point A and point B. When the potential at point B is greater than the potential at point A, the output ZCD_OUT is at a high level, indicating that the inductor current has passed through zero. When the potential at point B is less than the potential at point A, the output ZCD_OUT is at a low level, indicating that the inductor current has not passed through zero. When SW > 0, that is, I L <0, that is, the gate voltage of PM10 is greater than the gate voltage of PM11, and I4 < I5. When the potential at point B is greater than the potential at point A, the output ZCD_OUT is at a high level, and the inductor current has passed through zero. When SW < 0, that is, I L > 0, that is, the gate voltage of PM10 is less than the gate voltage of PM11, and I4 > I5. When the potential at point B is less than the potential at point A, the output ZCD_OUT is at a low level, and the inductor current has not passed through zero. At the zero-crossing moment, I4 = I5, and the gate-source voltages of PM10 and PM11 are equal.

[0063] In an optional implementation, as shown in the following table, it is an example trimming circuit correspondence table, where L represents low level, H represents high level; I is the actual zero-crossing point of the inductor current. After the current mirror circuit and the trimming circuit are expanded, the trimming circuit correspondence table will increase synchronously.

[0064] Table 1

[0065]

[0066] When the power management chip is tested, the actual zero-crossing point of the inductor current is obtained. The controller selects the Trim1, Trim2, Trim3, Trim4, and Trim5 level signals corresponding to this actual zero-crossing point according to Table 1. The controller then sends these Trim1, Trim2, Trim3, Trim4, and Trim5 level signals to the corresponding MOS transistors, controlling the current mirror circuit and trimming circuit to execute the corresponding operating mode to adjust the actual zero-crossing point.

[0067] by Figure 3 For example, when the actual zero crossing point of the inductor current is When PM3 is turned on, the controller outputs Trim1 = L to PM3, Trim2 = H to PM4, Trim3 = L to PM5, Trim4 = H to PM6, and Trim5 = L to PM7. At this time, PM3 is off, PM4 is on, PM5 is off, PM6 is on, and PM7 is off. When PM3 is turned on, I4 = I5 = I0 at the zero-crossing moment. When PM3 is turned off, I4 = I5 = I0 at the zero-crossing moment. When PM4 is turned on, PM5 is turned off, PM6 is turned on, and PM7 is turned off, the source potential of PM10 is greater than the source potential of PM11, and the difference is I5*R2=I5*R0. At the zero-crossing moment, the gate-source voltages of PM10 and PM11 are equal, so SW=I5*R2=I5*R0. When ZCD_OUT is detected to change from low to high, I5*R0=-I L R bottom , so the adjustment amount for the actual zero-crossing point I of the inductor current is

[0068] When the actual zero crossing point of the inductor current is When PM3 is off, the controller outputs Trim1 = L to PM3, Trim2 = L to PM4, Trim3 = H to PM5, Trim4 = L to PM6, Trim5 = H to PM7. At this time, PM3 is off, PM4 is off, PM5 is on, PM6 is off, and PM7 is on. When PM3 is off, there is a zero-crossing moment. When PM4 is off, PM5 is on, PM6 is off, and PM7 is on, the gate potential of PM10 is less than the gate potential of PM11, and the difference is I4*R1=I4*R0. At the zero-crossing moment, the gate-source voltages of PM10 and PM11 are equal, so SW=-I4*R1=-I4*R0. When ZCD_OUT changes from low to high, -I4*R0=-I L R bottom , so the adjustment amount for the actual zero-crossing point I of the inductor current is

[0069] This circuit can achieve multi-level adjustment, see Table 1. The minimum adjustment range is If I0 = 1uA, R0 = 100Ω, and R0 = 50mΩ, the minimum adjustment amplitude is 1mA, which is very accurate. This circuit has high sensitivity and can accurately detect current changes near zero. The trimming circuit can also adjust the zero point determination with an adjustment accuracy of up to 1mA.

[0070] The present invention provides a power management chip, comprising the above-mentioned zero-crossing detection circuit applied to BUCK.

[0071] The present invention provides a power management chip that can accurately detect the zero-crossing point by adopting the above-mentioned zero-crossing detection circuit applied to BUCK, and enters a power saving mode when the inductor current is zero, thereby improving the energy consumption of the power management chip.

[0072] The present invention provides a zero-crossing detection method applied to BUCK, based on the above-mentioned zero-crossing detection circuit applied to BUCK, such as Figure 5 As shown, the zero-crossing detection method includes the following steps:

[0073] Step S1: collecting a voltage signal at a switch node and amplifying the voltage signal.

[0074] Specifically, SW is connected to the gate of PM10 via NMd1, and GND is connected to the gate of PM11 via NMd2. Because the sampling and amplifier circuit has a large transconductance when operating in the saturation region, it can convert small voltage changes in SW into significant current changes for detection, thereby improving the circuit's detection sensitivity. Furthermore, the sampling and amplifier circuit operating in the saturation region can also convert small voltage changes in the trimming circuit output into significant current changes, thereby improving the trimming circuit's accuracy.

[0075] Step S2: Compare the amplified voltage signal with the ground terminal voltage to obtain a zero-crossing detection result.

[0076] Specifically, the comparison circuit is used to compare the amplified current signal with the ground terminal voltage and output a zero-crossing detection result.

[0077] Step S3, selecting the operating mode of the current mirror circuit and the adjustment circuit according to the zero-crossing point detection result, and adjusting the zero-crossing point.

[0078] Specifically, the zero-crossing point detection result output by the comparison circuit is the actual zero-crossing point of the inductor current. The Trim1, Trim2, Trim3, Trim4, and Trim5 level signals corresponding to this actual zero-crossing point are selected based on the trimming circuit correspondence table. These Trim1, Trim2, Trim3, Trim4, and Trim5 level signals are sent to the corresponding MOS transistors, controlling the current mirror circuit and trimming circuit to execute the corresponding operating modes and trimming the actual zero-crossing point of the inductor current.

[0079] The further functional description of each of the above steps is the same as that of the above corresponding embodiments and will not be repeated here.

[0080] The present invention provides a zero-crossing detection method for a buck (BUCK) circuit. Because the sampling and amplifier circuit has a large transconductance when operating in the saturation region, it can convert small voltage changes in the switch into significant current changes for detection, thereby improving the circuit's detection sensitivity. Furthermore, the sampling and amplifier circuit operating in the saturation region can also convert small voltage changes in the trimming circuit output into significant current changes, thereby improving the trimming accuracy of the zero-crossing detection circuit.

[0081] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A zero-crossing detection circuit applied to a BUCK, characterized in that: The zero-crossing detection circuit includes: a current mirror circuit, a trimming circuit, a sampling and amplifying circuit, a comparison circuit and a controller, wherein: A first end of the current mirror circuit is connected to a current source, a second end of the current mirror circuit is connected to a first end of the trimming circuit, and the current mirror circuit is used to copy the current to other internal power branches according to a preset proportional relationship; A first end of the sampling and amplifying circuit is connected to a switch node of the buck circuit, a second end of the sampling and amplifying circuit is connected to a second end of the trimming circuit, a third end of the sampling and amplifying circuit is connected to a third end of the trimming circuit, and a fourth end of the sampling and amplifying circuit is connected to a ground end. The sampling and amplifying circuit is configured to perform voltage-to-current conversion and amplify a voltage signal at the switch node, and output an amplified current signal. The first terminal of the comparison circuit is connected to the fifth terminal of the sampling and amplifying circuit, the second terminal of the comparison circuit is connected to the sixth terminal of the sampling and amplifying circuit, the third terminal of the comparison circuit is connected to the ground terminal, and the fourth terminal of the comparison circuit outputs the zero-crossing detection result to the controller. The comparison circuit is used to compare the amplified current signal with the ground terminal voltage and output the zero-crossing detection result; The controller is also connected to the control end of the current mirror circuit and the control end of the trimming circuit respectively, and the controller selects the working mode of the current mirror circuit and the trimming circuit according to the zero-crossing point detection result, and trims the zero-crossing point; The sampling and amplifying circuit includes: a tenth transistor and an eleventh transistor, wherein: The first end of the tenth transistor is connected to the second end of the trimming circuit, the second end of the tenth transistor is connected to the first end of the comparison circuit, and the control end of the tenth transistor is connected to the switch node of the buck circuit; The first end of the eleventh transistor is connected to the third end of the trimming circuit, the second end of the eleventh transistor is connected to the second end of the comparison circuit, and the control end of the eleventh transistor is connected to the ground end; The comparison circuit includes: a comparator, a fourth resistor and a fifth resistor, wherein: The non-inverting input terminal of the comparator is connected to the second terminal of the eleventh transistor and the first terminal of the fifth resistor respectively, and the inverting input terminal of the comparator is connected to the second terminal of the tenth transistor and the first terminal of the fourth resistor; The second end of the fourth resistor and the second end of the fifth resistor are both grounded.

2. The zero-crossing detection circuit applied to BUCK according to claim 1, characterized in that: The current mirror circuit includes a first transistor and a second transistor, wherein: The first end of the first transistor is connected to the first end of the second transistor and an external power supply, respectively. The second end of the first transistor is connected to the current source. The control end of the first transistor is connected to the control end of the second transistor and the second end of the first transistor, respectively. The second end of the second transistor is connected to the first end of the trimming circuit.

3. The zero-crossing detection circuit applied to BUCK according to claim 2, characterized in that: The current mirror circuit further includes a plurality of third transistors and a plurality of fourth transistors, wherein: The first end of each of the third transistors is connected to an external power supply, the control end of each of the third transistors is connected to the control end of the first transistor and the control end of the second transistor respectively, the second end of each of the third transistors is connected to the first end of one of the fourth transistors, the second end of each of the fourth transistors is connected to the first end of the trimming circuit, and the control end of each of the fourth transistors is connected to the controller.

4. The zero-crossing detection circuit applied to BUCK according to claim 1, characterized in that: The trimming circuit includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first resistor and a second resistor, wherein: The first end of the fifth transistor is respectively connected to the second end of the current mirror circuit, the first end of the first resistor, the first end of the second resistor, and the first end of the eighth transistor. The second end of the fifth transistor is respectively connected to the second end of the sixth transistor and the second end of the sampling and amplifying circuit. The second end of the first resistor is connected to the first end of the sixth transistor, the second end of the second resistor is connected to the first end of the seventh transistor, and the second end of the seventh transistor is respectively connected to the second end of the eighth transistor and the third end of the sampling and amplifying circuit. The control end of the fifth transistor, the control end of the sixth transistor, the control end of the seventh transistor, and the control end of the eighth transistor are all connected to the controller.

5. The zero-crossing detection circuit applied to BUCK according to claim 4, characterized in that: The trimming circuit further includes: a plurality of ninth transistors and a plurality of third resistors, wherein: The first end of each of the third resistors is respectively connected to the first end of the fifth transistor, the first end of the first resistor, the first end of the second resistor, and the first end of the eighth transistor. The second end of each of the third resistors is connected to the first end of the ninth transistor. The second end of the ninth transistor is connected to the second end and / or the third end of the sampling and amplifier circuit.

6. The zero-crossing detection circuit applied to BUCK according to claim 1, characterized in that: The sampling and amplifying circuit further includes: a twelfth transistor and a thirteenth transistor, wherein: A first end of the twelfth transistor is connected to the control end of the tenth transistor, a second end of the twelfth transistor is connected to a switch node of the BUCK circuit, and a control end of the twelfth transistor is connected to an external power supply; The first end of the thirteenth transistor is connected to the control end of the eleventh transistor, the second end of the thirteenth transistor is connected to the ground end, and the control end of the twelfth transistor is connected to an external power supply.

7. A power management chip, characterized in that: The invention comprises the zero-crossing detection circuit applied to a BUCK as claimed in any one of claims 1 to 6.

8. A zero-crossing detection method applied to BUCK, characterized in that: Based on the zero-crossing detection circuit applied to a BUCK according to any one of claims 1 to 6, the zero-crossing detection method includes: Obtaining an actual zero-crossing point of the inductor current, and selecting an operating mode of the current mirror circuit and the trimming circuit according to the actual zero-crossing point of the inductor current to obtain a trimmed current; Collect the voltage signal at the switch node, perform voltage-current conversion and amplification processing, and output the amplified current signal; The amplified current signal is compared with the ground terminal voltage to obtain a zero-crossing point, and the zero-crossing point is adjusted according to the adjustment current.

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