High-precision analog circuit, chip and IP for monitoring NBTI effect
By designing a high-precision simulation circuit including an NBTI effect monitoring unit, a bandgap reference circuit and a new hysteresis comparator, the problems of large chip area, high design complexity and low accuracy when monitoring NBTI effects in the prior art are solved, and simple and accurate NBTI effect monitoring under different conditions is achieved.
Patent Information
- Application Number
- CN202510071357.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-16
- Publication Date
- 2025-05-13
AI Technical Summary
When monitoring the NBTI effect, the prior art faces problems such as large chip area, high design complexity and low accuracy, and is affected by the power supply voltage, process and temperature, resulting in inaccurate monitoring results.
A high-precision analog circuit is designed, including an NBTI effect monitoring unit, a bandgap reference circuit and a new hysteresis comparator. By converting the NBTI effect into a voltage signal, and outputting early warning signals using the reference current and reference voltage, it is designed to monitor the NBTI effect.
It realizes the monitoring of NBTI effects in a simple and accurate manner under different processes, temperatures and power supply voltages, and solves the problems of large chip area, high design complexity and low accuracy in the existing technology.
Smart Images
Figure CN119986315A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a high-precision analog circuit, chip and IP for monitoring NBTI effects. Background Art
[0002] Due to the rapid development of semiconductor technology, the negative bias temperature instability (NBTI) effect has become more and more significant in devices and circuits. When subjected to stress, it affects the threshold voltage of MOS transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) to reduce the performance of analog or digital circuits, such as parameter mismatch in analog circuits and timing drift in digital circuits.
[0003] In order to monitor the NBTI effect of the chip and provide early warning, the first method is to use two ring oscillators to monitor the frequency degradation degree of the ring oscillator affected by the NBTI effect. The higher the degradation degree, the stronger the NBTI effect.
[0004] The second method uses a large number of sensors, VCO (Voltage-Controlled Oscillator) circuits and digital circuits (including triggers, registers, etc.) to monitor the frequency changes caused by the NBTI effect.
[0005] The third method is to monitor the threshold voltage change of the device affected by the NBTI effect to provide early warning, most of which is done through a comparator. Since the NBTI effect has a recovery effect - when the stress of the device is removed, its threshold voltage will recover. Therefore, in order to improve the accuracy of monitoring, the comparator is often changed to a hysteresis comparator circuit. The hysteresis function of the comparator can be achieved through external circuit positive feedback, comparator internal positive feedback or Schmitt trigger. First, external positive feedback mainly connects the input and output of the comparator through a resistor to form a positive feedback path; second, by introducing two additional MOS transistors inside the comparator, a positive feedback structure is realized, and its width-to-length ratio is set to be greater than the width-to-length ratio in a normal comparator, so that the positive feedback effect of the circuit is greater than the negative feedback, so that the overall circuit is in positive feedback; third, Schmitt trigger, Schmitt trigger is a special gate circuit. Although the circuit structure is simple and the voltage amplification capability is small, its hysteresis interval is determined by the internal MOS tube size and the conduction threshold voltage of the MOS tube and the power supply voltage, which is easy to design.
[0006] Since the circuit for monitoring the NBTI effect needs to be embedded as an IP in the overall analog chip, this IP must be small in area and low in cost. And when it is embedded in different circuits, it will encounter different power supply voltages. Secondly, after the circuit design is completed, it needs to be taped out. Due to the differences in equipment and errors in operating methods of the process manufacturers, the processes in the circuit will be different. At the same time, since the NBTI effect intensifies with the increase of temperature, the influence of temperature must also be considered. These situations will cause changes in the characteristics of the circuit, making the results very inaccurate.
[0007] The first method estimates the circuit NBTI effect by frequency detection using dual ring oscillators. In this method, two ring oscillators are required to use clocks to switch their operation processes. However, when the circuit encounters process problems during actual tape-out, the frequency of the clock will change greatly. At this time, the frequency generated by the ring oscillator will have obvious phase errors, making the circuit unsuitable for IP integration in the chip. In addition, since analog circuits and digital circuits will interfere greatly with each other when they are together, this pure digital circuit is not suitable for monitoring the NBTI effect of analog circuits.
[0008] The second method uses a large number of sensors, the circuit is complex, the area is huge, and it is not suitable for use as an IP. Similarly, the circuit using VCO requires a clock and will be affected by the process.
[0009] The third method: monitor the change of threshold voltage through hysteresis comparator:
[0010] 1. External positive feedback: This method often requires a large resistance in the CMOS process, resulting in a waste of layout area. At the same time, since the resistor is connected to the output end, current will flow through the resistor at the output end of the op amp, which will reduce the comparator's driving ability and cause power consumption waste. In addition, since the resistor is greatly affected by the process and temperature, the hysteresis range will change with the process and temperature, resulting in poor performance, inaccuracy, and inability to be applied in practice.
[0011] 2. Internal positive feedback: This circuit has a simple structure, and its hysteresis range is determined by the internal MOS tube size and the MOS tube's conduction threshold voltage. Since the threshold voltage is only affected by the process and temperature, the hysteresis range of the hysteresis comparator will also change after the final tape-out. This change is smaller than the first method, but it will also affect the use.
[0012] 3. Schmitt comparator: Similar to the second method, it is a type of hysteresis comparator designed with MOS tubes. The difference is that the Schmitt trigger is a circuit designed with a MOS tube, and the hysteresis range is fixed and cannot be changed. The range is the power supply voltage minus the threshold voltage of NMOS, minus the threshold voltage of PMOS. From this, it can be seen that if the monitoring circuit requires a different hysteresis range, we need to replace the entire circuit or change the process. As a test IP, this method is too cumbersome and difficult.
[0013] In summary, monitoring the NBTI effect of analog circuits faces the problem of using many digital circuits to interfere with the analog circuits, and the problem of changes in power supply voltage, process and temperature causing errors in the oscillator and hysteresis comparator used in monitoring the NBTI effect. These problems are huge challenges for NBTI effect monitoring. Summary of the invention
[0014] In order to solve the above problems existing in the prior art, the present invention provides a high-precision analog circuit, chip and IP for monitoring NBTI effects.
[0015] The technical problem to be solved by the present invention is achieved through the following technical solutions:
[0016] In a first aspect, the present invention provides a high-precision analog circuit for monitoring NBTI effects, the analog circuit comprising: an NBTI effect monitoring unit, a bandgap reference circuit, and a novel hysteresis comparator;
[0017] The NBTI effect monitoring unit is used to convert the NBTI effect from the stress Vstress into a voltage signal Vin and a voltage signal Vref, and transmit the voltage signal Vin and the voltage signal Vref to the novel hysteresis comparator;
[0018] The bandgap reference circuit is used to output a reference current Iref and a reference voltage VREF to the novel hysteresis comparator;
[0019] The novel hysteresis comparator is used to obtain the output current Iout according to the reference current Iref and the reference voltage VREF; and is also used to output the warning signal Vout according to the voltage signal Vin, the voltage signal Vref and the output current Iout to monitor the NBTI effect.
[0020] Optionally, the NBTI effect monitoring unit includes: a first branch, a second branch, a single-pole double-throw switch T1, a single-pole double-throw switch T2, a single-pole double-throw switch T3, a single-pole double-throw switch T4, a single-pole double-throw switch T5 and an inverter INV; the first branch includes a transistor M1, a transistor M2 and a transistor M3; the second branch includes a transistor M4, a transistor M5, a transistor M6 and a transistor M7; the gate end of the transistor M1 is respectively connected to the port of the stress Vstress input and the low level GND through the single-pole double-throw switch T1, the source end of the transistor M1 is respectively connected to the first power supply voltage VDD and the source end of the transistor M2 through the single-pole double-throw switch T2, the drain end of the transistor M1 is respectively connected to the output end of the inverter INV and the low level GND through the single-pole double-throw switch T3, and the gate end of the transistor M2 is respectively connected to the output end of the inverter INV and the low level GND. The gate terminal and the drain terminal are both connected to the source terminal of the transistor M3, and the gate terminal and the drain terminal of the transistor M3 are both connected to the drain terminal of the transistor M7; the gate terminal of the transistor M4 is connected to the low level GND, the drain terminal of the transistor M4 is respectively connected to the first power supply voltage VDD and the low level GND through the single-pole double-throw switch T4, the source terminal of the transistor M4 is respectively connected to the first power supply voltage VDD and the source terminal of the transistor M4 through the single-pole double-throw switch T5, the gate terminal and the drain terminal of the transistor M5 are both connected to the source terminal of the transistor M6, the source terminal of the transistor M5 is connected to the source terminal of the transistor M4, the gate terminal and the drain terminal of the transistor M6 are both connected to the drain terminal of the transistor M7, the gate terminal of the transistor M7 is connected to the control signal CTOL, and the source terminal of the transistor M7 is connected to the first power supply voltage VDD.
[0021] Optionally, the control signal CTOL is used to control the on and off of the single-pole double-throw switch T1 , the single-pole double-throw switch T2 , the single-pole double-throw switch T3 , the single-pole double-throw switch T4 and the single-pole double-throw switch T5 .
[0022] Optionally, the novel hysteresis comparator comprises: a current reference source and a traditional hysteresis comparator;
[0023] The current reference source is used to obtain the output current Iout according to the reference voltage VREF and the reference current Iref, and transmit the output current Iout to the traditional hysteresis comparator;
[0024] The conventional hysteresis comparator is used for using the output current Iout as a bias voltage and outputting the early warning signal according to the voltage signal Vin and the voltage signal Vref to monitor the NBTI effect.
[0025] Optionally, the current reference source includes: a third branch, a fourth branch, a fifth branch, a sixth branch, a seventh branch, an eighth branch, a transistor M21, a transistor M27, a resistor R1, a resistor R2, an amplifier A1 and an amplifier A2; the third branch includes: a resistor R3 and a transistor M25; the fourth branch includes: a transistor M25; the fifth branch includes: a transistor M24; the sixth branch includes: a transistor M22, a transistor M24 and a transistor M28; the seventh branch includes: a transistor M20; the eighth branch includes: a transistor M8, a transistor M23 and a transistor M29; the first branch of the resistor R3 includes: a transistor M24, a transistor M25 and a transistor M28; the seventh branch includes: a transistor M20; the eighth branch includes: a transistor M8, a transistor M23 and a transistor M29; the The first end of the resistor R1 is connected to the first end of the resistor R2, the second end of the resistor R3 is connected to the drain end of the transistor M26, the second end of the resistor R3 is connected to the first end of the resistor R2, the second end of the resistor R3 is also connected to the positive input end of the amplifier A1, and the second end of the resistor R3 is also connected to the positive input end of the amplifier A2; the drain end of the transistor M25 is connected to the second end of the resistor R2, and the drain end of the transistor M25 is also connected to the gate end of the transistor M28; the first end of the resistor R1 is connected to the first end of the resistor R2, and the drain end of the transistor M24 is connected to the second end of the resistor R1. , the drain terminal of the transistor M24 is also connected to the gate terminal of the transistor M29; the source terminal of the transistor M28 is connected to the second power supply voltage VD, the drain terminal of the transistor M28 is connected to the source terminal of the transistor M22, the drain terminal of the transistor is also connected to the negative input terminal of the amplifier A1, the gate terminal of the transistor M22 is connected to the output terminal of the amplifier A1, the gate terminal and the drain terminal of the transistor M21 are both connected to the drain terminal of the transistor M22; the gate terminal of the transistor M20 is connected to the gate terminal of the transistor M21, the drain terminal of the transistor M20 is connected to the drain terminal of the transistor M23, ...2 is connected to the output terminal of the amplifier A1, the gate terminal of the transistor M22 is connected to the output terminal of the amplifier A1, the gate terminal of the transistor M22 is connected to the output terminal of the amplifier A1, the gate terminal of the The drain terminal and the gate terminal of the transistor M8 are both connected to the drain terminal of the transistor M20; the source terminal of the transistor M29 is connected to the second power supply voltage, the drain terminal of the transistor M29 is connected to the negative input terminal of the amplifier A2, the drain terminal of the transistor M29 is connected to the source terminal of the transistor M23, and the gate terminal of the transistor M23 is connected to the output terminal of the amplifier A2; the drain terminals of the transistor M8, the transistor M20, the transistor M21, the transistor M24, the transistor M25 and the transistor M26 are all connected to the low level GND; the drain terminal of the transistor M27 is connected to the reference current Iref.
[0026] In a second aspect, the present invention provides a chip, comprising the high-precision analog circuit for monitoring NBTI effects as described in any one of the first aspects.
[0027] In a third aspect, the present invention provides an IP, wherein the IP comprises the high-precision analog circuit for monitoring NBTI effects as described in any one of the first aspects.
[0028] The technical solution provided by the embodiments of the present invention may have the following beneficial effects:
[0029] The circuit structure of the present invention is relatively simple, and an analog circuit is used. The resistance value in the circuit is small, and there is no interference and area problem of a digital circuit, and it has the characteristics of small area and low cost. Under different processes, temperatures, and power supply voltages, the NBTI effect of the chip under test can be monitored very simply and accurately through the output warning signal, thus solving the problems of large chip area, high design complexity, and low precision in the prior art solutions.
[0030] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 It is a structural schematic diagram of a high-precision analog circuit for monitoring NBTI effects provided by an embodiment of the present invention;
[0032] Figure 2 is a structural schematic diagram of an NBTI effect monitoring unit provided by an embodiment of the present invention;
[0033] Figure 3 is a structural schematic diagram of a novel hysteresis comparator provided by an embodiment of the present invention;
[0034] Figure 4 It is a simulation result waveform diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0035] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.
[0036] Figure 1 is a schematic diagram of the structure of a high-precision analog circuit for monitoring NBTI effects provided by an embodiment of the present invention, such as Figure 1 As shown, the analog circuit includes: an NBTI effect monitoring unit, a bandgap reference circuit and a novel hysteresis comparator;
[0037] An NBTI effect monitoring unit, used for converting the NBTI effect from the stress Vstress into a voltage signal Vin and a voltage signal Vref, and transmitting the voltage signal Vin and the voltage signal Vref to the novel hysteresis comparator;
[0038] A bandgap reference circuit is used for outputting a reference current Iref and a reference voltage VREF to a novel hysteresis comparator;
[0039] The novel hysteresis comparator is used to obtain an output current Iout according to a reference current Iref and a reference voltage VREF; and is also used to output a warning signal Vout according to a voltage signal Vin, a voltage signal Vref and the output current Iout to monitor the NBTI effect.
[0040] Optionally, Figure 2 is a structural diagram of an NBTI effect monitoring unit provided by an embodiment of the present invention, such as Figure 2 As shown, the NBTI effect monitoring unit includes: a first branch, a second branch, a single-pole double-throw switch T1, a single-pole double-throw switch T2, a single-pole double-throw switch T3, a single-pole double-throw switch T4, a single-pole double-throw switch T5 and an inverter INV; the first branch includes a transistor M1, a transistor M2 and a transistor M3; the second branch includes a transistor M4, a transistor M5, a transistor M6 and a transistor M7; the gate end of the transistor M1 is respectively connected to the port of the stress Vstress input and the low level GND through the single-pole double-throw switch T1, the source end of the transistor M1 is respectively connected to the first power supply voltage VDD and the source end of the transistor M2 through the single-pole double-throw switch T2, and the drain end of the transistor M1 is respectively connected to the output end of the inverter INV and the low level GN through the single-pole double-throw switch T3. D, the gate terminal and the drain terminal of the transistor M2 are both connected to the source terminal of the transistor M3, and the gate terminal and the drain terminal of the transistor M3 are both connected to the drain terminal of the transistor M7; the gate terminal of the transistor M4 is connected to the low level GND, the drain terminal of the transistor M4 is respectively connected to the first power supply voltage VDD and the low level GND through the single-pole double-throw switch T4, the source terminal of the transistor M4 is respectively connected to the first power supply voltage VDD and the source terminal of the transistor M4 through the single-pole double-throw switch T5, the gate terminal and the drain terminal of the transistor M5 are both connected to the source terminal of the transistor M6, the source terminal of the transistor M5 is connected to the source terminal of the transistor M4, the gate terminal and the drain terminal of the transistor M6 are both connected to the drain terminal of the transistor M7, the gate terminal of the transistor M7 is connected to the control signal CTOL, and the source terminal of the transistor M7 is connected to the first power supply voltage VDD.
[0041] It can be understood that the NBTI effect monitoring unit is respectively connected to the bandgap reference circuit, the current reference source and the traditional hysteresis comparator, and is used to convert the first power supply voltage VDD and provide it to the current reference source and the bandgap reference circuit after the control signal CTOL is pulled high; and provide two voltage signals Vin and voltage signal Vref to the traditional hysteresis comparator as inputs through the first branch and the second branch.
[0042] Specifically, refer to Figure 2In the NBTI effect monitoring unit, two identical PMOS transistors (M1 and M4) are selected, and the transistors M1 and M4 are placed in two identical branches (the first branch and the second branch) respectively. The transistor M1 is subjected to the stress Vstress from the NBTI effect, and the stress Vstress is an external voltage signal determined according to the environment. The change of the threshold voltage of the PMOS is measured through the first branch. In the first branch, the change of the threshold voltage of the transistor M1 after the NBTI effect can be reflected in the change of the voltage signal Vin. In the second branch, the second branch where the transistor M4 is located has the same circuit structure as the first branch, but does not apply the stress Vstress, but is only used to measure and maintain the initial threshold voltage of the PMOS, and output the initial threshold voltage to the second input terminal of the new hysteresis comparator. The influence of the stress of the NBTI effect on the threshold voltage of the PMOS transistor can be directly observed (the circuit is used as an IP, and the size of M1 and M4 needs to be consistent with the transistors in the chip / circuit under test). Transistor M2 , transistor M3 , transistor M5 and transistor M6 are responsible for providing saturated drain current for M1 and M4 , and are four NMOS transistors of the same size and reasonable values.
[0043] It is worth mentioning that the power supply end of the bandgap reference circuit is connected to the second power supply voltage VD of the NBTI effect monitoring unit, and is controlled by the second power supply voltage VD to switch the working or shutdown mode; the bandgap reference circuit outputs a reference current Iref and a reference voltage VREF connected to the new hysteresis comparator to ensure the normal operation of the new hysteresis comparator.
[0044] Optionally, the control signal CTOL is used to control the on and off of the single-pole double-throw switch T1 , the single-pole double-throw switch T2 , the single-pole double-throw switch T3 , the single-pole double-throw switch T4 and the single-pole double-throw switch T5 .
[0045] It can be understood that the control signal CTOL is an external precise clock pulse signal, which controls the switching of the stress Vstress between the NBTI effect state and the detection state; it also controls the operation of the current reference source circuit; when the control signal CTOL is at a low level, the circuit is in the detection state, the transistor M7 is turned on, and the first power supply voltage VDD is converted into the second power supply voltage VD, which is then transmitted to the current reference source to start working. And all single-pole double-throw switches are connected to the "0" terminal, the gate and drain of the transistor M1 are short-circuited with GND, and a constant current is applied to its source end through the first branch to make it in a saturated state. At this time, the source voltage of the transistor M1 is detected as the voltage signal Vin. When the control signal CTOL is at a high level, the circuit is in the NBTI effect state, the transistor M7 is turned off, and the second power supply voltage VD of the current reference source has no voltage value, so that it does not work. And all switches are connected to the "1" terminal. In this state, the gate and source of the transistor M1 are subjected to the stress Vstress of the NBTI effect, so that the absolute value of the threshold voltage of the transistor M1 continues to increase. The increase in the threshold voltage of transistor M1 can be reflected in the circuit through the source voltage. In the first branch, the change in the source voltage of transistor M1 is equal to the change in the threshold voltage (which can reflect the magnitude of the NBTI effect, and the greater the change in the threshold voltage, the stronger the NBTI effect). However, the transistor M4 of the second branch is not affected by the stress Vstress, and its source-drain voltage is allowed to be used as a reference for the change in the threshold voltage of transistor M1, so that the voltage signal Vref always outputs the magnitude of the threshold voltage of transistor M4.
[0046] Optionally, Figure 3 is a schematic diagram of the structure of a novel hysteresis comparator provided by an embodiment of the present invention, such as Figure 3 As shown, the novel hysteresis comparator includes: a current reference source and a traditional hysteresis comparator;
[0047] A current reference source, used for obtaining an output current Iout according to a reference voltage VREF and a reference current Iref, and transmitting the output current Iout to a conventional hysteresis comparator;
[0048] The conventional hysteresis comparator is used to use the output current Iout as a bias voltage and output a warning signal according to the voltage signal Vin and the voltage signal Vref to monitor the NBTI effect.
[0049] It can be understood that the current reference source is connected to the bandgap reference circuit and the traditional hysteresis comparator, and the input end is connected to the bandgap reference circuit to convert the reference current Iref into the output current Iout, and the output current Iout is given to the traditional hysteresis comparator as its bias current, thereby compensating for the influence of power supply voltage, process and temperature on the traditional structure.
[0050] Optionally, the current reference source includes: a third branch, a fourth branch, a fifth branch, a sixth branch, a seventh branch, an eighth branch, a transistor M21, a transistor M27, a resistor R1, a resistor R2, an amplifier A1 and an amplifier A2; the third branch includes: a resistor R3 and a transistor M25; the fourth branch includes: a transistor M25; the fifth branch includes: a transistor M24; the sixth branch includes: a transistor M22, a transistor M24 and a transistor M28; the seventh branch includes: a transistor M20; the eighth branch includes: a transistor M8, a transistor M23 and transistor M29; the first end of the resistor R3 is connected to the second power supply voltage VD, the second end of the resistor R3 is connected to the drain end of the transistor M26, the second end of the resistor R3 is connected to the first end of the resistor R2, the second end of the resistor R3 is also connected to the positive input end of the amplifier A1, and the second end of the resistor R3 is also connected to the positive input end of the amplifier A2; the drain end of the transistor M25 is connected to the second end of the resistor R2, and the drain end of the transistor M25 is also connected to the gate end of the transistor M28; the first end of the resistor R1 is connected to the first end of the resistor R2, and the drain end of the transistor M24 is connected to the gate end of the transistor M28; The drain terminal of transistor M24 is also connected to the gate terminal of transistor M29; the source terminal of transistor M28 is connected to the second power supply voltage VD, the drain terminal of transistor M28 is connected to the source terminal of transistor M22, the drain terminal of the transistor is also connected to the negative input terminal of amplifier A1, the gate terminal of transistor M22 is connected to the output terminal of amplifier A1, the gate terminal and drain terminal of transistor M21 are both connected to the drain terminal of transistor M22; the gate terminal of transistor M20 is connected to the gate terminal of transistor M21, the drain terminal of transistor M20 is connected to the gate terminal of transistor M23 The drain terminal of transistor M8 and the gate terminal of transistor M26 are connected to the drain terminal of transistor M20; the source terminal of transistor M29 is connected to the second power supply voltage, the drain terminal of transistor M29 is connected to the negative input terminal of amplifier A2, the drain terminal of transistor M29 is connected to the source terminal of transistor M23, and the gate terminal of transistor M23 is connected to the output terminal of amplifier A2; the drain terminals of transistor M8, transistor M20, transistor M21, transistor M24, transistor M25 and transistor M26 are all connected to the low level GND; the drain terminal of transistor M27 is connected to the reference current Iref.
[0051] Understandably, reference Figure 3, the left half is the current reference source. The circuit first mirrors the reference current Iref to the inside of the circuit through the current mirror composed of transistors M24, M25, M26, and M27, and then clamps the drain voltage of transistors M28 and M29 through the combined action of amplifiers A1, A2, and resistor R3. The mirrored current then passes through resistors R2 and R3 to generate the gate voltage of transistors M28 and M29. Finally, the current Iout obtained by subtracting the drain current I5 of transistor M23 from the drain current I6 of transistor M20 is mirrored to the traditional hysteresis comparator as its bias current to ensure its high-precision operation. In the circuit design, the circuit makes both transistors M28 and M29 work in the deep linear region, and the current I5 flowing through transistor M29 is greater than the mirrored current I6 flowing through transistor M28 by setting resistors R3, R1, and R2. The currents of transistors M28 and M29 working in the deep linear region are shown in the following formula:
[0052]
[0053] Among them, V GSM28 and V GSM29 are the gate-source voltages of transistor M28 and transistor M29 respectively. The drain-source voltages of transistor M28 and transistor M29 are equal to V DS , and the threshold voltage is V TH ;μ p is the mobility of the PMOS tube, C ox is the gate oxide capacitance, is the width-to-length ratio of transistor M28, V GSM28 is the voltage difference between the gate and source of transistor M28, V TH is the threshold voltage of the MOS tube, V DS It is the voltage difference between the drain and source of the MOS tube.
[0054] By designing the transistor M28 and the transistor M29 to be equal in size The output current Iout can be obtained as shown in the following formula:
[0055]
[0056] Wherein, K is the proportional coefficient of the current mirror, and the two amplifiers A1 and A2 adopt the existing Miller compensation two-stage operational amplifier structure.
[0057] In addition, conventional hysteresis comparators such as Figure 3The right half shows that the existing traditional hysteresis comparator structure is adopted. It only needs to ensure that the size (ratio of width to length) of transistor M18 and transistor M19 is equal, the size of transistor M16 and transistor M17 is equal, and the size of transistor M18 is larger than that of transistor M16. The size of transistor M18 is N times that of transistor M16, that is, (W / L) 18 :(W / L) 16 =N:1, the gate of the second input terminal transistor M15 of the conventional hysteresis comparator is connected to the voltage signal Vref, and the gate of the first input terminal transistor M14 is connected to the voltage signal Vin.
[0058] Figure 4 is a simulation result waveform diagram provided by an embodiment of the present invention, such as Figure 4 As shown, as the voltage of the voltage signal Vin gradually increases, when the voltage signal Vin is greater than the voltage signal Vref by more than 60mV (it can be designed and changed by yourself, and the present invention is tentatively set to 60mV), the transistors M7, M5, M3, and M4 are turned on, and the transistors M8 and M6 are turned off, and the warning signal Vout outputs a low level, which proves that the NBTI effect has caused damage to the circuit and the warning is successful.
[0059] Specifically, the bias current of a general conventional hysteresis comparator is the current IM2 flowing through the transistor M9. At this time, the hysteresis voltage of the circuit can be calculated:
[0060]
[0061] Among them, the mobility μ p and gate oxide capacitance C ox is a process-related parameter, V TRP+ is the forward hysteresis voltage of the hysteresis comparator, which makes the hysteresis voltage process-dependent. Secondly, the main scattering mechanisms in silicon semiconductors are acoustic wave scattering and ionized impurity scattering, which can be used to obtain the mobility μ p It will change with temperature. In addition, the comparator bias current has a temperature coefficient, which causes the hysteresis voltage of the hysteresis comparator to be related to temperature. The purpose of this part is to use the output current Iout of the new reference source as the bias current of the traditional hysteresis comparator to compensate for the influence of temperature and process on the hysteresis voltage.
[0062] At this time, let the bias current be the output current Iout, and we get:
[0063]
[0064] Among them, the temperature and process-related mobility μ p and gate oxide capacitance C oxIt is no longer in the formula, which means that these two parameters have no effect on the hysteresis voltage. The remaining part of the formula is mainly the width-to-length ratio of each MOS transistor, which is not affected by temperature and process.
[0065] When the whole circuit is placed as an IP in the monitored circuit, the NBTI effect monitoring unit starts to work, monitoring the stress changes of the NBTI effect, and passing the voltage signal Vin and the voltage signal Vref to the two input terminals of the new hysteresis comparator. The bandgap reference circuit provides its reference current Iref and reference voltage VREF. Regardless of how the temperature or process equipment changes, a hysteresis voltage V that is consistent with the power supply voltage, temperature and process is finally obtained. TRP+ , the NBTI effect can be monitored very accurately.
[0066] The circuit structure of the present invention is relatively simple, and an analog circuit is used. The resistance value in the circuit is small, and there is no interference and area problem of a digital circuit, and it has the characteristics of small area and low cost. Under different processes, temperatures, and power supply voltages, the NBTI effect of the chip under test can be monitored very simply and accurately through the output warning signal, thus solving the problems of large chip area, high design complexity, and low precision in the prior art solutions.
[0067] The present invention also provides a chip, which includes any one of the above-mentioned high-precision analog circuits for monitoring NBTI effects.
[0068] The present invention also provides an IP, which includes the content of any one of the above-mentioned high-precision analog circuits for monitoring NBTI effects.
[0069] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.
[0070] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.
Claims
1. A high-precision analog circuit for monitoring NBTI effects, characterized in that: The analog circuit includes: an NBTI effect monitoring unit, a bandgap reference circuit and a novel hysteresis comparator; The NBTI effect monitoring unit is used to convert the NBTI effect from the stress Vstress into a voltage signal Vin and a voltage signal Vref, and transmit the voltage signal Vin and the voltage signal Vref to the novel hysteresis comparator; The bandgap reference circuit is used to output a reference current Iref and a reference voltage VREF to the novel hysteresis comparator; The novel hysteresis comparator is used to obtain the output current Iout according to the reference current Iref and the reference voltage VREF; and is also used to output the warning signal Vout according to the voltage signal Vin, the voltage signal Vref and the output current Iout to monitor the NBTI effect.
2. The NBTI effect monitoring unit according to claim 1, characterized in that: The NBTI effect monitoring unit includes: a first branch, a second branch, a single-pole double-throw switch T1, a single-pole double-throw switch T2, a single-pole double-throw switch T3, a single-pole double-throw switch T4, a single-pole double-throw switch T5 and an inverter INV; the first branch includes a transistor M1, a transistor M2 and a transistor M3; the second branch includes a transistor M4, a transistor M5, a transistor M6 and a transistor M7; the gate end of the transistor M1 is respectively connected to the port of the stress Vstress input and the low level GND through the single-pole double-throw switch T1, the source end of the transistor M1 is respectively connected to the first power supply voltage VDD and the source end of the transistor M2 through the single-pole double-throw switch T2, the drain end of the transistor M1 is respectively connected to the output end of the inverter INV and the low level GND through the single-pole double-throw switch T3, and the gate end of the transistor M2 is respectively connected to the output end of the inverter INV and the low level GND. and drain terminals are connected to the source terminal of the transistor M3, and the gate terminal and drain terminal of the transistor M3 are connected to the drain terminal of the transistor M7; the gate terminal of the transistor M4 is connected to the low level GND, the drain terminal of the transistor M4 is respectively connected to the first power supply voltage VDD and the low level GND through the single-pole double-throw switch T4, the source terminal of the transistor M4 is respectively connected to the first power supply voltage VDD and the source terminal of the transistor M4 through the single-pole double-throw switch T5, the gate terminal and drain terminal of the transistor M5 are both connected to the source terminal of the transistor M6, the source terminal of the transistor M5 is connected to the source terminal of the transistor M4, the gate terminal and drain terminal of the transistor M6 are both connected to the drain terminal of the transistor M7, the gate terminal of the transistor M7 is connected to the control signal CTOL, and the source terminal of the transistor M7 is connected to the first power supply voltage VDD.
3. The NBTI effect monitoring unit according to claim 2, characterized in that: The control signal CTOL is used to control the on and off of the single-pole double-throw switch T1 , the single-pole double-throw switch T2 , the single-pole double-throw switch T3 , the single-pole double-throw switch T4 , and the single-pole double-throw switch T5 .
4. The NBTI effect monitoring unit according to claim 1, characterized in that: The novel hysteresis comparator comprises: a current reference source and a traditional hysteresis comparator; The current reference source is used to obtain the output current Iout according to the reference voltage VREF and the reference current Iref, and transmit the output current Iout to the traditional hysteresis comparator; The conventional hysteresis comparator is used for using the output current Iout as a bias voltage and outputting the early warning signal according to the voltage signal Vin and the voltage signal Vref to monitor the NBTI effect.
5. The NBTI effect monitoring unit according to claim 4, characterized in that: The current reference source includes: a third branch, a fourth branch, a fifth branch, a sixth branch, a seventh branch, an eighth branch, a transistor M21, a transistor M27, a resistor R1, a resistor R2, an amplifier A1 and an amplifier A2; the third branch includes: a resistor R3 and a transistor M25; the fourth branch includes: a transistor M25; the fifth branch includes: a transistor M24; the sixth branch includes: a transistor M22, a transistor M24 and a transistor M28; the seventh branch includes: a transistor M20; the eighth branch includes: a transistor M8, a transistor M23 and a transistor M29; the first end of the resistor R3 is connected to the The second power supply voltage VD is connected to the second end of the resistor R3, the second end of the resistor R3 is connected to the drain end of the transistor M26, the second end of the resistor R3 is connected to the first end of the resistor R2, the second end of the resistor R3 is also connected to the positive input end of the amplifier A1, and the second end of the resistor R3 is also connected to the positive input end of the amplifier A2; the drain end of the transistor M25 is connected to the second end of the resistor R2, and the drain end of the transistor M25 is also connected to the gate end of the transistor M28; the first end of the resistor R1 is connected to the first end of the resistor R2, the drain end of the transistor M24 is connected to the second end of the resistor R1, and the The drain terminal of the transistor M24 is also connected to the gate terminal of the transistor M29; the source terminal of the transistor M28 is connected to the second power supply voltage VD, the drain terminal of the transistor M28 is connected to the source terminal of the transistor M22, the drain terminal of the transistor is also connected to the negative input terminal of the amplifier A1, the gate terminal of the transistor M22 is connected to the output terminal of the amplifier A1, the gate terminal and the drain terminal of the transistor M21 are both connected to the drain terminal of the transistor M22; the gate terminal of the transistor M20 is connected to the gate terminal of the transistor M21, the drain terminal of the transistor M20 is connected to the drain terminal of the transistor M23, and the gate terminal of the transistor M20 is connected to the gate terminal of the transistor M21. The drain and gate of M8 are both connected to the drain of the transistor M20; the source of the transistor M29 is connected to the second power supply voltage, the drain of the transistor M29 is connected to the negative input of the amplifier A2, the drain of the transistor M29 is connected to the source of the transistor M23, and the gate of the transistor M23 is connected to the output of the amplifier A2; the drains of the transistor M8, the transistor M20, the transistor M21, the transistor M24, the transistor M25 and the transistor M26 are all connected to the low level GND; the drain of the transistor M27 is connected to the reference current Iref.
6. A chip, characterized in that: The chip comprises the high-precision analog circuit for monitoring NBTI effects as claimed in any one of claims 1 to 5.
7. An IP, characterized in that: The IP includes the high-precision analog circuit for monitoring NBTI effects as claimed in any one of claims 1 to 5.