Ethernet phy chip testing device and method

Abstract

The application belongs to the field of integrated circuit testing, and specifically discloses an Ethernet PHY chip testing device, which comprises an automatic testing module, a standard PHY chip and a controller. The automatic testing module is connected with a to-be-tested PHY chip or the standard PHY chip, and is used for generating a driving signal and performing signal comparison analysis. The standard PHY chip is used for being connected with the to-be-tested PHY chip and performing signal interaction, generating a testing signal and returning the testing signal to the automatic testing module. The controller is connected with the to-be-tested PHY chip and the standard PHY chip and establishes communication, is used for controlling the transmission path of the driving signal between the to-be-tested PHY chip and the standard PHY chip, and switches a communication protocol to realize multi-communication protocol testing. Through the application, the chip testing efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit testing, and more specifically, to an Ethernet PHY chip testing device and method. Background Art

[0002] Ethernet PHY chips are highly integrated, fast, and have numerous communication protocols. To fully test them, traditional integrated circuit testing methods are no longer applicable. Using production-level testing is costly and inefficient.

[0003] Therefore, how to improve the testing efficiency of the Ethernet PHY chip and solve the testing defects of the Ethernet PHY chip in a relatively efficient manner is a technical problem existing in the prior art. Summary of the Invention

[0004] In view of the defects of the prior art, the purpose of this application is to provide an Ethernet PHY chip testing device and method, aiming to solve the problems of Ethernet PHY chip testing difficulty and low testing efficiency in the prior art.

[0005] To achieve the above objectives, in a first aspect, the present application provides an Ethernet PHY chip testing device, comprising: a controller, an automatic testing module, and a standard PHY chip;

[0006] An automatic test module, connected to the PHY chip to be tested or to the standard PHY chip, for generating a drive signal and performing signal comparison analysis;

[0007] A standard PHY chip, configured to connect to and perform signal interaction with the PHY chip to be tested, generate a test signal, and return the test signal to the automatic test module;

[0008] The controller is connected to the PHY chip to be tested and the standard PHY chip and establishes communication with them, and is used to control the transmission path of the driving signal between the PHY chip to be tested and the standard PHY chip, and switch the communication protocol to implement multi-communication protocol testing.

[0009] Optionally, a signal switching module is further included, the signal switching module includes a communication interface, and the signal switching module is connected to the automatic test module, the PHY chip to be tested, and the standard PHY chip through the communication interface;

[0010] The signal switching module is used to switch signal paths during the test process to implement tests of different communication protocols.

[0011] Optionally, the automatic test module controls the signal switching module to connect to different modules, and the signal switching module switches the communication interface so that the automatic test module connects to the controller or connects to the PHY chip to be tested;

[0012] When the automatic test module is connected to the controller, the first communication protocol test mode or the second communication protocol test mode is executed;

[0013] When the automatic test module is connected to the PHY chip to be tested, a parameter test mode is executed.

[0014] Optionally, the automatic test module is connected to the controller, an output end of the controller is connected to the PHY chip to be tested, and an output end of the PHY chip to be tested is connected to the standard PHY chip;

[0015] The process of executing the first communication protocol test mode includes:

[0016] The controller processes the driving signal generated by the automatic test module and sends it to the PHY chip to be tested;

[0017] The PHY chip to be tested forwards the driving signal to the standard PHY chip;

[0018] The controller receives the test signal returned by the standard PHY chip and transmits the test signal to the automatic test module for comparison;

[0019] Change the communication protocol and repeat the above process until all communication protocols are traversed.

[0020] Optionally, the output end of the controller is connected to the standard PHY chip, and the output end of the standard PHY chip is connected to the PHY chip to be tested;

[0021] The process of executing the second communication protocol test mode includes:

[0022] The controller processes the driving signal generated by the automatic test module and sends it to the standard PHY chip;

[0023] The standard PHY chip forwards the driving signal to the PHY chip to be tested;

[0024] The controller receives a test signal returned by the PHY chip to be tested, and transmits the test signal to the automatic test module for comparison;

[0025] Change the communication protocol and repeat the above process until all communication protocols are traversed.

[0026] Optionally, the automatic test module is directly connected to the PHY chip to be tested to execute a parameter test mode;

[0027] The process of executing the parameter test mode includes:

[0028] The automatic test module sends a driving signal to the PHY chip to be tested;

[0029] The automatic test module receives a test signal returned by the PHY chip to be tested, compares the test signal with the driving signal, performs parameter testing, and generates a test result.

[0030] Optionally, the controller is a high-speed controller of a media access control (MAC) corresponding to the PHY to be tested and the standard PHY, and the controller includes a CPU and an FPGA.

[0031] In a second aspect, the present application provides an Ethernet PHY chip testing method, comprising:

[0032] Generating a driving signal;

[0033] Generating a test signal through the PHY chip to be tested and the standard PHY chip according to the driving signal, and performing signal comparison analysis according to the test signal;

[0034] Controlling the transmission path of the driving signal between the PHY chip to be tested and the standard PHY chip, and switching the communication protocol to realize multi-communication protocol testing.

[0035] Optionally, the process of the multi-communication protocol testing comprises:

[0036] The controller sends the driving signal generated by the automatic test module to the PHY chip to be tested after processing, returns the PHY chip to be tested to the standard PHY chip, and returns the standard PHY chip to the controller through the automatic test module, compares the driving signal with the test signal, replaces the communication protocol, and repeats the above signal processing process until all communication protocols are traversed.

[0037] The controller sends the driving signal generated by the automatic test module to the standard PHY chip after processing, returns the standard PHY chip to the PHY chip to be tested, and returns the PHY chip to be tested to the controller through the automatic test module, compares the driving signal with the test signal, replaces the communication protocol, and repeats the above signal processing process until all communication protocols are traversed.

[0038] The PHY chip to be tested returns the driving signal sent by the automatic test module to the automatic test module, compares the driving signal with the test signal, performs related parameter testing, replaces the communication protocol, and repeats the above signal processing process until all communication protocols are traversed.

[0039] In a third aspect, the present application provides an electronic device, comprising at least one memory for storing a program, and at least one processor for executing the program stored in the memory, wherein when the program stored in the memory is executed, the processor is configured to execute the method described in the first aspect or any possible implementation manner of the first aspect.

[0040] In a fourth aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method described in the first aspect or any possible implementation of the first aspect.

[0041] In a fifth aspect, the present application provides a computer program product, which, when executed on a processor, enables the processor to execute the method described in the first aspect or any possible implementation of the first aspect.

[0042] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0043] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the existing technologies:

[0044] (1) This application establishes communication with the Ethernet PHY chip through the controller, avoiding the tedious work of repeated configuration of multiple communication protocols of the automatic test system, reducing labor time costs, and improving development efficiency; through the connection between the controller and the PHY chip, the low-frequency test system is used to test the high-frequency chip, avoiding direct testing of high-speed signals and reducing the difficulty of test board design; through the signal switching module, the Ethernet PHY chip is used to test multiple communication protocols and related parameters, thereby improving test efficiency.

[0045] (2) The embodiments of the present application utilize standard PHY chips and PHY chips to be tested to perform different tests, and can comprehensively detect the complete functions of the PHY chip under different communication conditions from different signal starting transmission directions and interface application angles, ensuring that no matter whether the PHY chip to be tested receives the signal first or later, its function can be fully verified, effectively avoiding missing potential problems due to a single test angle, and improving the comprehensiveness and accuracy of the test.

[0046] (3) This application achieves a high degree of automation in the test process by integrating a controller with an automatic test module. The automatic test module can not only generate accurate drive signals, but also has the ability to perform signal comparison and analysis, significantly reducing the need for manual intervention, making the test process more efficient, avoiding errors that may be introduced by human operation, and improving the repeatability and reliability of the test.

[0047] (4) The PHY chip to be tested in this application can interact with standard PHY chips and automatic test modules under multiple communication protocols, so that the performance under different protocols can be evaluated through a unified test platform, reducing the complexity and cost of the test equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 is a structural schematic diagram of an Ethernet PHY chip test device provided by an embodiment of the present application.

[0049] Figure 2 is a flowchart of an Ethernet PHY chip test method provided by an embodiment of the present application.

[0050] Figure 3 is a flowchart of an Ethernet PHY chip test method provided by an embodiment of the present application.

[0051] Figure 4 is a flowchart of an Ethernet PHY chip test method provided by an embodiment of the present application.

[0052] Figure 5 is a flowchart of an Ethernet PHY chip test method provided by an embodiment of the present application.

[0053] Figure 6 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0054] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0055] The term "and / or" used herein is used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that there are three cases of A alone, A and B together, and B alone. The symbol " / " in this paper represents the relationship of or, for example, A / B represents A or B.

[0056] The terms "first" and "second" and the like in the specification and claims herein are used to distinguish different objects, and are not used to describe the specific order of the objects. For example, the first response message and the second response message are used to distinguish different response messages, and are not used to describe the specific order of the response messages.

[0057] In the embodiments of the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or having more advantages than other embodiments or design schemes. Rather, the words "exemplary" or "for example" are used in the specific manner to present the relevant concept.

[0058] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more, for example, multiple processing units means two or more processing units, etc.; multiple elements means two or more elements, etc.

[0059] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0060] Reference Figure 1 The present application provides an Ethernet PHY chip test device, comprising: a controller 110, an automatic test module 120, and a standard PHY chip 130. For ease of illustration, the figure shows the entire chip test device connected to a PHY chip to be tested 140. The connection relationship and functions of each module are as follows:

[0061] An automatic test module 120 is connected to the PHY chip to be tested or to the standard PHY chip, and is used to generate a driving signal and perform signal comparison analysis;

[0062] The standard PHY chip 130 is configured to connect to and perform signal interaction with the PHY chip to be tested 140 , generate a test signal, and return the test signal to the automatic test module;

[0063] The controller, namely the high-speed core controller 110, is connected to the PHY chip under test and the standard PHY chip and establishes communication, and is used to control the transmission path of the driving signal between the PHY chip under test and the standard PHY chip, and switch the communication protocol to implement multi-communication protocol testing.

[0064] Optionally, a signal switching module 150 is further included, the signal switching module includes a communication interface, and the signal switching module is connected to the automatic test module, the PHY chip to be tested, and the standard PHY chip through the communication interface;

[0065] The signal switching module is used to switch signal paths during the test process to implement tests of different communication protocols.

[0066] Specifically, the functions of each module in the embodiment of the present application are as follows:

[0067] Processing the driving signal generated by the automatic test module through the controller;

[0068] Control signal transmission path between the PHY chip under test and the standard PHY chip;

[0069] Switch communication protocols to implement multi-communication protocol testing.

[0070] It should be noted that the hardware implementation of the controller includes but is not limited to a CPU (central processing unit) and an FPGA (field programmable gate array), which are used for efficient signal processing and protocol switching.

[0071] Generate drive signals through the automatic test module; receive return signals and compare and analyze them with the original drive signals; perform parameter tests and generate test results.

[0072] It should be noted that the automatic test module can control the signal switching module to switch the communication interface to connect to the controller or the PHY chip to be tested.

[0073] Receive driving signals and return test signals through the PHY chip under test; interact with standard PHY chips or automatic test modules under different communication protocols.

[0074] Generate a standard reference signal by performing signal interaction between the standard PHY chip and the PHY chip under test, providing a benchmark for signal comparison.

[0075] The communication interface of the signal switching module is used to connect with the automatic test module, the PHY chip to be tested, and the standard PHY chip; the signal path is switched during the test process to implement the test of different communication protocols.

[0076] The signal switching module can be controlled by an automatic test module or a controller.

[0077] Optionally, the automatic test module controls a signal switching module, and the signal switching module switches a communication interface so that the automatic test module is connected to the controller or the PHY chip to be tested;

[0078] When the automatic test module is connected to the controller, the first communication protocol test mode or the second communication protocol test mode is executed;

[0079] When the automatic test module is connected to the PHY chip to be tested, a parameter test mode is executed.

[0080] Optionally, the automatic test module is connected to the controller, an output end of the controller is connected to the PHY chip to be tested, and an output end of the PHY chip to be tested is connected to the standard PHY chip;

[0081] The process of executing the first communication protocol test mode includes:

[0082] The controller processes the driving signal generated by the automatic test module and sends it to the PHY chip to be tested;

[0083] The PHY chip to be tested forwards the driving signal to the standard PHY chip;

[0084] The controller receives the test signal returned by the standard PHY chip and transmits the test signal to the automatic test module for comparison;

[0085] Change the communication protocol and repeat the above process until all communication protocols are traversed.

[0086] Specifically, the execution process of the first communication protocol test mode is as follows:

[0087] Connection method between modules:

[0088] The automatic test module is connected to the controller; the output end of the controller is connected to the PHY chip to be tested; and the output end of the PHY chip to be tested is connected to the standard PHY chip.

[0089] The testing process is:

[0090] The automatic test module generates a driving signal and sends it to the controller;

[0091] The controller processes the driving signal and sends it to the PHY chip under test;

[0092] The PHY chip under test forwards the signal to the standard PHY chip;

[0093] The standard PHY chip returns the signal to the controller;

[0094] The controller transmits the return signal to the automatic test module for comparison;

[0095] Change the communication protocol and repeat the above process until all communication protocols are traversed.

[0096] It should be noted that the communication protocols in this embodiment and the following embodiments include but are not limited to: rgmii, sgmii, fiber, utp, etc.

[0097] Optionally, the output end of the controller is connected to the standard PHY chip, and the output end of the standard PHY chip is connected to the PHY chip to be tested;

[0098] The process of executing the second communication protocol test mode includes:

[0099] The controller processes the driving signal generated by the automatic test module and sends it to the standard PHY chip;

[0100] The standard PHY chip forwards the driving signal to the PHY chip to be tested;

[0101] The controller receives a test signal returned by the PHY chip to be tested, and transmits the test signal to the automatic test module for comparison;

[0102] Change the communication protocol and repeat the above process until all communication protocols are traversed.

[0103] Accordingly, the execution process of the second communication protocol test mode is as follows:

[0104] Connection method between modules:

[0105] The automatic test module is connected to the controller; the output end of the controller is connected to the standard PHY chip; and the output end of the standard PHY chip is connected to the PHY chip to be tested.

[0106] The testing process is:

[0107] The automatic test module generates a driving signal and sends it to the controller;

[0108] The controller processes the driving signal and sends it to the standard PHY chip;

[0109] The standard PHY chip forwards the signal to the PHY chip under test;

[0110] The PHY chip under test returns a signal to the controller;

[0111] The controller transmits the return signal to the automatic test module for comparison;

[0112] Change the communication protocol and repeat the above process until all communication protocols are traversed.

[0113] Optionally, the automatic test module is directly connected to the PHY chip to be tested to execute a parameter test mode;

[0114] The process of executing the parameter test mode includes:

[0115] The automatic test module sends a driving signal to the PHY chip to be tested;

[0116] The automatic test module receives a test signal returned by the PHY chip to be tested, compares the test signal with a driving signal, performs parameter testing and generates a test result.

[0117] Specifically, in the parameter test mode of this embodiment, the automatic test module is directly connected to the PHY chip to be tested.

[0118] Testing process:

[0119] The automatic test module sends a driving signal to the PHY chip under test;

[0120] The PHY chip to be tested returns a test signal to the automatic test module;

[0121] The automatic test module compares the test signal with the original drive signal;

[0122] Perform parametric tests and generate test results;

[0123] Change the communication protocol and repeat the above process until all communication protocols are traversed.

[0124] Optionally, the controller is a high-speed controller corresponding to the media access control (MAC) of the PHY under test and the standard PHY, including but not limited to a CPU and an FPGA. The signal switching module is used to control the high-speed signal connection of the PHY chip under test, and can be, but is not limited to, a high-speed differential digital signal multiplexer.

[0125] Reference Figure 2 , the present application also provides an Ethernet PHY chip testing method, comprising:

[0126] S201. Generate a driving signal;

[0127] S202. The driving signal is passed through the PHY chip to be tested and the standard PHY chip to generate a test signal, and a signal comparison analysis is performed based on the test signal;

[0128] S203. Control the transmission path of the driving signal between the PHY chip to be tested and the standard PHY chip, and switch the communication protocol to implement multi-communication protocol testing.

[0129] Optionally, the process of the multi-communication protocol test includes:

[0130] S1. The high-speed core controller processes the drive signal generated by the automatic test module and sends it to the PHY chip under test. The PHY chip under test sends it to the standard PHY chip and returns to the high-speed core controller. The automatic test module compares it with the drive signal, and the communication protocol is changed. Repeat the above signal processing process until all communication protocols are traversed;

[0131] S2. The high-speed core controller processes the drive signal generated by the automatic test module and sends it to the standard PHY chip. The standard PHY chip sends it to the PHY chip under test and returns it to the high-speed core controller. The automatic test module compares it with the drive signal, and the communication protocol is changed. Repeat the above signal processing process until all communication protocols are traversed;

[0132] S3. The PHY chip under test returns the driving signal sent by the automatic test module to the automatic test module for comparison with the driving signal and performs relevant parameter tests. The above signal processing process is repeated after changing the communication protocol until all communication protocols are traversed.

[0133] It should be noted that in the above scheme, in the step S1, before the high-speed core controller sends data to the PHY chip to be tested, the automatic test system needs to place the signal switching module in the corresponding working state, and the high-speed core controller needs to configure the PHY chip to be tested and the standard PHY chip to the corresponding working state first; in the step S2, before the high-speed core controller sends data to the standard PHY chip, the high-speed core controller needs to configure the PHY chip to be tested and the standard PHY chip to the corresponding working state first; in the step S3, before the automatic test system sends data to the PHY chip to be tested, the automatic test system needs to place the signal switching module in the corresponding working state, and the automatic test system needs to configure the PHY chip to be tested to the corresponding working state first.

[0134] Specifically, the specific process of S1 is as shown in the following table: Figure 3

[0135] S11. The automatic test system controls the signal switching module to connect the PHY chip to be tested to the high-speed core controller and the standard PHY chip, and then sends a signal to the high-speed core controller to indicate that the connection of the PHY chip to be tested is established.

[0136] S12. After receiving the connection establishment signal sent by the automatic test system, the high-speed core controller configures the PHY chip to be tested and the standard PHY chip to the corresponding working state.

[0137] S13. The automatic test system sends data to the high-speed core controller.

[0138] S14. The high-speed core controller processes the data received from the automatic test system and packages it into a corresponding format to send to the PHY chip to be tested, and the PHY chip to be tested returns the data to the high-speed core controller through the standard PHY chip.

[0139] S15. The high-speed core controller sends the data back to the automatic test system, and the automatic test system compares the received data with the original data sent.

[0140] S16. Replace the communication protocol and repeat the above steps until all communication protocols are traversed.

[0141] Further, the specific process of S2 is as shown in the following table: Figure 4

[0142] S21. The automatic test system controls the signal switching module to connect the PHY chip to be tested to the high-speed core controller and the standard PHY chip, and then sends a signal to the high-speed core controller to indicate that the connection of the PHY chip to be tested is established.

[0143] ​​S22. After the high-speed core controller receives the connection establishment signal sent by the automatic test system, the configuration of the PHY chip to be tested and the standard PHY chip to the corresponding working state;

[0144] S23 automatic test system sends data to the high-speed core controller;

[0145] S24. The high-speed core controller processes the data received from the automatic test system and packages it into the appropriate format and sends it to the standard PHY chip. The standard PHY chip returns the data to the high-speed core controller through the PHY chip to be tested.

[0146] S25. The high-speed core controller sends the data back to the automatic test system, which compares the received data with the original data sent.

[0147] S26. Change the communication protocol and repeat the above steps until all communication protocols are traversed;

[0148] Furthermore, the specific process of the above S3 is as follows Figure 5 As shown:

[0149] S31. The automatic test system control signal switching module, the PHY chip to be tested access automatic test system;

[0150] S32. The automatic test system configures the PHY chip to be tested to the corresponding working state;

[0151] S33. The automatic test system sends data to the PHY chip to be tested, and after receiving the data, the PHY chip to be tested returns the data to the automatic test system, and the automatic test system performs relevant parameter tests;

[0152] S34. Change the communication protocol and repeat the above steps until all communication protocols are traversed.

[0153] The Ethernet PHY chip testing method of the present application has the following beneficial effects: establishing communication with the Ethernet PHY chip through a high-speed core controller avoids the tedious work of repeatedly configuring multiple communication protocols of the automatic test system, reduces labor time costs, and improves development efficiency; through the connection between the high-speed core controller and the PHY chip, a low-frequency test system is used to test the high-frequency chip, avoiding direct testing of high-speed signals and reducing the difficulty of test board design; through the signal switching module, one-click testing of multiple communication protocols and related parameters of the Ethernet PHY chip is achieved, thereby improving test efficiency.

[0154] Reference Figure 6Based on the method in the above embodiment, an embodiment of the present application provides an electronic device, which may include: a processor (Processor) 610, a communication interface (Communications Interface) 620, a memory (Memory) 630 and a communication bus 640, wherein the processor 610, the communication interface 620, and the memory 630 communicate with each other via the communication bus 640. The processor 610 can call the logic instructions in the memory 630 to execute the method in the above embodiment.

[0155] In addition, the logic instructions in the aforementioned memory 630 can be implemented in the form of a software functional unit and, when sold or used as an independent product, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the portion that contributes to the prior art, or the portion of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application.

[0156] Based on the method in the above embodiment, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method in the above embodiment.

[0157] Based on the method in the above embodiment, an embodiment of the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method in the above embodiment.

[0158] It is understood that the processor in the embodiments of the present application may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0159] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium can be located in an ASIC.

[0160] The above embodiments can be implemented in whole or in part using software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions. When loaded and executed on a computer, the computer program instructions fully or partially produce the processes or functions described in the embodiments of this application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted via the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be magnetic media (e.g., floppy disk, hard disk, tape), optical media (e.g., DVD), or semiconductor media (e.g., solid-state drive (SSD)).

[0161] It will be understood that the various numerical numbers involved in the embodiments of the present application are merely distinctions for the convenience of description and are not intended to limit the scope of the embodiments of the present application.

[0162] It is easy for those skilled in the art to understand that the above is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. An Ethernet PHY chip testing device, characterized in that: include: Controller, automatic test module and standard PHY chip; An automatic test module, connected to the PHY chip to be tested or to the standard PHY chip, for generating a drive signal and performing signal comparison analysis; A standard PHY chip, configured to connect to and perform signal interaction with the PHY chip to be tested, generate a test signal, and return the test signal to the automatic test module; A controller is connected to and establishes communication with the PHY chip to be tested and the standard PHY chip, and is used to control the transmission path of the driving signal between the PHY chip to be tested and the standard PHY chip, and switch the communication protocol to implement multi-communication protocol testing; When the automatic test module is connected to the controller, the first communication protocol test mode or the second communication protocol test mode is executed; When the automatic test module is connected to the PHY chip to be tested, the parameter test mode is executed; The automatic test module is connected to the controller, the output end of the controller is connected to the PHY chip to be tested, and the output end of the PHY chip to be tested is connected to the standard PHY chip to execute a first communication protocol test mode; The output end of the controller is connected to the standard PHY chip, and the output end of the standard PHY chip is connected to the PHY chip to be tested, so as to execute a second communication protocol test mode.

2. The Ethernet PHY chip testing device according to claim 1, characterized in that: It also includes a signal switching module, the signal switching module includes a communication interface, and the signal switching module is connected to the automatic test module, the PHY chip to be tested, and the standard PHY chip through the communication interface; The signal switching module is used to switch signal paths during the test process to implement tests of different communication protocols.

3. The Ethernet PHY chip testing device according to claim 2, characterized in that: The automatic test module controls the signal switching module to connect with different modules. The signal switching module switches the communication interface so that the automatic test module connects to the controller or the PHY chip to be tested.

4. The Ethernet PHY chip testing device according to claim 3, characterized in that: The process of executing the first communication protocol test mode includes: The controller processes the driving signal generated by the automatic test module and sends it to the PHY chip to be tested; The PHY chip to be tested forwards the driving signal to the standard PHY chip; The controller receives the test signal returned by the standard PHY chip and transmits the test signal to the automatic test module for comparison; Change the communication protocol and repeat the above process until all communication protocols are traversed.

5. The Ethernet PHY chip testing device according to claim 3, characterized in that: The process of executing the second communication protocol test mode includes: The controller processes the driving signal generated by the automatic test module and sends it to the standard PHY chip; The standard PHY chip forwards the driving signal to the PHY chip to be tested; The controller receives a test signal returned by the PHY chip to be tested, and transmits the test signal to the automatic test module for comparison; Change the communication protocol and repeat the above process until all communication protocols are traversed.

6. The Ethernet PHY chip testing device according to claim 3, characterized in that: The automatic test module is directly connected to the PHY chip to be tested to execute a parameter test mode; The process of executing the parameter test mode includes: The automatic test module sends a driving signal to the PHY chip to be tested; The automatic test module receives a test signal returned by the PHY chip to be tested, compares the test signal with a driving signal, performs parameter testing and generates a test result.

7. The Ethernet PHY chip testing device according to claim 1, characterized in that: The controller is a high-speed controller of the media access control MAC corresponding to the PHY to be tested and the standard PHY, and the controller includes a CPU and an FPGA.

8. An Ethernet PHY chip testing method implemented based on the Ethernet PHY chip testing device according to any one of claims 1 to 7, characterized in that: include: generating a driving signal; Passing the driving signal through the PHY chip to be tested and the standard PHY chip to generate a test signal, and performing signal comparison analysis based on the test signal; The transmission path of the driving signal between the PHY chip to be tested and the standard PHY chip is controlled, and the communication protocol is switched to implement multi-communication protocol testing.

9. The Ethernet PHY chip testing method according to claim 8, characterized in that: The process of the multi-communication protocol test includes: The controller processes the driving signal generated by the automatic test module and sends it to the PHY chip under test. The PHY chip under test then sends it to the standard PHY chip and returns it to the controller. The automatic test module compares it with the driving signal and repeats the above signal processing process by changing the communication protocol until all communication protocols are traversed. The controller processes the driving signal generated by the automatic test module and sends it to the standard PHY chip. The standard PHY chip then sends it to the PHY chip under test and returns it to the controller. The automatic test module compares it with the driving signal, and the communication protocol is changed and the above signal processing process is repeated until all communication protocols are traversed. The PHY chip to be tested returns the driving signal sent by the automatic test module to the automatic test module for comparison with the driving signal, and performs relevant parameter tests. The above signal processing process is repeated by changing the communication protocol until all communication protocols are traversed.

10. An electronic device, characterized in that: include: at least one memory for storing a computer program; At least one processor is configured to execute the program stored in the memory, and when the program stored in the memory is executed, the processor is configured to execute the method according to claim 8 or 9.

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