A multi-channel parallel level conversion circuit test system

Abstract

The present invention discloses a multi-channel parallel level conversion circuit test system, which relates to the technical field of circuit testing. The system includes a test host, a multi-channel parallel level conversion circuit, a signal source module, a signal acquisition module, a control module, and a display module. The test host verifies the test logic for the entire process of circuit testing. The multi-channel parallel level conversion circuit serves as the target circuit to be tested. The signal source module generates test signals for circuit testing and constructs test cases for the test signals. The signal acquisition module collects the output signals of the multi-channel parallel level conversion circuit and generates circuit optimization output signals after signal gain, signal-to-noise optimization, and frequency band filtering. The control module conducts circuit testing on the target circuit based on the test cases and the circuit optimization output signals. Finally, the display module visually displays the test results.

Description

Technical Field

[0001] The invention relates to the technical field of circuit testing, in particular to a multi-channel parallel level conversion circuit testing system. Background Art

[0002] Level conversion circuits are key components in electronic systems that enable signal communication between devices with different voltage standards, and are widely used in high-speed communications, embedded systems, and multi-protocol interface scenarios. With the increase in circuit integration, the demand for multi-channel parallel level conversion circuits has increased significantly, but the complexity of their testing has also increased.

[0003] Traditional testing methods mostly use a single-channel serial test mode, which has low test efficiency and is difficult to cover the interaction between multiple channels; in addition, existing test systems have deficiencies in signal processing, such as weak noise suppression capabilities and poor dynamic signal adaptability, which limits the accuracy of test results. At the same time, the test case design is relatively simple, lacking comprehensive verification of abnormal scenarios, boundary conditions, and fault tolerance, making it difficult to meet the testing requirements of high-reliability scenarios. Therefore, there is an urgent need for an efficient, accurate, and automated verification capability multi-channel parallel level conversion circuit test system to solve the problems of low test efficiency, insufficient signal processing capabilities, and incomplete test coverage in the prior art. Summary of the invention

[0004] In order to solve the above problems, an object of the present invention is to provide a multi-channel parallel level conversion circuit testing system.

[0005] The object of the present invention can be achieved by the following technical solutions: A multi-channel parallel level conversion circuit test system includes a test host, the test host is communicatively connected to the multi-channel parallel level conversion circuit, a signal source module, a signal acquisition module, a control module and a display module;

[0006] The test host is used to perform test logic verification on the entire process of circuit testing;

[0007] The multi-channel parallel level conversion circuit is used as a target circuit to be tested;

[0008] The signal source module is used to generate a test signal for circuit testing and construct a test case corresponding to the test signal;

[0009] The signal acquisition module is used to collect the output signal of the multi-channel parallel level conversion circuit, and perform signal gain, signal-to-noise optimization and frequency band filtering on the output signal, thereby generating a corresponding circuit tuning output signal;

[0010] The control module performs circuit testing on the target circuit according to the test case and the circuit tuning output signal;

[0011] The display module is used for visually displaying the test results of the circuit test.

[0012] Furthermore, the process of the test host performing test logic verification on the entire process of the circuit test includes:

[0013] Setting the verification working period of the test host;

[0014] The multi-channel parallel level conversion circuit, signal source module, signal acquisition module, control module, and display module that are communicatively connected to the test host respectively edit their respective test script files and transmit the test script files to the test host;

[0015] During the verification working period, the test host constructs corresponding test logic according to the ownership object of the test script file. If the test script file is correctly executed according to the test logic, it is determined that the ownership object corresponding to the test script file is in a logically correct state; otherwise, it is determined that the ownership object corresponding to the test script file is in a logically incorrect state.

[0016] Furthermore, the multi-channel parallel level conversion circuit, as the target circuit to be tested for the circuit test, has a structure including:

[0017] The multi-channel parallel level conversion circuit includes several high-level circuits and several low-level circuits. The low-level circuits are connected in parallel with the high-level circuits. Each high-level circuit or low-level circuit is composed of an input interface, a level converter, a channel isolation unit, and an output interface;

[0018] The several high-level circuits are sequentially numbered and denoted as i, where i = 1, 2, 3,..., n. The several low-level circuits are sequentially numbered and denoted as j, where j = 1, 2, 3,..., m. Here, both n and m are natural numbers greater than 0.

[0019] Furthermore, the process of the signal source module generating the test signal for the circuit test and constructing the test case corresponding to the test signal includes:

[0020] The signal source module configures the test scenario for the circuit test. The test scenario includes a normal working scenario and an abnormal working scenario, and sets the first test sub-case, the second test sub-case, and the third test sub-case corresponding to the test scenario;

[0021] The first test sub-case is used to control the test scenario to cover all channels, voltage combinations, and signal types in the multi-channel parallel level conversion circuit;

[0022] The second test sub-case is used to control the amplitude, frequency, duty cycle, and edge rate of the test signal in the multi-channel parallel level conversion circuit;

[0023] The third test sub - case is used to control the test signal for repeated testing;

[0024] Construct a test signal according to the case content of the first test sub - case, the second test sub - case, and the third test sub - case. Integrate the first test sub - case, the second test sub - case, and the third test sub - case to construct a regular test case corresponding to the test signal, synchronously construct an auxiliary test case corresponding to the test signal, and integrate the regular test case and the auxiliary test case as the final test case.

[0025] Furthermore, the process in which the signal acquisition module acquires the output signal of the multi - channel parallel level conversion circuit and performs signal gain, signal - to - noise optimization, and frequency band filtering on the output signal converted from the test signal, and then generates a corresponding circuit - optimized output signal includes:

[0026] When the multi - channel parallel level conversion circuit inputs a test signal, synchronously generate the output signal obtained after the test signal is converted by the multi - channel parallel level conversion circuit. The signal acquisition module acquires the output signal converted from the test signal, obtains the signal peak value of the output signal converted from the test signal and normalizes it, sets the gain multiple of the output signal converted from the test signal according to the normalized signal peak value, and then performs signal gain on the output signal converted from the test signal;

[0027] Perform signal - to - noise optimization and frequency band filtering on the output signal converted from the test signal after signal gain;

[0028] Convert the output signal converted from the test signal into a low - mean - noise output signal through signal - to - noise optimization;

[0029] Convert the low - mean - noise output signal into a circuit - optimized signal through frequency band filtering.

[0030] Furthermore, the process of the signal - to - noise optimization includes:

[0031] Set a number of sampling points, divide the output signal converted from the test signal into several local sampling signals according to the preset signal frame length and the number of sampling points, perform signal - to - noise ratio sampling on the corresponding local sampling signals at each sampling point, and then obtain the signal - to - noise ratio of each local sampling signal;

[0032] Judge whether the signal - to - noise ratio of the local sampling signal meets the standard;

[0033] If so, do not perform any operation;

[0034] If not, further analyze the signal frequency value of the local sampling signal, divide the local sampling signal into low-frequency signals, medium-frequency signals, and high-frequency signals according to the signal frequency value, and perform noise processing using a moving average filtering method, a multi-channel joint noise reduction method, or a wavelet threshold denoising method;

[0035] Integrate the low-frequency signals, medium-frequency signals, and high-frequency signals after noise processing to construct a low-mean noise output signal.

[0036] Further, the process of the control module performing circuit testing on the target circuit according to the test cases and the circuit tuning output signal includes:

[0037] The control module sets the test period and edits the test instructions;

[0038] During the test period, the control module obtains the test cases and the circuit tuning output signal as the test start samples, and performs circuit testing on the target circuit according to the different edited test instructions, where the test instructions include P1 and P2;

[0039] The types of circuit testing include circuit function testing and circuit performance testing;

[0040] When the test instruction is P1, perform circuit function testing on the target circuit;

[0041] When the test instruction is P2, perform circuit performance testing on the target circuit.

[0042] Further, the process of the display module visually displaying the test results of the circuit testing includes:

[0043] The display module consists of a display area, a display module one, and a display module two;

[0044] The display area is used to dynamically and visually circularly rotate and display the display module one and the display module two;

[0045] The display module one is used to display the test results of the circuit function testing;

[0046] The display module two is used to display the test results of the circuit performance testing.

[0047] Compared with the prior art, the beneficial effects of the present invention are as follows: Through the multi-channel parallel level conversion circuit and modular design, it supports synchronous testing of multiple channels, significantly improving the testing efficiency. The signal acquisition module adopts signal gain, signal-to-noise optimization, and frequency band filtering technologies, adaptively adjusts the gain multiple according to the signal peak value, and respectively adopts moving average filtering, multi-channel joint noise reduction, and wavelet threshold denoising methods for low-frequency, medium-frequency, and high-frequency signals, effectively suppressing noise interference and improving the signal-to-noise ratio and accuracy of the test signal. By constructing conventional test cases and auxiliary test cases, multi-dimensional verification of the circuit function, performance, and reliability is achieved to ensure that the test covers harsh scenarios. The test host automatically verifies the logical correctness by receiving the test script files of each module, performs logical reset on abnormal modules, reduces manual intervention, and enhances the system robustness. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a schematic diagram of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0049] As Figure 1 shown, a multi-channel parallel level conversion circuit test system includes a test host, and the test host is communicatively connected to a multi-channel parallel level conversion circuit, a signal source module, a signal acquisition module, a control module, and a display module;

[0050] The test host is used to verify the test logic for the entire process of circuit testing;

[0051] The multi-channel parallel level conversion circuit is used as the target circuit to be tested;

[0052] The signal source module is used to generate test signals for circuit testing and construct test cases corresponding to the test signals;

[0053] The signal acquisition module is used to collect the output signals of the multi-channel parallel level conversion circuit, perform signal gain, signal-to-noise optimization, and frequency band filtering on the output signals, and then generate corresponding circuit optimization output signals;

[0054] The control module performs circuit testing on the target circuit according to the test cases and the circuit optimization output signals;

[0055] The display module is used to visually display the test results of the circuit testing.

[0056] It should be further noted that in the specific implementation process, the process of the test host verifying the test logic for the entire process of circuit testing includes:

[0057] Setting the verification working period of the test host;

[0058] The multi-channel parallel level conversion circuit, signal source module, signal acquisition module, control module, and display module that communicate with the test host respectively edit their own test script files, and transmit the test script files to the test host through the communication between each of them and the test host;

[0059] During the verification working period, the test host receives all the test script files, and constructs corresponding test logics according to the ownership objects of the test script files. If the test script files are correctly executed according to the test logics, it is determined that the ownership objects corresponding to the test script files are in a logically correct state; otherwise, it is determined that the ownership objects corresponding to the test script files are in a logically incorrect state;

[0060] The ownership objects in the logically correct state can correctly execute the corresponding functional parts of the circuit tests they are responsible for without performing any operations. The ownership objects in the logically incorrect state cannot correctly execute the corresponding functional parts of the circuit tests they are responsible for, and the corresponding ownership objects are logically reset until they return to the logically correct state.

[0061] It should be noted that the multi-channel parallel level conversion circuit, signal source module, signal acquisition module, control module, and display module that communicate with the test host are all ownership objects.

[0062] It should be further noted that in the specific implementation process, the multi-channel parallel level conversion circuit, as the target circuit to be tested, has the following structure:

[0063] The multi-channel parallel level conversion circuit as the target circuit includes several high-level circuits and several low-level circuits. The low-level circuits are connected in parallel with the high-level circuits. Each high-level circuit or low-level circuit consists of an input interface, a level converter, a channel isolation unit, and an output interface;

[0064] The several high-level circuits are sequentially numbered, and the numbers are denoted as i, where i = 1, 2, 3,..., n, and n is a natural number greater than 0. The several low-level circuits are sequentially numbered, and the numbers are denoted as j, where j = 1, 2, 3,..., m, and m is a natural number greater than 0;

[0065] Input interface: used to receive signals from the source device, and these signals may be of different level standards;

[0066] Level Converter: It is the core part of the circuit. Each channel will have one or more level converters, and they can be implemented using the following several technologies: Transistor level converter: Using NPN or PNP transistors, MOSFETs, etc. to convert levels; Dedicated level conversion chips: Such as the 74LVC series, these chips are designed to convert between different levels, such as from TTL to CMOS, Resistive voltage divider network: In some cases, a resistive network can be used to adjust the level.

[0067] Channel Isolation Unit: To ensure that there is no interference between each channel, it specifically includes isolation components, such as optocouplers, transformers, or capacitive isolation;

[0068] Output Interface: Used to output the converted signal from here to the target device.

[0069] It should be further noted that in the specific implementation process, the process of the signal source module generating the test signal for circuit testing and constructing the test cases corresponding to the test signal includes:

[0070] The signal source module configures the test scenarios for circuit testing. The test scenarios include normal working scenarios and abnormal working scenarios, and sets the first test sub-case, the second test sub-case, and the third test sub-case corresponding to the test scenarios;

[0071] The first test sub-case is used to control the test scenario to cover all channels, voltage combinations, and signal types in the multi-channel parallel level conversion circuit. Among them, the signal types include static signals and dynamic signals;

[0072] The second test sub-case is used to control the amplitude, frequency, duty cycle, and edge rate of the test signal in the multi-channel parallel level conversion circuit;

[0073] The third test sub-case is used to control the test signal to perform repeated tests;

[0074] According to the content of the first test sub-case, the second test sub-case, and the third test sub-case, the test signal for the final circuit testing is constructed, and the first test sub-case, the second test sub-case, and the third test sub-case are integrated to construct the regular test case corresponding to the test signal;

[0075] Synchronously construct the function test case, boundary condition test case, and exception and fault tolerance test case corresponding to the test signal, and use the function test case, boundary condition test case, and exception and fault tolerance test case as the auxiliary test cases of the test signal;

[0076] Integrate the regular test case and the auxiliary test case as the final test case of the circuit signal.

[0077] It should be noted that the function test cases are used for basic conversion verification, multi-channel parallel testing, and bidirectional conversion testing. The basic conversion verification includes static testing and dynamic testing; the boundary condition test cases are used for voltage limit testing, temperature drift testing, and load capacity testing; the exception and fault tolerance test cases are used for overvoltage / undervoltage protection testing, ESD immunity testing, and hot plugging testing.

[0078] It should be further noted that in the specific implementation process, the signal acquisition module acquires the output signals of the multi-channel parallel level conversion circuit, and performs signal gain, signal-to-noise optimization, and frequency band filtering on the output signals, and then the process of generating the corresponding circuit optimization output signals includes:

[0079] When the multi-channel parallel level conversion circuit inputs a test signal, synchronously acquire the output signal obtained after the test signal generated by the multi-channel parallel level conversion circuit is converted, and the signal acquisition module acquires the output signal after the conversion of the test signal, and then obtains the signal peak value corresponding to the output signal after the conversion of the test signal, and normalizes the signal peak value, and sets the gain multiple corresponding to the output signal after the conversion of the test signal according to the normalized signal peak value, and then performs signal gain on the output signal after the conversion of the test signal;

[0080] Set the peak intensity interval, which includes the peak valley intensity interval, the flat peak intensity interval, and the peak wave intensity interval, and denote the peak valley intensity interval, the flat peak intensity interval, and the peak wave intensity interval as Ω1, Ω2, and Ω3 respectively;

[0081] Among them, Ω1 = (0, 0.3], Ω2 = (0.3, 0.7], Ω3 = (0.7, 1);

[0082] Denote the normalized signal peak value as τ, and perform the following operations:

[0083] If τ ∈ Ω1, then set the gain multiple of the output signal after the conversion of the test signal to 2 times;

[0084] If τ ∈ Ω2, then set the gain multiple of the output signal after the conversion of the test signal to 1.5 times;

[0085] If τ ∈ Ω3, then set the gain multiple of the output signal after the conversion of the test signal to 1 time;

[0086] Perform signal-to-noise optimization and frequency band filtering on the output signal after the conversion of the test signal after signal gain;

[0087] Convert the output signal after the conversion of the test signal into a low mean noise output signal through signal-to-noise optimization;

[0088] The content of the signal-to-noise optimization is as follows:

[0089] Set a number of sampling points, and divide the output signal converted from the test signal into several local sampling signals according to a preset signal frame length and the number of sampling points. Perform signal-to-noise ratio sampling on the corresponding local sampling signals at each sampling point, and then obtain the signal-to-noise ratio of each local sampling signal.

[0090] Judge whether the signal-to-noise ratio of the local sampling signal meets the standard.

[0091] If so, do nothing.

[0092] If not, further analyze the signal frequency value of the local sampling signal, and divide the local sampling signal into low-frequency signals, intermediate-frequency signals, and high-frequency signals according to the signal frequency value.

[0093] When the local sampling signal is a low-frequency signal, use the moving average filtering method to process the noise of the local sampling signal.

[0094] When the local sampling signal is an intermediate-frequency signal, use the multi-channel joint noise reduction method to process the noise of the local sampling signal.

[0095] When the local sampling signal is a high-frequency signal, use the wavelet threshold denoising method to process the noise of the local sampling signal.

[0096] Integrate the low-frequency signal, intermediate-frequency signal, and high-frequency signal after noise processing to construct a low-mean noise output signal.

[0097] Convert the low-mean noise output signal into a circuit optimization signal through frequency band filtering.

[0098] The content of the frequency band filtering is as follows:

[0099] Set an impedance mismatch correction interval and a signal edge optimization interval.

[0100] If a certain frequency band in the low-mean noise signal is within the impedance mismatch correction interval, integrate all the low-mean noise signals in the corresponding frequency band as the first subset of signals to be optimized. If a certain frequency band in the low-mean noise signal is within the signal edge optimization interval, integrate all the low-mean noise signals in the corresponding frequency band as the second subset of signals to be optimized.

[0101] The problem phenomenon of the first subset of signals to be optimized is: signal overshoot / vibration.

[0102] The corresponding optimization action to be performed is: identify the overshoot frequency through a low-pass filter, calculate the termination resistance of the multi-channel parallel level conversion circuit, and then locate and filter out the frequency band where the termination resistance does not meet the requirements.

[0103] The problem phenomenon of the second subset of signals to be optimized is: signal edge blur.

[0104] The corresponding optimization actions to be performed are: reducing the cut-off frequency corresponding to the low-pass filter, shortening the signal path or adding a buffer, so as to convert the low-mean noise signal into the circuit optimization output signal.

[0105] It should be further noted that in the specific implementation process, the process of the control module performing circuit testing on the target circuit according to the test case and the circuit optimization output signal includes:

[0106] The control module sets the test period and edits the test instructions;

[0107] During the test period, the control module obtains the test case and the circuit optimization output signal as the test start samples, and performs circuit testing on the target circuit according to the different edited test instructions, where the test instructions include P1 and P2;

[0108] The types of circuit testing include circuit function testing and circuit performance testing;

[0109] The corresponding relationship between different test instructions and the types of circuit testing is as follows:

[0110] When the test instruction is P1, circuit function testing is performed on the target circuit. The content of the circuit function testing is: testing the logic function of the target circuit, verifying whether the logic gates, flip-flops, state machines, etc. of the digital circuit are working properly (such as whether the output is 1 when the input A = 1 and B = 0), testing the signal integrity of the target circuit, for example, checking whether the bandwidth and distortion of the circuit signal meet the expectations; testing whether the protocol of the communication interface corresponding to the target circuit is compatible and whether the data transmission is correct;

[0111] When the test instruction is P2, circuit performance testing is performed on the target circuit. The content of the circuit performance testing is: testing the timing characteristic parameters of the target circuit, and the timing characteristic parameters include rise time, fall time and propagation delay, testing the frequency response parameters of the target circuit, and the frequency response parameters include bandwidth, phase margin and group delay, testing the power consumption of the target circuit, and the power consumption includes static power consumption and dynamic power consumption.

[0112] It should be further noted that in the specific implementation process, the process of the display module visually displaying the test results of the circuit testing includes:

[0113] The display module is composed of a display area, display module one and display module two;

[0114] The display area is used to dynamically and visually cycle through and display display module one and display module two;

[0115] The display module one is used to display the test results of the circuit function testing;

[0116] The display module two is used to display the test results of the circuit performance test;

[0117] The display duration set by the display module one is denoted as Time1;

[0118] The display duration set by the display module two is denoted as Time2;

[0119] The transition duration between the display module one and the display module two is denoted as Time3.

[0120] Among them, Time1, Time2, and Time3 are all timestamps greater than 0;

[0121] Only one of the display module one or the display module two is displayed in the display area at the same time period. When the display duration of the display module one in the display area reaches Time1, the display module two is switched to the display area according to the countdown of the transition duration Time3. When the display duration of the display module two in the display area reaches Time2, the display module one is directly jumped to the display area.

[0122] The above embodiments are only used to illustrate the technical method of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical method of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical method of the present invention.

Claims

1. A multi-channel parallel level conversion circuit test system, comprising a test host, characterized in that, The test host is communicatively connected to a multi-channel parallel level conversion circuit, a signal source module, a signal acquisition module, a control module, and a display module; The test host is used to verify the test logic for the entire process of circuit testing; The multi-channel parallel level conversion circuit is used as the target circuit to be tested; The signal source module is used to generate test signals for circuit testing and construct test cases corresponding to the test signals; The signal acquisition module is used to collect the output signals of the multi-channel parallel level conversion circuit, perform signal gain, signal-to-noise optimization, and frequency band filtering on the output signals, and then generate corresponding circuit optimization output signals; The control module performs circuit testing on the target circuit according to the test cases and the circuit optimization output signals; The display module is used to visually display the test results of the circuit testing; The process by which the signal source module generates test signals for circuit testing and constructs test cases corresponding to the test signals includes: The signal source module configures the test scenarios for circuit testing. The test scenarios include normal working scenarios and abnormal working scenarios, and sets the first test sub-case, the second test sub-case, and the third test sub-case corresponding to the test scenarios; The first test sub-case is used to control the test scenario to cover all channels, voltage combinations, and signal types in the multi-channel parallel level conversion circuit; The second test sub-case is used to control the amplitude, frequency, duty cycle, and edge rate of the test signals in the multi-channel parallel level conversion circuit; The third test sub-case is used to control the test signals to perform repeated tests; Construct test signals according to the case content of the first test sub-case, the second test sub-case, and the third test sub-case, integrate the first test sub-case, the second test sub-case, and the third test sub-case, construct a conventional test case corresponding to the test signals, synchronously construct an auxiliary test case corresponding to the test signals, and integrate the conventional test case and the auxiliary test case as the final test case.

2. The multi-channel parallel level conversion circuit test system according to claim 1, characterized in that, The process by which the test host verifies the test logic for the entire process of circuit testing includes: Set the verification working period of the test host; The multi-channel parallel level conversion circuit, the signal source module, the signal acquisition module, the control module, and the display module that are communicatively connected to the test host respectively edit their respective test script files and transmit the test script files to the test host; During the verification working period, the test host constructs corresponding test logics according to the ownership objects of the test script files. If the test script files are correctly executed according to the test logics, it is determined that the ownership objects corresponding to the test script files are in a logically correct state; otherwise, it is determined that the ownership objects corresponding to the test script files are in a logically incorrect state.

3. A multi-channel parallel level conversion circuit test system according to claim 2, characterized in that, The multi-channel parallel level conversion circuit is used as the target circuit to be tested, and its structure includes: The multi-channel parallel level conversion circuit includes several high-level circuits and several low-level circuits. The low-level circuits are connected in parallel with the high-level circuits. Each high-level circuit or low-level circuit is composed of an input interface, a level converter, a channel isolation unit, and an output interface; A number of high-level circuits are sequentially numbered and denoted as i, where i = 1, 2, 3, ……, n. A number of low-level circuits are sequentially numbered and denoted as j, where j = 1, 2, 3, ……, m. Here, both n and m are natural numbers greater than 0.

4. A multi-channel parallel level conversion circuit test system according to claim 3, characterized in that The process by which the signal acquisition module acquires the output signals of the multi-channel parallel level conversion circuit, and performs signal gain, signal-to-noise optimization, and frequency band filtering on the output signals converted from the test signals, and then generates the corresponding circuit optimization output signals includes: When the multi-channel parallel level conversion circuit inputs a test signal, synchronously generate the output signal obtained after the test signal is converted by the multi-channel parallel level conversion circuit. The signal acquisition module acquires the output signal converted from the test signal, obtains the signal peak value of the output signal converted from the test signal and normalizes it, sets the gain multiple of the output signal converted from the test signal according to the normalized signal peak value, and then performs signal gain on the output signal converted from the test signal; Perform signal-to-noise optimization and frequency band filtering on the output signal converted from the test signal after signal gain; Convert the output signal converted from the test signal into a low-mean noise output signal through signal-to-noise optimization; Convert the low-mean noise output signal into a circuit optimization signal through frequency band filtering.

5. A multi-channel parallel level conversion circuit test system according to claim 4, characterized in that, The process of the signal-to-noise optimization includes: Set a number of sampling points, divide the output signal converted from the test signal into several local sampling signals according to the preset signal frame length and a number of sampling points, perform signal-to-noise ratio sampling on the corresponding local sampling signals at each sampling point, and then obtain the signal-to-noise ratio of each local sampling signal; Judge whether the signal-to-noise ratio of the local sampling signal meets the standard; If so, do not perform any operation; If not, further analyze the signal frequency value of the local sampling signal, divide the local sampling signal into low-frequency signals, intermediate-frequency signals, and high-frequency signals according to the signal frequency value, and respectively perform corresponding noise processing using the moving average filtering method, multi-channel joint noise reduction method, and wavelet threshold denoising method; Integrate the low-frequency signal, intermediate-frequency signal, and high-frequency signal after noise processing, and construct a low-mean noise output signal.

6. The multi-channel parallel level conversion circuit test system according to claim 5, characterized in that, The process by which the control module performs circuit testing on the target circuit according to the test cases and the circuit optimization output signals includes: The control module sets the test period and edits the test instructions; During the test period, the control module obtains the test cases and the circuit optimization output signals as the test start samples, and performs circuit testing on the target circuit according to the different test instructions edited, where the test instructions include P1 and P2; The types of circuit testing include circuit function testing and circuit performance testing; When the test instruction is P1, perform circuit function testing on the target circuit; When the test instruction is P2, perform circuit performance testing on the target circuit.

7. A multi-channel parallel level conversion circuit test system according to claim 6, characterized in that, The process by which the display module visually displays the test results of the circuit testing includes: The display module consists of a display area, display module one, and display module two; The display area is used to dynamically and visually cyclically display display module one and display module two in a carousel; The display module one is used to display the test results of the circuit function testing; The display module II is used to display the test results of the circuit performance test.

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