Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel, which can inhibit reduction of aperture ratio and protect a semiconductor film of a TFT (Thin Film Transistor) at the same time. The array substrate (21) includes a first TFT (27) having: a first insulating film (31); a first semiconductor film (27D) disposed on an upper layer thereof; a second insulating film (33) disposed on an upper layer thereof; a first gate electrode (27E) disposed on the upper layer thereof; and a first source electrode (27B) and a first drain electrode (27C) comprising a metal film disposed above the third insulating film and connected to the first semiconductor film (27D) through a first contact hole (36) penetrating a third insulating film (34) disposed above the first source electrode and the first drain electrode. The array substrate (21) includes a first TFT (27) having an auxiliary film (32) made of a non-metallic material, the auxiliary film (32) being disposed at a position overlapping at least the lower surfaces of the first source electrode (27B) and the first drain electrode (27C) on the upper layer or the lower layer of the first semiconductor film (27D).

Description

Technical Field

[0001] The present technology relates to an array substrate and a display panel. Background Art

[0002] It is known that in display panels such as liquid crystal panels and organic EL (electro-luminescence) panels, TFTs (thin film transistors) are used as switching elements. TFTs are formed by stacking various thin films on an array substrate (active matrix substrate, TFT substrate) constituting a display panel. Patent document 1 discloses a case where two types of TFTs are formed on the same substrate. Prior art literature Patent Literature

[0003] Patent Document 1: Japanese Patent Application Publication No. 2020-202223

[0004] The TFT described in Patent Document 1 includes: a channel formed of a first polysilicon at the source and drain and a second polysilicon that imparts conductivity to the first polysilicon; and a second TFT having a channel formed of an oxide semiconductor and a source and a drain that impart conductivity to the oxide semiconductor. In addition, in the oxide semiconductor film of the second TFT, a metal protective film is formed in the portion connected to the drain electrode and the source electrode. The metal protective film is provided to protect the oxide semiconductor film from the influence of hydrofluoric acid when hydrofluoric acid is cleaned in the through hole for the drain electrode and the source electrode. Thus, the degradation of the oxide semiconductor film can be suppressed. Summary of the invention Technical Problems to be Solved by the Invention

[0005] In the case of the above-mentioned metal protective film, in fact, considering the deviation of the plane pattern in manufacturing and the position deviation between the plane patterns of each part, the metal protective film needs to contain a margin and be formed larger. However, if the plane size of the metal protective film becomes larger, the aperture ratio may be reduced because the metal material has light-shielding properties.

[0006] The technology described in the present specification has been accomplished based on the above-mentioned actual situation, and its purpose is to protect the semiconductor film of the TFT while suppressing a decrease in the aperture ratio. Solutions for solving problems

[0007] (1) An array substrate related to the technology described in the specification of the present application includes a first TFT, wherein the first TFT has: a first insulating film, which is arranged on the upper side of an insulating substrate; a first semiconductor film, which is arranged on the upper layer of the first insulating film; a second insulating film, which is arranged on the upper layer of the first semiconductor film; a first gate electrode, which is arranged on the upper layer of the second insulating film and overlaps with the first semiconductor film; a third insulating film, which is arranged on the upper layer of the first gate electrode; a first source electrode and a first drain electrode, which are composed of a metal film arranged on the upper layer of the third insulating film and are connected to the first semiconductor film through a first contact hole penetrating the third insulating film; and an auxiliary film, which is arranged on the upper layer or lower layer of the first semiconductor film, at least at a position overlapping with the lower surface of the first source electrode and the first drain electrode, and is made of a non-metallic material.

[0008] (2) In addition, in the array substrate described above in (1), the auxiliary film may be disposed on the upper layer of the first semiconductor film and may be made of a transparent conductive material.

[0009] (3) In addition, in the array substrate described above in (1), the auxiliary film may be disposed under the first semiconductor film and made of the same material as the first semiconductor film.

[0010] (4) In addition, based on any one of the above (1) to (3), the above-mentioned array substrate may also include a first shading portion on the lower side of the first insulating film, wherein the first shading portion overlaps with the first gate electrode but does not overlap with the lower surface of the first source electrode and the first drain electrode.

[0011] (5) In addition, based on any one of the above (1) to (4), the first TFT can also be a double-gate structure TFT further having a second gate electrode, and the second gate electrode is arranged in a lower layer of the first insulating film.

[0012] (6) In addition, based on the above (5), the above-mentioned array substrate may also include a second TFT, wherein the second TFT has: a second semiconductor film; a gate insulating film, which is arranged on the upper layer of the second semiconductor film; a third gate electrode, which is arranged on the upper layer of the gate insulating film and is made of the same material as the second gate electrode; the first insulating film, which is arranged on the upper layer of the third gate electrode; the third insulating film, which is arranged on the upper layer of the first insulating film; and a second source electrode and a second drain electrode, which are connected to the second semiconductor film from the upper layer of the third insulating film through a second contact hole that penetrates the third insulating film, the first insulating film and the gate insulating film, the first semiconductor film of the first TFT is made of an oxide semiconductor material, and the second semiconductor film of the second TFT is made of a polysilicon semiconductor material.

[0013] (7) A display panel related to the technology described in the specification of the present application includes: an array substrate of any one of (1) to (6) above; a relative substrate arranged relative to the array substrate in a form with an internal space between the substrate and the array substrate; and a liquid crystal layer sealed in the internal space. Effects of the Invention

[0014] According to the technology described in the specification of the present application, it is possible to protect the semiconductor film of the TFT while suppressing a decrease in the aperture ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic plan view of a liquid crystal panel according to the first embodiment. Figure 2 This is a cross-sectional view of a liquid crystal panel. Figure 3 is a circuit diagram showing a pixel arrangement in a display area of ​​an array substrate. Figure 4 It is a cross-sectional view of the array substrate near the first TFT and the second TFT. Figure 5 Yes Figure 4 An enlarged cross-sectional view of the vicinity of the first TFT. Fig. 6A It is shown Figure 4 FIG. 1 is a diagram showing the manufacturing process of the array substrate. Figure 6B It shows that Fig. 6A A diagram of subsequent manufacturing steps of the array substrate. Figure 6C It shows that Figure 6B A diagram of subsequent manufacturing steps of the array substrate. Fig.6D It shows that Figure 6C A diagram of subsequent manufacturing steps of the array substrate. Fig. 6E It shows that Fig.6D A diagram of subsequent manufacturing steps of the array substrate. Fig. 6F It shows that Fig. 6E A diagram of subsequent manufacturing steps of the array substrate. Fig. 7A 1 is a diagram showing a manufacturing process of an array substrate according to Comparative Example 1. Figure 7B It shows that Fig. 7A A diagram of subsequent manufacturing steps of the array substrate. Figure 8 It is an enlarged cross-sectional view of the first TFT of the array substrate according to the second embodiment. Fig.9A It is shown Figure 8 FIG. 1 is a diagram showing the manufacturing process of the array substrate. Fig. 9B It shows that Fig.9A A diagram of subsequent manufacturing steps of the array substrate. Fig. 9C It shows that Fig. 9B A diagram of subsequent manufacturing steps of the array substrate. Fig.9D It shows that Fig. 9C A diagram of subsequent manufacturing steps of the array substrate. Fig.9E It shows that Fig.9D A diagram of subsequent manufacturing steps of the array substrate. Fig.10 It is an enlarged cross-sectional view of a first TFT of an array substrate according to another embodiment. DETAILED DESCRIPTION

[0016] <Implementation Method 1> Reference Figures 1 to 6F A liquid crystal panel 11 (an example of a display panel) according to Embodiment 1 will be described. In addition, an X-axis, a Y-axis, and a Z-axis are shown in the drawings, and the directions of the axes are drawn so as to be common in the drawings.

[0017] like Figure 1 As shown, the surface of the liquid crystal panel 11 is divided into a display area (active area) AA that can display images and is arranged on the central side, and a non-display area (non-active area) NAA that is arranged on the peripheral side in the form of surrounding the display area AA and is frame-shaped (frame-shaped) when viewed from above. Figure 1In the figure, the single-point dash line represents the outer shape of the display area AA, and the area outside the single-point dash line is the non-display area NAA. The planar shape of the liquid crystal panel 11 is not limited, but in the present embodiment, the whole is a longitudinally long rectangle, the short side direction is consistent with the X-axis direction, the long side direction is consistent with the Y-axis direction of each drawing, and the thickness direction is consistent with the Z-axis direction.

[0018] like Figure 2 As shown, the liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21. Between the pair of substrates 20 and 21, at least a liquid crystal layer 22 and a sealing portion 23 that seals the liquid crystal layer 22 are sandwiched. The liquid crystal layer 22 includes liquid crystal molecules, which are substances whose optical properties change with the application of an electric field. The sealing portion 23 as a whole is in the shape of a rectangular frame when viewed from above, and the liquid crystal layer 22 is surrounded by a non-display area NAA. The gap (cell gap) corresponding to the thickness of the liquid crystal layer 22 is maintained by the sealing portion 23. Polarizers 24 are respectively attached to the outer surface sides of the pair of substrates 20 and 21.

[0019] In a pair of substrates 20 and 21, the counter substrate (CF substrate) 20 is arranged on the front side (display surface side), and the array substrate (active matrix substrate, TFT substrate) 21 is arranged on the back side. Both the counter substrate 20 and the array substrate 21 are formed by laminating various films on the inner surface side (liquid crystal layer 22 side) of a glass substrate that is substantially transparent and has excellent light transmittance.

[0020] A backlight device for irradiating light to the liquid crystal panel 11 is provided on the back side (array substrate 21 side) of the liquid crystal panel 11. The liquid crystal panel 11 involved in this embodiment is used, for example, in a head-mounted display and has extremely high precision. The pixel density of the liquid crystal panel 11 is, for example, in the range of about 800 ppi to 1800 ppi.

[0021] The array substrate 21 is larger than the relative substrate 20, and a part thereof protrudes more than the relative substrate 20. A flexible substrate 13 is mounted on a protruding portion 21A of the array substrate 21. The flexible substrate 13 is configured to form a plurality of wiring patterns on a substrate having insulation and flexibility. One end side of the flexible substrate 13 is connected to the array substrate 21, and the other end side is connected to an external control substrate (signal supply source). Various signals supplied from the control substrate are transmitted to the liquid crystal panel 11 via the flexible substrate 13.

[0022] like Figure 3 As shown in FIG. 1 , a plurality of gate wirings (scanning wirings) 25 and source wirings (image wirings) 26 are arranged in a grid pattern in the display area AA of the array substrate 21. The gate wirings 25 extend approximately along the X-axis direction in the form of crossing the display area AA. A plurality of gate wirings 25 are arranged at intervals in the Y-axis direction. The scanning signal output from the first circuit unit 14A described later is Figure 3The upper side of the display area AA is sequentially supplied to the plurality of gate wirings 25. The source wiring 26 extends substantially in the Y-axis direction in the form of vertically traversing the display area AA, and intersects with the gate wiring 25. The plurality of source wirings 26 are arranged at intervals in the X-axis direction. The image signal output from the second circuit unit 14B described later is distributed to the source wiring 26.

[0023] A first TFT 27 and a pixel electrode 28 are provided near the intersection of the gate wiring 25 and the source wiring 26. A plurality of first TFTs 27 and pixel electrodes 28 are regularly arranged along the X-axis direction and the Y-axis direction, respectively. The first TFT 27 is connected to the gate wiring 25, the source wiring 26, and the pixel electrode 28. When the first TFT 27 is driven based on the scanning signal supplied to the gate wiring 25, the pixel electrode 28 is charged to a potential based on the image signal supplied to the source wiring 26.

[0024] like Figure 1 As shown, a circuit unit (peripheral circuit unit) 14 is provided in the non-display area NAA of the array substrate 21. The circuit unit 14 includes a first circuit unit 14A and a second circuit unit 14B. The first circuit unit 14A is configured in a pair in the form of sandwiching the display area AA from both sides in the X-axis direction, but can also be provided on only one side.

[0025] The first circuit unit 14A is provided in a strip-shaped range extending in the Y-axis direction. The first circuit unit 14A is used to supply a scanning signal to the gate wiring 25, and is provided monolithically on the array substrate 21. The first circuit unit 14A is a GDM (Gate Driver Monolithic) circuit. The first circuit unit 14A includes a shift register circuit that outputs a scanning signal at a specified timing, a buffer circuit for amplifying the scanning signal, and the like.

[0026] The second circuit portion 14B is arranged at a position sandwiched between the display area AA and the flexible substrate 13 in the Y-axis direction. The second circuit portion 14B is arranged within a strip-shaped range extending in the X-axis direction. The second circuit portion 14B is used to supply an image signal (data signal) to the source wiring 26, and is monolithically arranged on the array substrate 21. The second circuit portion 14B includes a demultiplexer circuit (source signal division circuit) and the like. The second circuit portion 14B has a switch function of dividing the image signal (source signal) supplied by the source driver 14C and distributing it to each source wiring 26. The first circuit portion 14A and the second circuit portion 14B constituting the circuit portion 14 have various circuit elements, but at least the second TFT 15 is included therein.

[0027] Next, the cross-sectional structure of the array substrate 21 is described in detail. Figure 4, the cross-sectional structure of the display area AA (first TFT 27) and the cross-sectional structure of the circuit portion 14 (second TFT 15) in the non-display area NAA are shown. Figure 4 As shown in the right figure of , a first TFT 27 is provided in the display area AA of the array substrate 21. The first TFT 27 has a first gate electrode 27E, a second gate electrode 27A, a first source electrode 27B, a first drain electrode 27C and a first semiconductor film 27D. The first semiconductor film 27D is located on the upper layer side than the second gate electrode 27A and is located on the lower layer side than the first source electrode 27B, the first drain electrode 27C and the first gate electrode 27E. Therefore, the first semiconductor film 27D is sandwiched from the top and bottom by the two gate electrodes 27A and 27E, and the first TFT 27 has a double-gate structure. By adopting the double-gate structure, a channel region can be stably generated on the first semiconductor film 27D.

[0028] like Figure 4 As shown in the left figure of FIG. 2 , a second TFT 15 is provided in the non-display area NAA of the array substrate 21. The second TFT 15 has a third gate electrode 15A, a second source electrode 15B, a second drain electrode 15C, and a second semiconductor film 15D. The second semiconductor film 15D is located at the bottom layer side relative to each electrode 15A to 15C. Therefore, the second TFT 15 has a top gate structure.

[0029] The array substrate 21 includes the above-mentioned two types of TFTs 15 and 27, and is formed by laminating various films on a glass substrate 21GS (an example of an insulating substrate). The glass substrate 21GS includes, for example, alkali-free glass as a main material. On the array substrate 21, a first light shielding portion 40 and a second light shielding portion 16 composed of a light shielding film, a primer film 29, a second semiconductor film 15D, a gate insulating film 30, a third gate electrode 15A and a second gate electrode 27A composed of a first metal film, a first insulating film 31, a first semiconductor film 27D, an auxiliary film 32 composed of a first transparent conductive film, a second insulating film 33, a first gate electrode 27E composed of a second metal film, a third insulating film 34, a first source electrode 27B, a first drain electrode 27C, a second source electrode 15B and a second drain electrode 15C composed of a third metal film, a planarizing film 37, a pixel electrode 28 composed of a second transparent conductive film, a fourth insulating film 38, and a common electrode 39 composed of a third transparent conductive film are stacked in order from the lower layer side (glass substrate 21GS side). In addition, an alignment film is applied to the uppermost layer (the layer closest to the liquid crystal layer 22) of the array substrate 21 in such a manner as to cover these various stacked films.

[0030] The light-shielding film, the first metal film, the second metal film, and the third metal film are single-layer films made of one metal material or stacked films or alloys made of different kinds of metal materials, and have electrical conductivity and light-shielding properties.

[0031] The first transparent conductive film, the second transparent conductive film, and the third transparent conductive film are made of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

[0032] The primer film 29, the gate insulating film 30, the first insulating film 31, the second insulating film 33, the third insulating film 34 and the fourth insulating film 38 are composed of inorganic materials (inorganic resin materials), for example, single-layer films or stacked films of SiO (silicon oxide, silicon oxide) and SiN (silicon nitride). The film thickness of the gate insulating film 30 and the second insulating film 33 is set to be, for example, in the range of about 80nm to 120nm. The second insulating film 33 serves as a gate insulating film of the first gate electrode 27E composed of the second metal film. The second insulating film 33 has a plane size overlapping with the first gate electrode 27E. The film thickness of the first insulating film 31 is larger than that of the gate insulating film 30, for example, set to be about 300nm. The film thickness of the third insulating film 34 is set to be, for example, in the range of about 500nm to 700nm.

[0033] The planarization film 37 is made of an organic material (organic resin material), for example, PMMA (acrylic resin). The film thickness of the planarization film 37 is generally larger than that of other insulating films made of inorganic materials.

[0034] The first semiconductor film 27D is made of an oxide semiconductor material. Compared with polycrystalline silicon semiconductor materials, oxide semiconductor materials have a characteristic of having a higher resistance value in a state where no voltage is applied (off state). In addition, compared with amorphous silicon semiconductor materials, oxide semiconductor materials have higher electron mobility.

[0035] As the oxide semiconductor material, for example, an oxide semiconductor material containing at least one metal element of In, Ga and Zn can be used. The oxide semiconductor material can be amorphous or crystalline, for example, an In-Ga-Zn-O type semiconductor (for example, indium gallium zinc oxide). In addition, for example, In-Sn-Zn-O type semiconductors (such as In2O3-SnO2-ZnO; InSnZnO), In-W-Zn-O type semiconductors, In-W-Sn-Zn-O type semiconductors, In-Al-Zn-O type semiconductors, In-Al-Sn-Zn-O type semiconductors, Zn-O type semiconductors, In-Zn-O type semiconductors, Zn-Ti-O type semiconductors, Cd-Ge-O type semiconductors, Cd-Pb-O type semiconductors, CdO (cadmium oxide), Mg-Zn-O type semiconductors, In-Ga-Sn-O type semiconductors, In-Ga-O type semiconductors, Zr-In-Zn-O type semiconductors, Hf-In-Zn-O type semiconductors, Al-Ga-Zn-O type semiconductors, Ga-Zn-O semiconductors and In-Ga-Zn-Sn-O type semiconductors are used.

[0036] The second gate electrode 27A is formed of a first metal film and is arranged to overlap the first semiconductor film 27D on the lower layer side via the first insulating film 31. The second gate electrode 27A is arranged to overlap the center portion of the first semiconductor film 27D.

[0037] The first gate electrode 27E is composed of a second metal film. The first gate electrode 27E is arranged on the upper side of the first semiconductor film 27D via the second insulating film 33. The first gate electrode 27E is arranged to overlap with the central part of the first semiconductor film 27D. The first gate electrode 27E has a smaller plane size than the second gate electrode 27A and is arranged to overlap with the central part of the second gate electrode 27A.

[0038] The first gate electrode 27E and the second gate electrode 27A are connected to each other. At least one of the gate electrodes 27A and 27E is connected to the gate wiring 25 (see Figure 3 ) are connected. Therefore, the scanning signal supplied to the gate wiring 25 is supplied to the gate electrodes 27A and 27E, and they have the same potential. When the scanning signal is supplied to the gate electrodes 27A and 27E, a channel region is generated in the first semiconductor film 27D.

[0039] The first source electrode 27B and the first drain electrode 27C are formed of a third metal film. The first source electrode 27B partially overlaps one end of the first semiconductor film 27D, and the first drain electrode 27C partially overlaps the other end of the first semiconductor film 27D. The first source electrode 27B overlaps the source wiring 26 (see Figure 3 ) are connected.

[0040] The upper portions of the first source electrode 27B and the first drain electrode 27C are arranged on the upper side relative to the first semiconductor film 27D via the third insulating film 34. A first contact hole 36 is formed on the third insulating film 34. The first contact hole 36 is arranged at a position where the first source electrode 27B and the first drain electrode 27C overlap with the first semiconductor film 27D, respectively, and do not overlap with the first gate electrode 27E. The first source electrode 27B and the first drain electrode 27C are connected to the auxiliary film 32 (filled in the first contact hole 36) through the first contact hole 36, and are connected to the first semiconductor film 27D through the auxiliary film 32.

[0041] The auxiliary film 32 is composed of a first transparent conductive film. Figure 5 As shown in FIG. 1 , the auxiliary film 32 is provided between the lower surface 27B1 of the first source electrode 27B and the first semiconductor film 27D, and between the lower surface 27C1 of the first drain electrode 27C and the first semiconductor film 27D. Therefore, the auxiliary film 32 is arranged at a position overlapping with the lower surface 27B1 of the first source electrode 27B and the lower surface 27C1 of the first drain electrode 27C, and not overlapping with the first gate electrode 27E and the second insulating film 33. The auxiliary film 32 according to the present embodiment serves as a stop film for suppressing the etching of the first semiconductor film 27D on the lower side of the first contact hole 36 (over-etching) when the first contact hole 36 is formed by etching.

[0042] The auxiliary film 32 involved in this embodiment has a protection portion 32A and an extension portion 32B. The protection portion 32A overlaps with the lower surface 27B1 of the first source electrode 27B and the lower surface 27C1 of the first drain electrode 27C, and is located between these lower surfaces 27B1, 27C1 and the first semiconductor film 27D to protect the first semiconductor film 27D. The extension portion 32B is a portion extending from the protection portion 32A to the opposite side of the first gate electrode 27E. The extension portion 32B becomes a margin for corresponding to the deviation of the plane pattern in manufacturing and the positional offset between the plane patterns of each part. As described later, by providing the extension portion 32B, for example, when forming the first contact hole 36, it is easy to deal with the positional offset with the first semiconductor film 27D.

[0043] The pixel electrode 28 is formed of a second transparent conductive film. The upper portion of the pixel electrode 28 is overlapped with the first drain electrode 27C. A contact hole 35 is provided on the planarization film 37 between the pixel electrode 28 and the first drain electrode 27C, and the pixel electrode 28 is connected to the first drain electrode 27C through the contact hole 35.

[0044] The common electrode 39 is composed of a third transparent conductive film. The common electrode 39 is overlapped with all the pixel electrodes 28 and arranged on the upper side via the fourth insulating film 38. A plurality of slits 39A are respectively opened and formed in the portions of the common electrode 39 that overlap with the plurality of pixel electrodes 28. A common potential signal as a common potential (reference potential) is supplied to the common electrode 39. When the pixel electrode 28 is charged to a potential based on the image signal transmitted to the source wiring 26 in association with the driving of the first TFT 27, a potential difference is generated between the pixel electrode 28 and the common electrode 39. Thus, a fringe electric field (oblique electric field) is generated between the opening edge of the slit 39A in the common electrode 39 and the pixel electrode 28, and the electric field includes a component in the normal direction relative to the board surface of the array substrate 21 in addition to a component along the board surface of the array substrate 21. The fringe electric field can control the alignment state of the liquid crystal molecules contained in the liquid crystal layer 22. That is, the operation mode of the liquid crystal panel 11 involved in this embodiment is the FFS (Fringe Field Switching) mode.

[0045] In addition, in the display area AA, a first light shielding portion 40 is provided at a position overlapping at least the entire area of ​​the first gate electrode 27E. The first light shielding portion 40 is composed of a light shielding film located at the bottom layer of the film provided by the array substrate 21. The first light shielding portion 40 is overlapped with most of the second gate electrode 27A. The first light shielding portion 40 is overlapped on the lower layer side with respect to each channel region in the first semiconductor film 27D generated as a voltage is applied to the first gate electrode 27E and the second gate electrode 27A. Thus, the first light shielding portion 40 can be used to block light irradiated from the backlight device to each channel region of the first semiconductor film 27D from the lower layer side. As a result, it is possible to suppress changes in the characteristics of the first TFT 27 that may occur when light is irradiated to each channel region of the first semiconductor film 27D.

[0046] Next, refer to Figure 4 The cross-sectional structure of the second TFT 15 of the circuit portion 14 is described. As described above, the second TFT 15 has a third gate electrode 15A, a second source electrode 15B, a second drain electrode 15C, and a second semiconductor film 15D. The second semiconductor film 15D is located at the bottom layer side relative to each electrode 15A to 15C. The second semiconductor film 15D is made of a crystalline polycrystalline silicon semiconductor material produced by a known method such as laser crystallization. Polycrystalline silicon semiconductor materials have higher electron mobility than oxide semiconductor materials.

[0047] The third gate electrode 15A is formed of a portion of the first metal film that is different from the second gate electrode 27A. Therefore, since the third gate electrode 15A of the second TFT 15 and the second gate electrode 27A of the first TFT 27 are both formed of the first metal film, the number of metal film layers can be reduced compared to the case where these electrodes are formed of different metal films for each TFT 15, 27. The third gate electrode 15A is arranged on the upper side with respect to the second semiconductor film 15D via the gate insulating film 30. The first gate electrode 15A is arranged to overlap the central portion of the second semiconductor film 15D.

[0048] The second source electrode 15B and the second drain electrode 15C are formed of a portion of the third metal film that is different from the first source electrode 27B and the first drain electrode 27. Therefore, the second source electrode 15B and the second drain electrode 15C of the second TFT 15, and the first source electrode 27B and the first drain electrode 27C of the first TFT 27 are formed of the third metal film, so that the number of metal film layers can be reduced compared to the case where these electrodes are formed of different metal films for each TFT 15, 27. The second source electrode 15B overlaps with a portion of one end side of the second semiconductor film 15D, and the second drain electrode 15C overlaps with a portion of the other end side of the second semiconductor film 15D.

[0049] Parts of the second source electrode 15B and the second drain electrode 15C are arranged on the upper side relative to the second semiconductor film 15D via the gate insulating film 30, the first insulating film 31, and the third insulating film 34. The second contact hole 18 is formed in the gate insulating film 30, the first insulating film 31, and the third insulating film 34. The second contact hole 18 is arranged at a position where the second source electrode 15B and the second drain electrode 15C overlap with the second semiconductor film 15D and do not overlap with the third gate electrode 15A. The second source electrode 15B and the second drain electrode 15C are connected to the second semiconductor film 15D through the second contact hole 18 (filled in the second contact hole 18).

[0050] In addition, in the circuit portion 14, a second light shielding portion 16 is provided at least at a position overlapping with the third gate electrode 15A. The second light shielding portion 16 is composed of a portion of the light shielding film that is different from the first light shielding portion 40. The second light shielding portion 16 is arranged on the lower layer side to overlap with the channel region in the second semiconductor film 15D that is generated when a voltage is applied to the third gate electrode 15A. Thus, the second light shielding portion 16 can block light irradiated from the backlight device to the channel region of the second semiconductor film 15D from the lower layer side. As a result, it is possible to suppress the change in the characteristics of the second TFT 15 that may occur when light is irradiated to the channel region of the second semiconductor film 15D.

[0051] Next, a method for manufacturing the array substrate 21 is described. Figure 4The stacking process of the cross-section shown in FIG. 6A to 6F , the manufacturing process from the formation of the first insulating film 31 to the formation of the planarizing film 37 is described in detail.

[0052] The first semiconductor film 27D is patterned on the first insulating film 31 ( Fig. 6A ), a transparent conductive film L1 ( Figure 6B The transparent conductive film L1 after film formation is patterned to form an auxiliary film 32 ( Figure 6C Next, a second insulating film 33 and a first gate electrode 27E are patterned on the first semiconductor film 27D, and then a third insulating film 34 is formed ( Fig.6D ).

[0053] Here, "pattern formation" refers to film processing based on general photolithography. Specifically, it means forming a photoresist film on the film to be processed, exposing the photoresist film via a photomask having a predetermined pattern using an exposure device, developing the photoresist film, and etching the film to be processed via the developed photoresist film.

[0054] Next, the first contact hole 36 and the second contact hole 18 are formed together in the same process. Fig. 6E ). The first contact hole 36 is formed by etching and patterning the third insulating film 34, and the auxiliary film 32 becomes a stopper film for etching. The second contact hole 18 is formed by etching and patterning the third insulating film 34, the first insulating film 31, and the gate insulating film 30 from the upper layer side, and the second semiconductor film 15D becomes a stopper film for etching.

[0055] After forming the first contact hole 36 and the second contact hole 18, the first source electrode 27B, the first drain electrode 27C, the second source electrode 15B and the second drain electrode 15C are patterned. Fig. 6F ). Thus, the first source electrode 27B and the first drain electrode 27C are filled in the first contact hole 36, and the second source electrode 15B and the second drain electrode 15C are filled in the second contact hole 18. The lower surface 27B1 of the first source electrode 27B and the lower surface 27C1 of the first drain electrode 27C are in contact with and connected to the upper surface of the protective portion 32A of the auxiliary film 32. As a result, the first source electrode 27B and the first drain electrode 27C are connected to the first semiconductor film 27D via the auxiliary film 32. On the other hand, the lower surface 15B1 of the second source electrode 15B and the lower surface 15C1 of the second drain electrode 15C are in contact with the upper surface of the second semiconductor film 15D and are directly connected to the second semiconductor film 15D.

[0056] In addition, in the above-mentioned contact hole forming step ( Fig. 6E ), the first contact hole 36 and the second contact hole 18 are formed in the same process, but the lengths (depths) of the two contact holes are different. Therefore, the shorter first contact hole 36 is overetched, and its lower layer is easily corroded by the etchant. More specifically, assuming that the auxiliary film 32 is not provided, as shown in FIG. Fig. 7A and Figure 7B As shown in the manufacturing process of Comparative Example 1, the first semiconductor film 27D may be etched and the film thickness may be excessively reduced. In addition, due to etching time, positional deviation of the photomask, etc., the first contact hole 936 may penetrate the underlying first semiconductor film 27D.

[0057] In this regard, in this embodiment, if Figure 5 As shown, an auxiliary film 32 is provided on the first semiconductor film 27D, and the first semiconductor film 27D is protected by the protective portion 32A of the auxiliary film 32. As a result, it is possible to suppress the excessive reduction in the film thickness of the first semiconductor film 27D or the penetration of the first semiconductor film 27D due to over-etching of the first contact hole 36. As a result, the first contact hole 36 and the second contact hole 18 can be appropriately formed in the same process, and the number of times the insulating film (the third insulating film 34, the first insulating film 31, and the gate insulating film 30) is patterned (etched) can be reduced compared to the case where they are provided in different processes, and the manufacturing process can be shortened.

[0058] In addition, the auxiliary film 32 is composed of the first transparent conductive film and has no light shielding property. Therefore, even if the plane size of the auxiliary film 32 is formed larger in consideration of manufacturing variations, the auxiliary film 32 can suppress the decrease in the aperture ratio. Therefore, according to the auxiliary film 32, the decrease in the aperture ratio can be suppressed and the first semiconductor film 27D of the first TFT 27 can be protected.

[0059] In addition, the extension 32B of the auxiliary film 32 can easily cope with the positional deviation from the first semiconductor film 27D when forming the first contact hole 36. Fig. 7A and Figure 7B As shown in the manufacturing process of Comparative Example 1, if the first contact hole 936 is formed with a position shift, it may penetrate the first insulating film 31, the gate insulating film 30, and the primer film 29 on the lower layer side of the first semiconductor film 27D. Therefore, in order to protect the glass substrate 21GS from the overetching of the first contact hole 936, the plane size of the first light shielding portion 940 must be formed larger than the first semiconductor film 27D. As a result, the actual situation is that the aperture ratio is reduced due to the first light shielding portion 940 with a large plane size.

[0060] On the other hand, in this embodiment, even if the first contact hole 936 and the first semiconductor film 27D are offset from each other (see Fig. 6E The single dotted line of the auxiliary film 32 can also suppress over-etching of the first contact hole 936 by the extension 32B of the auxiliary film 32. Therefore, it is not necessary to form the plane size of the first light shielding portion 40 larger than the first semiconductor film 27D, and it is easier to suppress the reduction of the aperture ratio. The plane size of the first light shielding portion 40 only needs to be a size that can block the light irradiated from the lower layer side to the channel region of the first semiconductor film 27D (for example, the same size as the second gate electrode 27A).

[0061] <Implementation Method 2> Reference Figures 8 to 9E The first TFT 127 of the array substrate 121 according to the second embodiment is described. The first TFT 127 is different from the first embodiment in that the auxiliary film 132 is provided in the lower layer of the first semiconductor film 127D and is made of the same material as the first semiconductor film 127D. In the second embodiment, the same reference numerals are used for the same structure, function, and effect as those in the first embodiment, and repeated descriptions are omitted.

[0062] The auxiliary film 132 is provided in the lower layer of the first semiconductor film 127D, at the portions overlapping the lower surface 27B1 of the first source electrode 27B and the lower surface 27C1 of the first drain electrode 27C. Since the auxiliary film 132 is made of the same material as the first semiconductor film 127D, the portion of the first semiconductor film 127D in this embodiment that overlaps with the auxiliary film 132 is thickened.

[0063] In this way, even when the film thickness of the first semiconductor film 127D is reduced due to over-etching of the first contact hole 36 , the reduction can be compensated by the auxiliary film 132 .

[0064] Next, a method for manufacturing the array substrate 121 is described. A semiconductor film L11 ( Fig.9A The semiconductor film L11 is made of the same material as the first semiconductor film 127D. The semiconductor film L11 after film formation is patterned to form an auxiliary film 132 ( Fig. 9B A semiconductor film L12 made of a semiconductor material is formed on the auxiliary film 132 ( Fig. 9C The formed semiconductor film L12 is patterned to form a first semiconductor film 127D ( Fig.9D Next, a second insulating film 33 and a first gate electrode 27E are patterned on the first semiconductor film 127D, and then a third insulating film 34 is formed, and a first contact hole 36 and a second contact hole 18 are formed in the same process ( Fig.9E ).

[0065] The first contact hole 36 is formed by etching and patterning the third insulating film 34, and the first semiconductor film 127D serves as a stopper film for etching. Fig.9E As shown, even when the film thickness of the first semiconductor film 127D is reduced due to overetching of the first contact hole 36, the reduction can be compensated by the auxiliary film 132. In this way, by forming the auxiliary film 132 with the same material as the first semiconductor film 127D, the characteristics of the first TFT 127 can be suppressed from changing due to the configuration of the auxiliary film 132.

[0066] In addition, when the auxiliary film 132 and the first semiconductor film 127D are made of the same material, assuming that the auxiliary film 132 is provided on the upper layer of the first semiconductor film 127D as in the first embodiment, when the auxiliary film 132 is etched and patterned, the portion of the first semiconductor film 127D that does not overlap with the auxiliary film 132 is also etched. In this regard, in the present embodiment, the auxiliary film 132 is disposed on the lower layer side of the first semiconductor film 127D, and such a situation can be avoided.

[0067] <Other embodiments> The technology described in the present application specification is not limited to the embodiments described in the above description and drawings, and for example, the following embodiments are also included in the technical scope of the present invention.

[0068] (1) Fig.10 As shown, the auxiliary film 232 involved in the first embodiment only needs to have at least the protection portion 32A, and may not have the extension portion 32B. In this case, it is preferred that the plane size of the first light shielding portion 240 is larger. In this way, it becomes easy to suppress the situation where the characteristics of the first TFT 27 are changed due to the configuration of the auxiliary film 232.

[0069] (2) The material of the auxiliary films 32 and 232 according to the first embodiment and the above (1) is not limited to the transparent conductive material, but may be a semiconductor material different from that of the first semiconductor film 27D.

[0070] (3) The layer structure and layout pattern of the array substrates 21 and 121 are not limited to those shown in the figure. For example, the array substrates 21 and 121 may also include wiring for realizing a touch panel function.

[0071] (4) The driving method of the liquid crystal panel 11 is not limited to the FFS mode, and may be other methods such as the IPS (In Plane Switching) mode. In addition, the common electrode 39 may be provided on the counter substrate 20 depending on the driving method.

[0072] (5) This technology can also be applied to other types of display panels such as organic EL panels. Description of Reference Numerals

[0073] 11…liquid crystal panel (display panel), 22…liquid crystal layer, 21, 121…array substrate, 20…counter substrate, 21GS…glass substrate (insulating substrate), 15…second TFT (thin film transistor), 15A…third gate electrode, 15B…second source electrode, 15C…second drain electrode, 15D…second semiconductor film, 27, 127…first TFT, 27A…second gate electrode, 27B…second source electrode, 27B1…lower surface, 27C…second drain electrode, 27C1…lower surface, 27D, 127D…first semiconductor film, 27E…first gate electrode, 30…gate insulating film, 31…first insulating film, 32, 132, 232…auxiliary film, 33…second insulating film, 34…third insulating film, 40…first light shielding portion.

Claims

1. An array substrate, characterized in that: A first TFT is included, wherein the first TFT has: A first insulating film disposed on an upper layer side of the insulating substrate; a first semiconductor film disposed on an upper layer of the first insulating film; a second insulating film disposed on an upper layer of the first semiconductor film; a first gate electrode disposed on an upper layer of the second insulating film and overlapping the first semiconductor film; a third insulating film disposed on an upper layer of the first gate electrode; A first source electrode and a first drain electrode are formed of a metal film disposed on an upper layer of the third insulating film and are connected to the first semiconductor film through a first contact hole penetrating the third insulating film; as well as The auxiliary film is disposed on an upper layer or a lower layer of the first semiconductor film, at least at a position overlapping with the lower surfaces of the first source electrode and the first drain electrode, and is made of a non-metallic material.

2. The array substrate according to claim 1, characterized in that: The auxiliary film is disposed on the upper layer of the first semiconductor film and is made of a transparent conductive material.

3. The array substrate according to claim 1, characterized in that: The auxiliary film is disposed in a lower layer of the first semiconductor film and is made of the same material as that of the first semiconductor film.

4. The array substrate according to any one of claims 1 to 3, characterized in that: A first light shielding portion is included on the lower layer side of the first insulating film, The first light shielding portion overlaps with the first gate electrode, but does not overlap with the lower surfaces of the first source electrode and the first drain electrode.

5. The array substrate according to any one of claims 1 to 3, characterized in that: The first TFT is a dual-gate structure TFT further including a second gate electrode, and the second gate electrode is disposed in a lower layer of the first insulating film.

6. The array substrate according to claim 5, characterized in that: Also included is a second TFT, wherein the second TFT has: a second semiconductor film; a gate insulating film disposed on an upper layer of the second semiconductor film; a third gate electrode, which is disposed on an upper layer of the gate insulating film and is made of the same material as the second gate electrode; The first insulating film is disposed on an upper layer of the third gate electrode; The third insulating film is disposed on an upper layer of the first insulating film; as well as A second source electrode and a second drain electrode are connected to the second semiconductor film from an upper layer of the third insulating film through a second contact hole penetrating the third insulating film, the first insulating film, and the gate insulating film, The first semiconductor film of the first TFT is made of an oxide semiconductor material, The second semiconductor film of the second TFT is made of a polysilicon semiconductor material.

7. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 3; A relative substrate, arranged relative to the array substrate in a form of having an internal space therebetween; as well as A liquid crystal layer is sealed in the internal space.

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