Optical proximity correction method and computer readable storage medium

Abstract

The invention provides an optical proximity correction method and a computer readable storage medium, and is applied to the technical field of semiconductors. According to the invention, after first optical proximity correction is carried out on all main graphs in an original layout to obtain a first corrected layout, at least one main graph with splicing defects can be screened out from the first corrected layout, and optical proximity correction is carried out on the screened main graph again to obtain a second corrected graph; in other words, optical proximity correction is carried out on part of the main patterns in the original layout again, so that the number of iterations of optical proximity correction can be reduced, and the efficiency of optical proximity correction is improved. Specifically, the main patterns can be screened by utilizing a mode of judging whether the correction modes of the main patterns in related layout blocks are the same or not, and then behaviors and changes of the screened main patterns in different layout blocks are adjusted and unified by utilizing a mode of re-executing optical proximity correction, so that the aim of reducing edge placement errors (EPE) is fulfilled.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an optical proximity correction method and a computer-readable storage medium. Background Art

[0002] With the development of the semiconductor industry, people have increasingly stringent requirements on chip performance and energy consumption. In order to obtain chips with smaller areas, higher performance and lower energy consumption, it is necessary to further reduce the size of each graphic on the chip and the spacing between each graphic. The reduction in spacing will cause the design distance between some graphics on the layout to be less than the length of the light wave. Therefore, it is necessary to correct the layout before it is engraved on the mask to prevent the optical proximity effect (OPE) during the photolithography process and to avoid the graphics engraved on the chip being inconsistent with the design and causing graphic distortion. The technology for correcting the layout to avoid the optical proximity effect is called Optical Proximity Correction (OPC) technology.

[0003] At present, the computing power of existing EDA software and computer server clusters is not enough to support the processing of the entire chip layout at one time. Generally, the complete layout needs to be divided into micron-sized patches, and the patches are processed first, and finally the processed patch layout results are integrated (stitched) to obtain the complete layout. However, in the layout, different graphic areas of a polygonal main graphic may be divided into different patches. In this case, the polygonal main graphic can be defined as a global polygon. Since the processing between patches is distributed, it is impossible to fully and uniformly consider the behavior and changes of global polygons in different patches, which will inevitably cause the problem of poor graphic consistency at the junction of adjacent patches. Summary of the invention

[0004] The object of the present invention is to provide an optical proximity correction method and a computer-readable storage medium to reduce edge placement error (EPE), increase process window, and improve product yield.

[0005] In a first aspect, in order to solve the above technical problems, the present invention provides an optical proximity correction method, comprising: providing an initial layout, wherein the initial layout comprises a plurality of main graphics.

[0006] The initial layout is divided to obtain a plurality of layout blocks, wherein at least one of the main graphics is divided into a plurality of sub-graphics, and different sub-graphics are located in different layout blocks.

[0007] A first optical proximity correction is performed on the graphics in the plurality of layout blocks respectively, and the corrected plurality of layout blocks are spliced ​​to obtain a first corrected layout of the initial layout.

[0008] At least one first correction pattern with a splicing defect is determined from the first correction pattern, and a main pattern corresponding to the determined first correction pattern and other main patterns located around the main pattern are formed into a pattern set.

[0009] The graphic set is divided into blocks as a new layout, and a second optical proximity correction is performed on the main graphic corresponding to the first correction graphic in the graphic set to obtain a second correction graphic of the main graphic.

[0010] The first revised pattern corresponding to the main pattern determined in the first revised layout is removed, and the second revised pattern corresponding to the main pattern is backfilled to the removed position on the first revised layout to obtain a second revised layout.

[0011] In some optional examples, before the initial layout is divided, corresponding auxiliary graphics may be added in the intervals between adjacent main graphics in the initial layout according to a preset auxiliary graphic adding rule.

[0012] In some optional examples, after obtaining the second revised layout, the method may further include: Perform a graphic check on the second revised layout to determine whether the second revised layout lacks the first revised graphic or the second revised graphic corresponding to the main graphic. If so, return to the step of removing the first revised graphic corresponding to the main graphic determined in the first revised layout, and backfilling the second revised graphic corresponding to the main graphic to the removed position on the first revised layout to obtain the second revised layout.

[0013] In some optional examples, the graphic check may include: performing an XOR operation on the second revised layout and the initial layout.

[0014] In some optional examples, at least part of a line edge of the main graphic that is divided into a plurality of sub-graphics may be located in different layout blocks.

[0015] In some optional examples, the step of determining at least one first revised pattern having a splicing defect from the first revised layout may include: Determine whether the correction methods of the first optical proximity correction performed in the relevant layout blocks for the partial line edges of a line edge of the main graphic located in different layout blocks are the same; if different, the main graphic including the line edge is regarded as the main graphic with splicing defects.

[0016] In some optional examples, if the partial line edges of the main graphic located in different layout blocks are corrected in the same way as the first optical proximity correction performed in the relevant layout blocks, an intersection operation is performed on the first corrected graphic of the sub-graphic corresponding to the partial line edges in different layout blocks.

[0017] In some optional examples, the step of determining at least one first revised pattern having a splicing defect from the first revised layout may include: At least one dividing point is set on the partial line edge of the main graphic located in different layout blocks to divide the line edge into multiple sub-line segments, and it is determined whether the correction method of the first optical proximity correction performed on the sub-line segments in the relevant layout blocks is the same. If different, the main graphic including the sub-line segment is regarded as the main graphic with splicing defects.

[0018] In some optional examples, the correction method of the first optical proximity correction may include: expanding the line edge of the main graphic outward or shrinking the line edge inward in a direction perpendicular to the line edge.

[0019] In a second aspect, the present invention further provides an electronic device, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory, used to store computer programs; The processor is used to implement the above-mentioned method steps of optical proximity correction when executing the program stored in the memory.

[0020] In a third aspect, the present invention further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method steps of optical proximity correction as described above are implemented.

[0021] Compared with the prior art, the technical solution provided by the present invention has at least one of the following beneficial effects: The present invention provides an optical proximity correction method, comprising: providing an initial layout, the initial layout comprising a plurality of main graphics, dividing the initial layout to obtain a plurality of layout blocks, wherein at least one of the main graphics is divided into a plurality of sub-graphics, and different sub-graphics are located in different layout blocks, performing a first optical proximity correction on the graphics in the plurality of layout blocks respectively, and splicing the corrected plurality of layout blocks to obtain a first corrected layout of the initial layout, determining at least one first corrected graphic with a splicing defect from the first corrected layout, and forming a graphic set with a main graphic corresponding to the determined first corrected graphic and other main graphics located around the main graphic, using the graphic set as a new layout block, and performing a second optical proximity correction on the main graphic corresponding to the first corrected graphic in the graphic set to obtain a second corrected graphic of the main graphic, removing the first corrected graphic corresponding to the main graphic determined in the first corrected layout, and backfilling the second corrected graphic corresponding to the main graphic to the removed position on the first corrected layout to obtain a second corrected layout.

[0022] In the present invention, after performing at least one optical proximity correction on all main graphics in the original layout to obtain a first corrected layout, at least one main graphic with a splicing defect is screened out from the first corrected layout, and the screened main graphic is re-performed with optical proximity correction to obtain a second corrected graphic, that is, only part of the main graphics in the original layout is re-optically proximity corrected, such as main graphics (global polygons) in which different graphic areas are divided into different layout blocks, and an unexpected effect is obtained: the number of optical proximity correction iterations of the original layout can be reduced, that is, the efficiency of the optical proximity correction is improved; wherein, the screened main graphics can be re-performed in the first corrected layout. The corresponding first correction graphic in the revised layout is replaced by the second correction graphic, so as to utilize the first correction graphic of part of the main graphics and the second correction graphic of at least one of the main graphics to form a final revised layout of the original layout, and obtain an unexpected effect: utilizing whether the correction method of the main graphics in the relevant layout blocks is the same to determine whether the behavior and changes of the main graphics, such as the global polygon, in different layout blocks are unified, and utilizing the method of re-executing the optical proximity correction to adjust and unify the behavior and changes of the main graphics in different layout blocks, thereby achieving the purpose of reducing the edge placement error EPE, increasing the process window, and improving the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings: Figure 1FIG. 4 is a flow chart of an optical proximity correction method in one embodiment of the present invention.

[0024] Figure 2 This is an example diagram of an original layout in an embodiment of the present invention.

[0025] Figure 3 In one embodiment of the present invention, Figure 2 An example diagram of a number of layout blocks obtained after the original layout is divided.

[0026] Figure 4 In one embodiment of the present invention Figure 3 An enlarged example of a local shape of the global polygon is shown.

[0027] Figure 5 In one embodiment of the present invention Figure 4 An example diagram of a target layout corresponding to a local graphic of the global polygon shown.

[0028] Figure 6 In one embodiment of the present invention Figure 4 The local graphics of the global polygon shown is an example of a first corrected graphic after an optical proximity correction is performed according to the layout blocks in which it is located.

[0029] Figure 7 In one embodiment of the present invention Figure 4 The local graphics of the global polygon shown is an example of a first corrected graphics after an optical proximity correction is performed according to another layout block.

[0030] Figure 8 In one embodiment of the present invention, Figures 5 to 7 An example of a graph obtained by superimposing the graphs shown.

[0031] Fig. 9 In one embodiment of the present invention Figure 4 The local graphics implementation of the global polygon shown Figure 1 An example diagram of the second correction pattern after the optical proximity correction method is shown.

[0032] Wherein, the accompanying drawings are marked as follows: 100-original layout, 101-global polygon, 102-other main graphics, 10 / 10a~10c-layout blocks, AA-dividing line, 1011-sub-graphics, 101a-one line edge of the global polygon, 101b-another line edge of the global polygon, S1-target layout of the local graphics of the global polygon, S2 / S3-the first corrected graphics after an optical proximity correction is performed on the local graphics of the global polygon according to different layout blocks, S4-the second corrected graphics after a second optical proximity correction is performed on the local graphics of the global polygon.

[0033] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0034] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0035] Layout refers to mapping the circuit design circuit diagram or circuit description language to the physical description level, so that the designed circuit can be mapped to the wafer for production. Layout is a graphic containing relevant physical information such as the device type, device size, relative position between devices, and connection relationship between each device of the integrated circuit. These graphics are composed of graphics located on different drawing layers. For example, the layout usually includes a through-hole layer, a metal wire layer, an insulating layer, a contact layer, a packaging layer, etc. Among them, the metal wire layer (Metal Layer) is mainly used to realize the circuit connection inside the chip. Metal wires are generally made of metal materials such as copper and aluminum. Therefore, the metal wire layer usually involves the problem of global polygons. The present invention needs to properly handle the global polygons during the optical proximity correction process so that the global polygons can be stitched (spliced) normally after distributed operation.

[0036] The existing optical proximity correction method is to divide the entire layout into multiple adjacent blocks, and the polygons belonging to the same block perform OPC operations (optical proximity correction operations) on a separate central processing unit (CPU). After the OPC calculations of all the blocks are completed, the different blocks are then merged into a complete layout. If the correction graphics after the OPC operation of at least a part of at least one line edge of the global polygon in different layout blocks are directly overlapped according to the existing technology to serve as the complete layout after splicing, it is bound to be impossible to fully and uniformly consider the behavior and changes of the global polygon in different layout blocks, that is, the same part of the same line edge of the global polygon will be subjected to OPC operations with different correction rules or correction methods in different layout blocks. Therefore, improper stitching (stitching or integration) due to inconsistency often occurs near the spliced ​​layout blocks, resulting in weaknesses that are difficult to solve, such as large edge placement error EPE and small process window.

[0037] In order to solve the above problems, the present invention provides an optical proximity correction method and a computer-readable storage medium to reduce edge placement error EPE, increase process window, and improve product yield.

[0038] Please refer to Figure 1 , which is a schematic diagram of the process flow of an optical proximity correction method in one embodiment of the present invention. Figure 1 As shown, the optical proximity correction method may include at least the following steps: Step S101, providing an initial layout, wherein the initial layout includes a plurality of main graphics.

[0039] Step S102, dividing the initial layout to obtain a plurality of layout blocks, wherein at least one of the main graphics is divided into a plurality of sub-graphics, and different sub-graphics are located in different layout blocks.

[0040] Step S103, performing a first optical proximity calibration on the graphics in the plurality of layout blocks respectively, and splicing the corrected plurality of layout blocks to obtain a first corrected layout of the initial layout.

[0041] Step S104, determining at least one first correction pattern with a splicing defect from the first correction pattern, and forming a pattern set with a main pattern corresponding to the determined first correction pattern and other main patterns located around the main pattern.

[0042] Step S105 , dividing the graphic set into a new layout block, and performing a second optical proximity calibration on the main graphic corresponding to the first corrected graphic in the graphic set to obtain a second corrected graphic of the main graphic.

[0043] Step S106, removing the first revised pattern corresponding to the main pattern determined in the first revised layout, and backfilling the second revised pattern corresponding to the main pattern to the removed position on the first revised layout to obtain a second revised layout.

[0044] In the present invention, at least one of the main figures in the initial layout is a global polygon. When the global polygon is divided into different layout blocks, at least a portion of at least one line edge of the global polygon (also referred to as a part of the line edge) will be divided into different layout blocks at the same time, so that when the first optical proximity correction operation (hereinafter referred to as the first OPC operation) is performed on a CPU in all layout blocks, at least a portion of at least one line edge of the global polygon (or a part of the line edge) will be subjected to different first OPC operations in different layout blocks (for example, an outward expansion process is performed in one layout block, and an inward contraction process is performed in another layout block), so that after the first OPC operation is performed, by determining the same part of the same line edge of the global polygon (on a certain line edge) The global polygon with inconsistent stitching problem is screened out from the initial layout in a way that determines whether the OPC operation methods performed on the same part of the line edge) in different layout blocks are consistent, and then the global polygon and at least one other main graphic around it are used as a new layout block (also called a new layout block). That is, the present invention will not divide the screened global polygon into layouts when performing the second OPC operation. Therefore, the second corrected graphic obtained after the second OPC operation of the screened global polygon will definitely not have the problem of inconsistent correction methods or correction rules of the second OPC operation performed on the same part of the same line edge, thereby reducing the edge placement error EPE of the global polygon and increasing the process window.

[0045] A specific embodiment of the present invention is described below with reference to the drawings.

[0046] Please refer to Figure 2 , what is drawn is an example diagram of the original layout in one embodiment of the present invention.

[0047] like Figure 2 As shown, in the above step S101, an original layout 100 may be provided first, wherein the original layout 100 includes a plurality of main graphics, and the plurality of main graphics include at least a global polygon 101 and other main graphics 102 surrounding the global polygon 101. The interval between the global polygon 101 and other main graphics 102 (the area corresponding to the spacing between the two) may be used as an area for adding auxiliary graphics. Then, in other optional examples, a preset auxiliary graphics adding rule may be further utilized, for example, based on the interval length between the global polygon 101 and other main graphics 102, or the interval length between adjacent other main graphics 102, at least one auxiliary graphic (not shown) is set in the interval, such as an auxiliary graphic in the shape of a grid bar, but not limited thereto.

[0048] Please refer to Figure 3, which is shown in one embodiment of the present invention. Figure 2 An example diagram of several layout blocks obtained by segmenting the original layout shown in FIG. Figure 3 As shown, in the above step S102, a plurality of mutually spaced dividing lines AA may be sequentially set on the original layout 100 along the longitudinal direction and / or the transverse direction to divide the original layout 100 into at least two layout blocks 10. In one embodiment, the intervals between the plurality of dividing lines AA along the longitudinal direction and / or the transverse direction may be the same or different, so that the sizes or areas of the plurality of layout blocks 10 may be the same or different. For example, in the embodiment of the present invention, the original layout 100 is spaced along the longitudinal direction (e.g. Figure 3 The original layout 100 is divided into two parts (in the Y direction), and at least some of the layout blocks 10 have different areas or sizes, but the invention is not limited thereto. Under this setting, different graphic parts of the global polygon 101 in the original layout 100 are located in at least two different layout blocks 10, that is, in the process of dividing the original layout 100, the global polygon 101 therein will also be divided into multiple sub-graphics 1011, and different sub-graphics 1011 are located in different layout blocks 10.

[0049] Please refer to Figure 4 , which is shown in one embodiment of the present invention Figure 3 An enlarged example of a local figure of the global polygon shown in FIG. Figure 4 As shown, in the embodiment of the present invention, at least part of the main figure divided into a plurality of sub-figures 1011 is located in different layout blocks 10, for example, the same line edge of the global polygon 101 (for example Figure 4 The line edge 101a or the other line edge 101b extending in the horizontal X manner in the global polygon 101 will be divided into different layout blocks 10 at the same time. For example, the line edge 101a of the global polygon 101 will be divided into the layout block 10a and the layout block 10b at the same time, while the other line edge 101b will be divided into the layout block 10b and the layout block 10c at the same time. It should be understood that if the optical proximity correction method proposed in the embodiment of the present invention adds auxiliary graphics to the original layout 100 after providing the original layout 100 and before dividing the original layout 100, then in the process of dividing the original layout 100 in step S102, the auxiliary graphics added therein may also be divided into different layout blocks 10, which will not be repeated here.

[0050] Please refer to Figures 5 to 8 ,in Figure 5 In one embodiment of the present invention Figure 4 An example diagram of the target layout corresponding to the local graphics of the global polygon shown, Figure 6 In one embodiment of the present invention Figure 4 The local graphics of the global polygon shown is an example of a first corrected graphics after an optical proximity correction is performed according to the layout blocks in which it is located. Figure 7 In one embodiment of the present invention Figure 4 The local graphics of the global polygon shown is an example of a first corrected graphics after an optical proximity correction is performed on the local graphics according to another layout block. Figure 8 In one embodiment of the present invention, Figures 5 to 7 An example of the graph obtained by superimposing the graphs shown in the figure. Figures 5 to 8 As shown, in the above step S103, the number of layout blocks can be obtained according to step S102, and the same number of servers or processes can be set, and then each of the layout blocks 10 (for example Figure 4 The graphics contained in the different layout blocks (identified by reference numerals 10a to 10c in the figure) are respectively subjected to the first optical proximity correction, for example Figure 6 and Figure 7 In one embodiment, the step of performing the first optical proximity calibration on the graphics contained in each of the layout blocks 10 is: the line edges of the graphics contained in the layout block 10, for example Figure 4 The line edge 101a of the middle layout block 10a is cut into multiple sub-line segments along the X direction, and then each sub-line segment is expanded outward or contracted inward along the direction perpendicular to the line edge 101a (i.e., the Y direction), thereby obtaining a sub-corrected graphic after the first optical proximity correction of the graphic in each layout block 10.

[0051] Then, the sub-corrected graphics corresponding to the plurality of layout blocks 10 after the first optical proximity correction are spliced. Specifically, the sub-corrected graphics corresponding to the plurality of layout blocks 10 can be spliced ​​along the dividing line AA set when the original layout 100 is divided in step S102, so as to form a plurality of layout blocks 10. Figure 8 The first revised layout of the original layout 100 composed of the revised graphics S2 and S3 shown; wherein Figure 5 and Figure 8 S1 in Figure 4 The target graphics of the local graphics of the global polygon shown, S2 and S3 are Figure 4After the local figure of the global polygon is cut into a plurality of sub-figures 1011, the sub-figures 1011 are spliced ​​with the corresponding sub-corrected figures after the first optical proximity correction is performed on different layout blocks 10 to obtain the first corrected figure of the local figure of the global polygon. Under this setting, the optical proximity correction method of the prior art is only to stack the corrected figures corresponding to the first optical proximity correction of the global polygon after the sub-figures are cut into a plurality of sub-figures and different layout blocks are performed. Figure 6 The S2 and Figure 7 The S3 stack shown is then used to perform exposure and development respectively using the modified patterns of S2 and S3 to form corresponding patterns on the wafer. However, the embodiment of the present invention further requires performing steps S104 to S106 on the modified patterns corresponding to the S2 and S3.

[0052] It should be understood that the embodiments of the present invention Figure 6 and Figure 7 In order to distinguish the modified graphics corresponding to S2 and S3, the lines of the non-modified graphics are represented by dotted lines, but the present invention is not limited thereto. Figure 4 The line edge 101a or the other line edge 101b extending in the horizontal X manner in the global polygon 101 will be simultaneously divided into different layout blocks 10, for example, the line edge 101a of the global polygon 101 will be simultaneously divided into the layout block 10a and the layout block 10b, and the other line edge 101b will be simultaneously divided into the layout block 10b and the layout block 10c; therefore, the line edges simultaneously divided into different layout blocks 10 will undergo the first optical proximity correction respectively with the different layout blocks 10, for example, the line edge 101a or the other line edge 101b of the global polygon 101 will undergo multiple first optical proximity corrections, and the correction rules of the first optical proximity corrections performed in different layout blocks 10 (outward expansion processing or inward contraction processing) need to be based on the correction rules performed in each layout block 10, that is, the correction rules of the first optical proximity corrections performed on the same part of the same line edge in different layout blocks 10 may be the same or different.

[0053] Please continue to refer to Figures 5 to 8In the above step S104, after obtaining the first revised layout of the original layout 100, it can be determined whether the parts of the line edges of all the main graphics (global polygon 101 and other main graphics 102) on the original layout 100 located in different layout blocks 10 are corrected in the same way as the first optical proximity correction in the relevant layout blocks 10. If they are different, the main graphics containing the line edges are regarded as the main graphics with splicing defects, that is, if the correction methods of the first optical proximity correction performed on the same part of the same line edge of the main graphics in the relevant layout block 10 are respectively outward expansion processing and inward contraction processing (different correction directions), it means that the main graphics containing the line edge will have the problem of inconsistent splicing and stitching. For example, the line edge 101a or the other line edge 101b of the global polygon 101 will be subjected to multiple first optical proximity corrections in the relevant layout blocks 10 where it is located, and thus the line edge 101a or the other line edge 101b is prone to the problem of inconsistent splicing and stitching. In another embodiment, after obtaining the first revised layout of the original layout 100, at least one dividing point can be set on the parts of the line edges of all the main graphics (global polygon 101 and other main graphics 102) on the original layout 100 located in different layout blocks 10 to divide the line edges into multiple sub-line segments, and then determine whether the correction method of the first optical proximity correction performed on the sub-line segments in the relevant layout blocks is the same, so as to judge which main graphics on the original layout 100 will have splicing defects, that is, the main graphics containing the line edges will have inconsistent splicing and stitching problems; otherwise, it means that the main graphics containing the line edges will not have inconsistent splicing and stitching problems.

[0054] Next, after the main graphics with splicing defects are screened out from the original layout 100, for example, the screened out main graphics are the global polygon 101, and at least part of the other main graphics 102 located around the global polygon 101 can be further combined with the global polygon 101 into a graphics set, so as to characterize the environmental impact of other main graphics when the global polygon 101 is subjected to the second optical proximity correction through the part of other main graphics 102, but not limited to this. It should be understood that when the main graphics corresponding to the multiple first correction graphics screened out from the first correction layout all have the problem of inconsistent splicing and stitching, it is necessary to form a graphics set for the main graphics corresponding to each screened out first correction graphic and at least part of the other main graphics around it, but not limited to this.

[0055] Then, in the above step S105, for each of the graphic sets formed in step S104, each of them can be divided into blocks as a new layout, and a second optical proximity correction is performed on the main graphic (such as the global polygon 101) corresponding to the first corrected graphic with inconsistent splicing and stitching problems (splicing defects) in each of the graphic sets, so as to obtain a second corrected graphic of the main graphic (such as the global polygon 101), such as Fig. 9 S4 shown, Fig. 9 The diagram is an embodiment of the present invention. Figure 4 The local graphics implementation of the global polygon shown Figure 1 An example of a second correction pattern after the optical proximity correction method shown in FIG. Fig. 9 S1 in the figure is the target figure of the local figure of the global polygon. In the process of performing the second optical proximity correction on the selected main figure in the embodiment of the present invention, it is divided into a new layout block, that is, the selected main figure will not be divided again, but the optical proximity correction is performed as a whole, thereby avoiding the problem of reducing the edge placement error EPE and increasing the process window due to the inconsistent behavior and changes of the main figure such as the global polygon in different layout blocks.

[0056] Next, in the above step S106, the first correction graphic corresponding to the selected main graphic, such as the global polygon 101, in the first correction layout can be removed, and then the second correction graphic corresponding to the main graphic, such as the global polygon 101, can be backfilled to the removed position on the first correction layout to obtain the second correction layout. Afterwards, the second correction layout is checked to determine whether the second correction layout lacks the first correction graphic or the second correction graphic corresponding to the main graphic. If so, return to step S106, otherwise, the second correction layout is used as the target correction layout of the original layout 100, and the optical proximity correction is terminated. In one embodiment, the purpose of performing a graphic check on the second revised layout is to check whether there is a problem of missing a second revised graphic that replaces a main graphic, or replacing other first revised graphics that do not need to be replaced with a second revised graphic of another main graphic during the execution of the above-mentioned step S106. Exemplarily, the graphic check may include: performing an XOR operation on the second revised layout and the initial layout. For example, an XOR operation may be performed on the total number of main graphics corresponding to the first revised graphics and the second revised graphics contained in the second revised layout and the total number of main graphics contained in the initial layout. If the operation result is 0, the second revised layout is used as the target revised layout of the original layout 100, and the optical proximity correction is terminated. Otherwise, the execution of step S106 is returned until the operation result is 0.

[0057] In one embodiment, if it is determined in the above step S104 that the portions of the line edges of all the main graphics in the original layout 100 located in different layout blocks are corrected in the same manner as the first optical proximity correction performed in the relevant layout blocks 10, it means that the first correction graphics in the first correction layout formed do not need to be replaced, and the first correction layout, for example, Figure 8 or Figure 6 and Figure 7 The corrected graph corresponding to the sub-graph corresponding to the parts of the same line edge in S2 and S3 located in different layout blocks 10 after intersection operation is performed is used as the target corrected layout of the original layout 100, but it is not limited to this.

[0058] It is known from calculation that, using the optical proximity correction method provided by the prior art, the two horizontally extending edges of the global polygon (e.g. Figure 4 After the correction is performed on the target pattern and the corrected pattern, the edge placement errors EPE of the corresponding target pattern and the corrected pattern are 2.3 nm and 1.9 nm respectively. However, the optical proximity correction method provided in the embodiment of the present invention is used to correct the two horizontally extending edges of the same global polygon (e.g. Figure 4 After correction is made to the edge placement errors EPE of the corresponding target graphics and the corrected graphics, it is obvious that the optical proximity correction method provided by the present invention can achieve the purpose of reducing the edge placement error EPE of the global polygon and increasing the art window.

[0059] In summary, the present invention provides an optical proximity correction method, comprising: providing an initial layout, the initial layout comprising a plurality of main graphics, dividing the initial layout to obtain a plurality of layout blocks, wherein at least one of the main graphics is divided into a plurality of sub-graphics, and different sub-graphics are located in different layout blocks, performing a first optical proximity correction on the graphics in the plurality of layout blocks respectively, and splicing the corrected plurality of layout blocks to obtain a first corrected layout of the initial layout, determining at least one first corrected graphic with a splicing defect from the first corrected layout, and forming a graphic set with a main graphic corresponding to the determined first corrected graphic and other main graphics located around the main graphic, using the graphic set as a new layout block, and performing a second optical proximity correction on the main graphic corresponding to the first corrected graphic in the graphic set to obtain a second corrected graphic of the main graphic, removing the first corrected graphic corresponding to the main graphic determined in the first corrected layout, and backfilling the second corrected graphic corresponding to the main graphic to the removed position on the first corrected layout to obtain a second corrected layout.

[0060] In the present invention, after performing at least one optical proximity correction on all main graphics in the original layout to obtain a first corrected layout, at least one main graphic with a splicing defect is screened out from the first corrected layout, and the screened main graphic is re-performed with optical proximity correction to obtain a second corrected graphic, that is, only part of the main graphics in the original layout is re-optically proximity corrected, such as main graphics (global polygons) in which different graphic areas are divided into different layout blocks, and an unexpected effect is obtained: the number of optical proximity correction iterations of the original layout can be reduced, that is, the efficiency of the optical proximity correction is improved; then, the screened main graphic is re-performed with optical proximity correction in the first corrected layout. The first correction graphic corresponding to the genuine version is replaced by the second correction graphic, so as to utilize the first correction graphic of part of the main graphics and the second correction graphic of at least one of the main graphics to form a final correction layout of the original layout, and obtain an unexpected effect: utilizing the method of whether the correction method of the main graphics in the relevant layout blocks is the same to determine whether the behavior and changes of the main graphics, such as the global polygon, in different layout blocks are unified, and utilizing the method of re-executing the optical proximity correction to adjust and unify the behavior and changes of the main graphics in different layout blocks, thereby achieving the purpose of reducing the edge placement error EPE, increasing the process window, and improving the product yield.

[0061] An embodiment of the present invention further provides an electronic device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus. Memory, used to store computer programs; The processor is used to implement an optical proximity correction method provided by an embodiment of the present invention when executing a program stored in the memory.

[0062] In addition, other implementations of the optical proximity correction method implemented by the processor executing the program stored in the memory are the same as the implementations mentioned in the aforementioned method embodiment part, and will not be repeated here.

[0063] The communication bus mentioned in the above control terminal may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc.

[0064] The communication interface is used for communication between the above electronic device and other devices.

[0065] The memory may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0066] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0067] In another embodiment of the present invention, a computer-readable storage medium is provided. The computer-readable storage medium stores instructions. When the instructions are executed on a computer, the computer executes an optical proximity correction method described in any one of the above embodiments.

[0068] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0069] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0070] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, electronic device, and computer-readable storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0071] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. An optical proximity correction method, characterized in that: include: Providing an initial layout, wherein the initial layout includes a plurality of main graphics; Dividing the initial layout to obtain a plurality of layout blocks, wherein at least one of the main graphics is divided into a plurality of sub-graphics, and different sub-graphics are located in different layout blocks; Performing a first optical proximity correction on the graphics in the plurality of layout blocks respectively, and splicing the corrected plurality of layout blocks to obtain a first corrected layout of the initial layout; Determine at least one first correction pattern with a splicing defect from the first correction pattern, and form a pattern set with a main pattern corresponding to the first correction pattern and other main patterns located around the main pattern; The graphic set is divided into blocks as a new layout, and a second optical proximity correction is performed on a main graphic corresponding to the first corrected graphic in the graphic set to obtain a second corrected graphic of the main graphic; The first revised pattern corresponding to the main pattern determined in the first revised layout is removed, and the second revised pattern corresponding to the main pattern is backfilled to the removed position on the first revised layout to obtain a second revised layout.

2. The optical proximity correction method according to claim 1, wherein: Before the initial layout is divided, corresponding auxiliary graphics are added in the intervals between adjacent main graphics in the initial layout according to a preset auxiliary graphics adding rule.

3. The optical proximity correction method according to claim 1, wherein: After obtaining the second revised version, the method further includes: Perform a graphic check on the second revised layout to determine whether the second revised layout lacks the first revised graphic or the second revised graphic corresponding to the main graphic. If so, return to the step of removing the first revised graphic corresponding to the main graphic determined in the first revised layout, and backfilling the second revised graphic corresponding to the main graphic to the removed position on the first revised layout to obtain the second revised layout.

4. The optical proximity correction method according to claim 3, wherein: The graphic checking includes: performing an XOR operation on the second revised layout and the initial layout.

5. The optical proximity correction method according to claim 1, wherein: At least part of a line edge of the main graphic that is divided into a plurality of sub-graphics is located in different layout blocks.

6. The optical proximity correction method according to claim 5, wherein: The step of determining at least one first revised pattern having a splicing defect from the first revised pattern includes: Determine whether the correction methods of the first optical proximity correction performed in the relevant layout blocks for the partial line edges of a line edge of the main graphic located in different layout blocks are the same; if different, the main graphic including the line edge is regarded as the main graphic with splicing defects.

7. The optical proximity correction method according to claim 6, wherein: If the partial line edges of the main graphic located in different layout blocks are corrected in the same way as the first optical proximity correction performed in the relevant layout blocks, an intersection operation is performed on the first corrected graphics of the partial line edges in different layout blocks.

8. The optical proximity correction method according to claim 5, wherein: The step of determining at least one first revised pattern having a splicing defect from the first revised pattern includes: At least one dividing point is set on the partial line edge of the main graphic located in different layout blocks to divide the line edge into multiple sub-line segments, and it is determined whether the correction method of the first optical proximity correction performed on the sub-line segments in the relevant layout blocks is the same. If different, the main graphic including the sub-line segment is regarded as the main graphic with splicing defects.

9. The optical proximity correction method according to claim 6 or 8, characterized in that: The correction method of the first optical proximity correction includes: performing an outward expansion process or an inward contraction process on the line edge of the main pattern in a direction perpendicular to the line edge.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the optical proximity correction method according to any one of claims 1 to 9 are implemented.

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